SLG7NT4317 DIALOG

Document overview

  • Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 9

Technical content

Features

  • Low Power Consumption
  • 3.3V Supply
  • Pb-Free / RoHS Compliant
  • Halogen-Free
  • STQFN-20 Package Output Summary
  • 6 Outputs – NMOS Open Drain 1X Pin Configuration VDD V1P8S_PWRGD VDDQ_PWRGD V1P5S_PWRGD PS_ON_SW_N VDDQ_VTT 7ALL_SYS_PWRGD 11 8 9 10 20 19 18 SMC_ONOFF_N VCC0_PWRGD VCC1_PWRGD SMC_SHUTDOWN COREPWROK STARTUP_LATCH_SET STQFN-20 TOP VIEW GND DDR3_VCCA_PWROK DD3_DRAM_PWROK VR_ALW_EN PLTRST_3P3_N BC_ACOK DELAY_ALL_SYS_PWRGD SLG7NT4317V

SLG7NT4317_DS_r100 Page 2 Block Diagram

SLG7NT4317_DS_r100 Page 3 Pin Configuration Pin # Pin Name Type Pin Description

1 VDD PWR Supply Voltage

2 V1P8S_PWRGD Input Digital Input

3 VDDQ_PWRGD Input Digital Input with Schmitt Trigger

4 V1P5S_PWRGD Input Digital Input

5 PS_ON_SW_N Input Digital Input with Schmitt Trigger

6 VDDQ_VTT Input Analog Input

7 ALL_SYS_PWRGD Output NMOS Open Drain 1X

8 VCC0_PWRGD Input Digital Input

9 VCC1_PWRGD Input Digital Input

10 SMC_SHUTDOWN Input Digital Input

11 GND -- Ground

12 DDR3_VCCA_PWROK Output NMOS Open Drain 1X

13 DDR3_DRAM_PWROK Output NMOS Open Drain 1X

14 VR_ALW_EN Output NMOS Open Drain 1X

15 PLTRST_3P3_N Input Digital Input

16 BC_ACOK Input Digital Input

17 DELAY_ALL_SYS_PWRGD Input Digital Input

18 STARTUP_LATCH_SET Input Digital Input

19 COREPWROK Output NMOS Open Drain 1X

20 SMC_ONOFF_N Output NMOS Open Drain 1X

Ordering Information

SLG7NT4317V V=STQFN-20 SLG7NT4317VTR STQFN-20 – Tape and Reel (3k units)

SLG7NT4317_DS_r100 Page 4 Absolute Maximum Conditions Parameter Min. Max. Unit VHIGH to GND -0.3 7 V Voltage at input pins -0.3 7 V Current at input pin -1.0 1.0 mA Storage temperature range -65 150 °C Junction temperature -- 150 °C

Electrical Characteristics

(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3 -- 4.5 V TA Operating Temperature -40 25 85 °C IQ Quiescent Current Static inputs and outputs at VDD=4.5V -- 70 -- μA IL Input Leakage Current Leakage Current for Digital Inputs or outputs in High impedance state -1 -- 1 µA VIH HIGH-Level Input Voltage Logic Input at VDD=3.3V 1.78 -- -- V Logic Input at VDD=5V 2.64 -- -- Logic Input with Schmitt trigger at VDD=3.3V 2.13 -- -- Logic Input with Schmitt trigger at VDD=5V 3.16 -- -- VIL LOW-Level Input Voltage Logic Input at VDD=3.3V -- -- 1.21 V Logic Input at VDD=5V -- -- 1.84 Logic Input with Schmitt trigger at VDD=3.3V -- -- 0.95 Logic Input with Schmitt trigger at VDD=5V -- -- 0.78 IIH HIGH-Level Input Curr ent Logic Input Pins; V IN = 3.3 V -1.0 -- 1.0 μA IIL LOW-Level Input Current Logic Input Pins; V IN = 0 V -1.0 -- 1.0 μA VOL LOW-Level Output Voltage Open Drain, at VDD=3.3V, IOL = 3 mA, 1X Driver -- 0.08 0.147 V Open Drain, at VDD=5V, IOL = 3 mA, 1X Driver -- 0.102 0.180 IOL LOW-Level Output Current Open Drain, at VDD=3.3V, VOL = 0.4 V 1X Driver 7.313 12.37 -- mA Open Drain, at VDD=5V, VOL = 0.4 V, 1X Driver 10.82 17.38 -- VACMP Analog Comparator Threshold Voltage ACMP0 threshold including input offset, Vref variation and hysteresis at 25°C temperature 368 -- 432 mV VHYST Analog Comparator Hysteresis AC MP0, at 25°C -- 25 -- mV

SLG7NT4317_DS_r100 Page 5 VO Maximal Voltage Applied to any PIN in High-Impedance State -- -- VDD V IO Maximal Average or DC Current Per Each Side (PIN2-PIN10, PIN12-PIN20) -- -- 80 mA TDLY0 Delay0 Time At 25°C temperature 48 -- 52 ms At 0-70°C temperature range 44 -- 56 RPU Internal Pull Up Resistance On PIN5 7 10 13 k Ω RPD Internal Pull Down Resistance On PIN18 7 10 13 kΩ On PIN10 70 100 130 TSU Start up Time After VDD reaches 1.6V level -- 1 -- ms

SLG7NT4317_DS_r100 Page 6 Package Top Marking Datasheet Revision Programming Code Number Locked Status Part Code Revision Date 1.0 004 L 4317V AB 01/26/2015 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking

SLG7NT4317_DS_r100 Page 7 Package Drawing and Dimensions

20 Lead STQFN Package

JEDEC MO-220, Variation WECE

SLG7NT4317_DS_r100 Page 8 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch STQFN 20L 2x3mm 0.4P Green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W STQFN 20L 2x3mm 0.4P Green Refer to EIA-481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.3 mm3 (nominal). More information can be found at www.jedec.org.

SLG7NT4317_DS_r100 Page 9 Silego Website & Support Silego Technology Website Silego Technology provides online support via our website at http://www.silego.com/.This website is used as a means to make files and information easily available to customers. For more information regarding Silego Green products, please visit: http://greenpak.silego.com/ http://greenpak2.silego.com/ http://greenfet.silego.com/ http://greenfet2.silego.com/ http://greenclk.silego.com/ Products are also available for purchase directly from Silego at the Silego Online Store at http://store.silego.com/. Silego Technical Support Datasheets and errata, application notes and example design s, user guides, and hardware support documents and the latest software releases are available at the Silego website or can be requested directly at info@silego.com. For specific GreenPAK design or applications questi ons and support please send email requests to GreenPAK@silego.com Users of Silego products can receive assistance through several channels: Contact Your Local Sales Representative Customers can contact their local sales representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. More information rega rding your local representative is available at the Silego website or send a request to info@silego.com Contact Silego Directly Silego can be contacted directly via e-mail at info@silego.com or user submission form, located at the following URL: http://support.silego.com/ Other Information The latest Silego Technology press releases, listing of semi nars and events, listings of worldwide Silego Technology offices and representatives are all available at http://www.silego.com/ THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYST EMS ARE NOT AUTHORIZED. SILEGO TECHNOLOGY DOES NOT ASSUME ANY LIABILITY ARIS ING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE.