SLG7NT4198V DIALOG

Document overview

  • Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 9

Technical content

Features

  • Low Power Consumption
  • 3.3V Supply
  • Pb-Free / RoHS Compliant
  • Halogen-Free
  • TDFN-8 Package Pin Configuration VDD NMI_GATE MBL_PWRGD_MR_N SENSE SMC_RST_N EX_VREF SMC_INIT_CK GND TDFN-8 TOP VIEW Thermal Pad connected to GND SLG7NT4198V Output Summary
  • 1 Output – Push Pull
  • 1 Output – Open Drain

1 Hz Interrupt Generator

SLG7NT4198_DS_r100 Page 2 Pin Configuration Pin # Pin Name Type Pin Description 1 VDD Power 3.3V Supply Voltage

2 NMI_GATE Input Digital Input

3 MBL_PWRGD_MR_N Input Digital Input

4 SENSE Input Analog input

5 GND GND Ground

6 SMC_INIT_CK Output Push Pull

7 SMC_RST_N Output Open Drain

8 EX_VREF Input Analog input

Ordering Options & Configuration Part Number Package Type SLG7NT4198V V = TDFN-8 SLG7NT4198VTR VTR = TDFN-8 – Tape and Reel (3k units)

SLG7NT4198_DS_r100 Page 3 Absolute Maximum Ratings Parameter Min. Max. Unit VDD to GND -0.3 4.6 V Voltage at input pins -0.3 4.6 V Current at input pin -1.0 1.0 mA Storage temperature range -65 150 °C Junction temperature -- 150 °C

Electrical Characteristics

Symbol Parameter Condition / Note Min Typ Max Unit VDD Supply Voltage 3.0 3.3 3.6 V IQ Quiescent Current Static I nputs and Outputs -- 30 -- μA TA Operating temperature -40 25 85 °C VAIR Analog Input Voltage Range for PIN8 0 -- 1.5 V VIH HIGH-Level Input Voltage Logic Input 1.8 -- -- V VIL LOW-Level Input Voltage Logic Input -- -- 0.8 V IIH HIGH-Level Input Leakage Current Logic Input Pins; VIN=3.3V -1.0 -- 1.0 μA IIL LOW-Level Input Leakage Current Logic Input Pins; VIN=0V -1.0 -- 1.0 μA VOH HIGH-Level Output Voltage Push Pu ll Logic Level Outputs 2.4 -- -- V VOL LOW-Level Output Voltage Push Pull Logic Level Outputs -- -- 0.4 V VOL LOW-Level Output Voltage Open Drain Logic Level Outputs -- -- 0.4 V IOH HIGH-Level Output Current Push Pull -- 8 -- mA IOL LOW-Level Output Current Push Pull -- -8 -- mA IOL LOW-Level Output Current Open Drain -- 20 -- mA VOFFSET Analog Comparator Offset Voltage Analog Comparator 0 -- ±20 -- mV VHYST Analog Comparator hysteresis Analog Comparator 0 -- 50 -- mV RPULL UP Internal Pull Up Resistance Pull up on PIN3 80 100 120 k Ω TDLY0 Delay0 Time 16 20 24 ms TDLY2 Delay2 Time 1.6 2 2.4 ms TStUp Start Up Time After V DD > 2.4V -- 7 -- ms

SLG7NT4198_DS_r100 Page 4

Description

This is a special oscillator with supervisor system. Three inputs are used to control the oscillator. SENSE (PIN4) controls the voltage supply of the chip. If supply voltage decreases do wn to the threshold set by EX_VREF (PIN8), the chip disables the oscillator and sets SMC_INICK to LOW. W hen the voltage is bigger than threshold set by EX_VREF is detected on the SENSE pin, SMC_RST_N (P IN7) is set to HIGH with 20 ms delay and enables the oscillator. MBL_PWRGD_MR_N (PIN3) is used for manual reset of SM C_RST_N. Use NMI_GATE (NMI_GATE) to disable the oscillator. Typical Application Circuit SLG7NT4198 VDD data I data I/O data I/O 4 data I/O 6data I/O 7data I/O GND 100nFR1 +3.3VSENSE EX_VREF SMC_INIT_CLK SMC_RST_N NMI_GATE MBL_PGOOD_MR V_SOURCE Timing Diagrams

SLG7NT4198_DS_r100 Page 5 Package Top Marking Datasheet Revision Programming Code Number Part Code Revision Date 1.0 03 ZR B 03/04/2014

SLG7NT4198_DS_r100 Page 6 Package Drawing and Dimensions

SLG7NT4198_DS_r100 Page 7 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch TDFN 8L 2x2mm Green 8 2x2x0.75 3000 3000 178/60 42 168 42 168 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W TDFN 8L 2x2mm Green Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 4.6875 mm3 (nominal). More information can be found at www.jedec.org.

SLG7NT4198_DS_r100 Page 8 Datasheet Revision History Date Version Change 05/29/2013 0.1 New Design 07/09/2013 0.12 Jump to 0.12 version. Changed PWM frequency to 1Hz 07/09/2013 0.13 Updated Device Revision Table 07/11/2013 0.14 Changed PIN7 configuration to Open Drain 08/07/2013 0.15 Updated Device Revision Table 03/04/2014 1.0 Production Release

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