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Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 9
Technical content
Features
- Low Power Consumption
- Pb-Free / RoHS Compliant
- Halogen-Free
- STQFN-20 Package Output Summary
- 7 Outputs — Open Drain NMOS 1X Pin Configuration 11 8 9 10 20 19 18 STQFN-20 TOP VIEW VDD SLG7NT41204 GND PSEUDO_G3 PWRBTN_SW ADPTR_PRESENT_EC ADPTR_PRESENT BXT_GLK_PD SLP_S0ix_N PCH_PWROK IMVP_VR_ON VNN_COMP DDR_VR_PGD RSMRST_PWRGD SLP_S3_N THERMTRIP_N VTT_CTRL PWRBTN_EC 5VR_PGD NC VNN_PGD Silego SLG7NT41204 is a low power and small form device. The SoC is housed in a 2mm x 3mm STQFN package which is optimal for using with small devices.
SLG7NT41204_DS_r103 SLG7NT41204 Pin Configuration Pin # Pin Name Type Pin Description
1 VDD PWR Supply Voltage
2 PSEUDO_G3 Digital Input Digital Input without Schmitt trigger
3 PWRBTN_SW Digital Input Digital Input with Schmitt trigger
4 ADPTR_PRESENT_EC Digital Output Open Drain NMOS 1X
5 ADPTR_PRESENT Digital Input Digital Input without Schmitt trigger
6 BXT_GLK_PD Analog Input/Output Analog Input/Output
7 SLP_S0ix_N Digital Input Digital Input without Schmitt trigger
8 PCH_PWROK Digital Output Open Drain NMOS 1X
9 IMVP_VR_ON Digital Output Open Drain NMOS 1X
10 VNN_COMP Analog Input/Output Analog Input/Output
11 GND GND Ground
12 DDR_VR_PGD Digital Input Digital Input without Schmitt trigger
13 RSMRST_PWRGD Digital Input Digital Input without Schmitt trigger
14 SLP_S3_N Digital Input Digital Input without Schmitt trigger
15 THERMTRIP_N Analog Input/Output Analog Input/Output
16 NC -- Keep Floating or Connect to GND
17 VNN_PGD Digital Output Open Drain NMOS 1X
18 VTT_CTRL Digital Output Open Drain NMOS 1X
19 PWRBTN_EC Digital Output Open Drain NMOS 1X
20 5VR_PGD Digital Output Open Drain NMOS 1X
Ordering Information
SLG7NT41204V V=STQFN-20 SLG7NT41204VTR VTR=STQFN-20 – Tape and Reel (3k units)
SLG7NT41204_DS_r103 SLG7NT41204 Absolute Maximum Conditions Parameter Min. Max. Unit VHIGH to GND -0.3 7 V Voltage at input pins -0.3 7 V Current at input pin -1.0 1.0 mA Storage temperature range -65 125 °C Junction temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1300 -- V Moisture Sensitivity Level 1
Electrical Characteristics
(@ 25°C, unless otherwise stated) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 4.5 5 5.5 V TA Operating Temperature -40 25 85 °C IQ Quiescent Current Static inputs and outputs -- 95 -- µA VO Maximal Voltage Applied to any PIN in High-Impedance State -- -- VDD V IO Maximal Average or DC Current (note 1) Per Each Chip Side (PIN2-PIN10, PIN12-PIN20) -- -- 90 mA VIH HIGH-Level Input Voltage Logic Input, at VDD=5.0V 2.64 -- VDD V Logic Input with Schmitt Trigger, at VDD=5.0V 3.16 -- VDD VIL LOW-Level Input Voltage Logic Input, at VDD=5.0V -- -- 1.84 V Logic Input with Schmitt Trigger, at VDD=5.0V -- -- 1.51 IIH HIGH-Level Input Current Logic Input PINs; VIN = VDD -1.0 -- 1.0 µA IIL LOW-Level Input Current Logic Input PINs; VIN = 0V -1.0 -- 1.0 µA VOL LOW-Level Output Voltage Open Drain, IOL = 5mA, 1X Driver, at VDD=5.0 V -- 0.102 0.180 V IOL LOW-Level Output Current Open Drain, VOL =0.4V, 1X Driver, at VDD=5.0 V 10.82 17.38 -- mA VACMP0 Analog Comparator Threshold Voltage ACMP0 threshold including input offset, reference voltage variation and hysteresis, at temperature 25°C. 1184 -- 1219 mV ACMP0 threshold including input offset, reference voltage variation and hysteresis, at temperature -40°C +85°C (note 1) 1133 -- 1245 VACMP1 Analog Comparator Threshold Voltage ACMP1 threshold including input offset, reference voltage variation and hysteresis, at temperature 25°C. 568 -- 633 mV
SLG7NT41204_DS_r103 SLG7NT41204 ACMP1 threshold including input offset, reference voltage variation and hysteresis, at temperature -40°C +85°C (note 1) 548 -- 645 VACMP3 Analog Comparator Threshold Voltage ACMP3 threshold including input offset, reference voltage variation and hysteresis, at temperature 25°C. 777 -- 823 mV ACMP3 threshold including input offset, reference voltage variation and hysteresis, at temperature -40°C +85°C (note 1) 746 -- 838 VHYST Analog Comparator Hysteresis Voltage (note 1) ACMP 3 -- 25 -- mV ACMP 1 -- 50 -- TDLY3 Delay3 Time At temperature 25°C 116.56 140 164.7 µs At temperature -40°C +85°C (note 1) 104.85 140 194.48 TDLY5 Delay5 Time At temperature 25°C 271.99 300 329.4 µs At temperature -40°C +85°C (note 1) 244.67 300 388.95 TSU Start up Time From VDD rising past 1.6V -- 0.3 -- ms 1. Guaranteed by Design.
SLG7NT41204_DS_r103 SLG7NT41204 Timing Diagram
SLG7NT41204_DS_r103 SLG7NT41204 Package Top Marking Datasheet Revision Programming Code Number Locked Status Part Code Revision Date 1.03 002 L 41204 AB 06/29/2017 The IC security bit is locked/set for code security for production unless otherwise specified. Revision number is not changed for bit locking.
SLG7NT41204_DS_r103 SLG7NT41204 Package Drawing and Dimensions
20 Lead STQFN Package
JEDEC MO-220, Variation WECE IC Net Weight: 0.0090 g
SLG7NT41204_DS_r103 SLG7NT41204 Tape and Reel Specification Package Type # of Pins Nominal Package Size (mm) Max Units Reel & Hub Size (mm) Trailer A Leader B Pocket (mm) per reel per box Pockets Length (mm) Pockets Length (mm) Width Pitch STQFN 20L 2x3mm 0.4P Green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Length (mm) Pocket BTM Width (mm) Pocket Depth (mm) Index Hole Pitch (mm) Pocket Pitch (mm) Index Hole Diameter (mm) Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm) Tape Width (mm) A0 B0 K0 P0 P1 D0 E F W STQFN 20L 2x3mm 0.4P Green Refer to EIA-481 Specifications Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 3.3 mm3 (nominal). More information can be found at www.jedec.org.
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