SLG6M6001V

SLG6M6001V DIALOG

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 19

Technical content

Features

• 2 x 3 mm STQFN 18L FC package (6 fused pins for drain and 6 fused pins for source)
• Logic level ON pins able to support 1.05 V CMOS Logic
• 3.8 m Ω RDSONwhile supporting 10 A
• Discharges load when off
• Two Over Current Protection Modes (Short Circuit/Active)
• Short Circuit Current Limit
• Active Current Limit
• Over Temperature Protection
• NVM programmable configuration for Ramp Rate, Dis- charge, Logic Cell, Temperature Limit, and Current Limit
• High / Low Current Select
• Automatic Switch from Low to High Current
• Current Sense Output:
• Wide IDS current sensing range: 50 mA to 10 A
• High Current Mode Accuracy (typ)
• ±3% from 3A to 10A
• ±6% from 1A to 2.9A
• Low Current Mode Accuracy (typ)
• ±10% from 0.1A to 1A
• Pb-Free / Halogen-Free / RoHS 6/6 compliant
• Operating Temperature (ambient): -40 °C to 85°C
• Operating Voltage: 3.0 V to 5.5 V Pin Configuration

Applications

• Notebook, Tablet, and Server Power Rail Switching
• Telecommunications Equipment Power Rail Switching
• Power Rail Monitoring
• Telemetry Reporting
• Hot-swap Applications
• Over Current Protection 18-pin STQFN FC (Top View) ON1 1 PG/FAULT# IOUT D ON2/MODE 2 SLG6M6001V D 4 S S VDD GND D D 5 D 7 S12 S S DS

000-006M6001-070 Page 2 of 19 SLG6M6001V Preliminary Block Diagram D Short Circuit Programmable Logic Cell (PLC) 0.85 to VDD Programmable Ramp Options VS+ 5 V Charge Pump VDD Programmable Current Limit ON1 OSC Programmable Temp Limit Programmable Discharge1024-bit NVM Programmable 0.9 xVREF S IOUT PG/FAULT# 0 to 2.5 V (full scale) (Open Drain) 3.0 to 5.5 V 1.0 to 5.5 V High Current Drive Low Current Drive ON2/MODE Current Detect High Current Bank Low Current Bank Fault# 2 kΩ 4.7 μF b[5:0] b[15:13] b[7:6] b[10:8] b[12:11] b[20:16] 10 kΩ pullup 1μF

000-006M6001-070 Page 3 of 19 SLG6M6001V Preliminary Pin Description PG/FAULT# Status Table Pin # Pin Name Type Pin Description

1 ON1 Input Programmable Logic (4 MΩ pull down resistor)

CMOS input with VIL < 0.3 V, VIH > 0.85 V

2 ON2/MODE Input

ON2 or Current Mode Selection Pin Programmed by bit [2:0] = “000” Current Mode L = High Current Mode, 10 A max(Power Up Default) H = Low Current Mode, 750 mA max

3 D MOSFET Drain of Power MOSFET (fused pin 3 through pin 8)

4 D MOSFET Drain of Power MOSFET (fused pin 3 through pin 8)

5 D MOSFET Drain of Power MOSFET (fused pin 3 through pin 8)

6 D MOSFET Drain of Power MOSFET (fused pin 3 through pin 8)

7 D MOSFET Drain of Power MOSFET (fused pin 3 through pin 8)

8 D MOSFET Drain of Power MOSFET (fused pin 3 through pin 8)

9 S MOSFET Source of Power MOSFET (fused pin 9 through pin 14)

10 S MOSFET Source of Power MOSFET (fused pin 9 through pin 14)

11 S MOSFET Source of Power MOSFET (fused pin 9 through pin 14)

12 S MOSFET Source of Power MOSFET (fused pin 9 through pin 14)

13 S MOSFET Source of Power MOSFET (fused pin 9 through pin 14)

14 S MOSFET Source of Power MOSFET (fused pin 9 through pin 14)

15 PG/FAULT# Output, Open

Pin 15 is a multipurpose status output pin. 10 kΩ pull up resistor recom- mended. - When Pin 15 asserts high, it acts as a power good output signal. The device’s VS voltage has reached 90% voltage level and the internal N-FET has fully turned on which allows max IDS current at lowest RDSON value. - When Pin 15 asserts low, it acts as a fault# notification signal. The fault condition is dependent on Pin 2’s input level. 16 IOUT Output Current Output. 2 kΩ (1% or better) external resistor and 1 nF external capacitor recommended.

17 GND GND Ground

18 VDD PWR VDD power for load switch control (3.0 V to 5.5 V) Pin 2 (MODE) Pin 15 (Fault#) Device Status L (High Current Mode) Low VS dropped below 90% of power rail voltage. H (Low Current Mode) Low Device failed to enter low current mode. See State diagram for more details.

000-006M6001-070 Page 4 of 19 SLG6M6001V Preliminary Absolute Maximum Ratings Recommended Operating Temperature

Electrical Characteristics

Parameter Description Conditions Min. Typ. Max. Unit VDD Power Supply -- -- 7 V TS Storage Temperature (ambient) -65 -- 150 °C ESDHBM ESD Protection Human Body Model 2000 -- -- V MOSFET IDS Current from Drain to Source Continuous -- -- 12 A MOSFET IDSPK Peak Current from Drain to Source For no more than 1 ms with 1% duty cycle -- -- 16 A Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above t hose indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Description Min. Max. Unit TO Operating Temperature (ambient) -40 85 °C Conditions: -40 °C to 85 °C (unless otherwise noted) Parameter Description Conditions Min. Typ. Max. Unit VDD Power Supply Voltage -40 °C to 85 °C 3.0 -- 5.5 V IDD Power Supply Current when OFF @ 25°C Leakage -- 5 TBD μA when ON, no load, @ 25°C -- 300 TBD μA IDS Drain to Source Current High Current Mode -- -- 10 A Low Current Mode -- -- 750 mA Conditions: -40 °C to 85 °C (unless otherwise noted) Parameter Description Conditions Min. Typ. Max. Unit RDSON ON Resistance (High Current Mode) TA 25°C @ 100 mA -- 3.8 4.0 m Ω TA 85°C @ 100 mA -- 4.0 4.3 m Ω ON Resistance (Low Current Mode) TA 25°C @ 100 mA -- 30.4 -- m Ω TA 85°C @ 100 mA -- 32.0 -- m Ω VS Source Voltage -- 0 V D V VD Drain Voltage 1.0 -- 5.5 V

000-006M6001-070 Page 5 of 19 SLG6M6001V Preliminary ON/OFF Characteristics * Not 100% tested Conditions: -40 °C to 85 °C (unless otherwise noted) Parameter Description Conditions Min. Typ. Max. Unit TINIT_DELAY Power up initiation delay* See Timing Diagram -- -- 1 ms TON_DELAY ON Logic Delay* See Timing Diagram -- -- 500 μs TPROG_DELAY Programmable Delay 0 Prog. 2.5 ms TSLEW Programmable Slew Rate 10% to 90% VS, CL = 100 μF, RL = 20 Ω 0.5 Prog. 2.0 V/ms TTOTAL_ON Total on Delay 50% ON1 to VS 90%, CL = 100 μF, RL = 20 Ω 0.5 -- 3 ms TOFF_DELAY Off Delay 50% ON1 to VS Fall, CL = 100 μF, RL = 20 Ω -- 35 TBD μs TPG_DELAY PG/FAULT# Driver Assertion Delay* Logic trigger to PG/FAULT# assert- ed -- -- 100 μs TSWITCH_DLY_LH Low Current mode to High Current Mode swtich delay 50% Pin 2 to High Current Mode -- -- 5 ms TSWITCH_DLY_HL High Current mode to Low Current Mode swtich delay 50% Pin 2 to Low Current Mode -- -- 500 μs VIH High Input Voltage Pin 1 & Pin 2 0.85 -- V DD V VIL Low Input Voltage Pin 1 & Pin 2 -0.3 -- 0.3 V VOL_PG PG/FAULT# Low Output Voltage IOL = 1 mA, Pull Up Resistor = 10 kΩ, Pin 15 -- -- 0.5 V VREF_PG_RISE Power Good Rising VREF compara- VREF_PG_FALL Power Good Failing VREF compar- ILIMIT Active Current Limit (High Mode) Programmable ILIMIT. VS > 500 mV, Pin 2 = Assert Low (High Current Mode) 6 Prog. 12 A Active Current Limit (Low Mode) Programmable ILIMIT. VS > 500 mV, Pin 2 = Assert High (Low Current Mode) 0.75 Prog. 1.25 A Short Circuit Current Limit V S < 500 mV 1.5 Prog. 3.0 A ILIMIT _ACC Current Limit Accuracy * Cu rrent Limit Accuracy -- -- ±20 % THERMOFF Thermal Protection Shutoff (junction) * Programmable, automatic shutoff temperature 85 Prog. 110 °C THERMOFF_ACC Thermal Sensor Accuracy * -- -- ±10 % THERMON Thermal Protection turn on (junction) * Programmable, automatic Turn on temperature 85 -- -- °C THERMTIME Thermal shutoff reaction time * -- -- 1.0 ms IAS_TRIGGER IDS Current Automatic Low Current to High Current Trigger Level 0.8 1.0 1.2 A IBLK_HL_TRANS IDS Current level to block illegal High current to Low Current transi- tion -- -- 750 mA RDIS Equivalent discharge resistance Programmable VS discharge resis- tor 75 Prog. 1500 Ω CapSource Source Cap Source to GND 10 100 -- μf

000-006M6001-070 Page 6 of 19 SLG6M6001V Preliminary Current Sense Output Characteristics * 2kΩ (1% or better) external resistor recommended. IOUT Accuracy Test Setup Conditions: -40 °C to 85 °C (unless otherwise noted) Parameter Description Cond itions Min. Typ. Max. Unit ISENSE IOUT (Pin 16) Output Current, FET Array High Current Mode 10 A Max IDS = 10 A, Pin 2 (Mode) = L -- 1000 -- μA IDS = 1 A, Pin 2 (Mode) = L -- 100 -- μA IDS = 0.5 A, Pin 2 (Mode) = L -- 50 -- μA IOUT (Pin 16) Output Current, FET Array Low Mode 750 mA Max IDS = 0.75 A, Pin 2 (Mode) = H -- 600 -- μA IDS = 0.1 A, Pin 2 (Mode) = H -- 80 -- μA IDS = 0.05 A, Pin 2 (Mode) = H -- 40 -- μA ISENSE_ACC IOUT (Pin 16) Output Current Accu- racy, FET Array High Current Mode

10 A Max

IDS = 3 A to 10 A, Pin 2 (Mode) = L -- ±3 -- % IDS = 1 A to 2.9 A, Pin 2 (Mode) = L -- ±6 -- % IOUT (Pin 16) Output Current Accu- racy, FET Array Low Mode 750 mA Max IDS = 0.1 to 1 A, Pin 2 (Mode) = H -- ±10 -- % Power Supply #1 Power Supply #2 IOUT Agilent 6060B Constant Current DC Electric Load D S VDD Current Meter Fluke 289 DUT

000-006M6001-070 Page 7 of 19 SLG6M6001V Preliminary SLG6M6001V Turn ON The normal power on sequence is first VDD, with VD only being applied after VDD is > 1 V, and then ON after VD is at least 90% of final value. The normal power off sequence is the power on sequence in reverse. If VDD and VD are turned on at the same time, then it is possible that a voltage glitch will appear on VS before VDD achieves 1V, which is the VT of the main MOSFET. The size of the glitch is dependent on source and drain capacitance loading and the ramp rate of VDD & VD. SLG6M6001V Turn ON The VS ramp follows a linear path, not an RC limitation provided the ramp is slow enough to not be current limited by load capacitance. SLG6M6001V Current Limiting The SLG6M6001V has two forms of current limiting.

12 A Standard Current Limiting Mode (Programmable Level)

Current is measured by mirroring the current through the main MOSFET. This response is a closed loop response and is therefore very fast and current limits in less than a few micro-seconds. There is no difference between peak or constant current limit Temperature Cutoff As the V(g) drops the Rds(ON) of the main MOSFET will increa se, thus limiting the current, but also increasing the power dissipation of the IC. The IC is very small and cannot dissipate much power. Therefore, if a current limit condition is sustained the IC will heat up. If the junction temperature exceeds approximately 125°C (Default, Programmable), then V(g) will be brought low completely shutting off the main MOSFET. As the die cools the MOSFET will be turned back on at 100°C (Default, Programmable hysteresis). If the current limiting condition has not been mitigated then the die will again heat up to 125°C (Default, Programmable) and the process will repeat. Short Circuit Current Limiting Mode When V(S) < 500 mV, the current is limited to approximately 3 A to 1.5 A. The short circuit current limit is a NVM programmable setting. This current limit is accomplished in the same manner as the Standard Current Limiting Mode with the exception that the current mirror is 15x greater. Because the current mirror is so much larger, a 15 x smaller main MOSFET current is required to generate the same V(i). If V(S) rises above approximately 500 mV, then this mode is automatically switched out. The short circuit current limiting mode does not protect the device from a sudden short after ON. In the event of a sudden short after ON, the VS pin of the CurrentPAK will switch from 10A @ 5V to ground within few nanoseconds. During this transition, the device will incur irreversible damage due to a high voltage sp ike created on VD or VS pins. To prevent this damage, it is recommended to add decoupling capacitors at the VD and VS pins of the CurrentPAK, as shown below, to suppress the voltage spike on the VS and VD pins. For example, assume the power supply max output feeding into the CurrentPAK is 45A max, it is recommended to use an 8000 µF capacitor from VD to GND and a 4000 µF capacitor from VS to GND. The decoupling capacitors should be placed as close to the CurrentPAK as possible. In addition to using the large size decoupling capacitors, minimizing the inductance on PCB power and ground plane is also important to minimize the voltage spike. Power Supply 5.5V, 45A Max CurrentPAK 8000uF 4000uF GND VD VS Load 10A Max PCB Power Plane inductance PCB Power Plane inductance PCB Ground Plane inductance PCB Ground Plane inductance PCB Ground Plane inductance Instant short

000-006M6001-070 Page 8 of 19 SLG6M6001V Preliminary High Current Mode vs. Low Current Mode Selection The device powers up in high current mode as the default setting. In high current mode, the max IDS is 10 A. When Pin 2 is driven from low to high, the internal power FET array shuts down the high current bank, keeping only the low current bank active, limiting max IDS to 750 mA. Best system practice: The purpose of low current mode is to allow the system to get a more precise current sense reading when instantaneous IDS is between 50 mA to 750 mA. In low current mode, the IOUT (pin 16) output scales up by 8 times to produce a higher current level reading. If the system does not need precise current reading at low IDS, it is recommended to stay in high current mode at all times by tying MODE (pin 2) to GND. NOTE: this recommendation is only applicable when one of the two "H/L Select" options is selected from the ON Logic Functions pull-down menu in the GUI. The load switch can only switch to low current mode when instantaneous IDS is less than IBLK_HL_TRANS. If the device attempts to switch to low current mode while the instantaneous IDS is higher than I BLK_HL_TRANS, the device’s internal control logic will block this operation. The device keeps the FET array in high current mode to prevent any system failures. The device also asserts FAULT# (Pin 15) low to notify the system that the attempt to switch to low current mode has failed. If the IDS current increases above I AS_TRIGGER, the device automatically switches back to high current mode by turning on all banks of the FET array. The auto switch delay time is TSWITCH_DLY_LH (5 ms max). Discharge Resistor Function An integrated discharge resistor has a programmable value (see table below) that will engage to discharge V(S) anytime a turn-off is initiated, whether by deassertion of enable(s) or inception of over temperature protection.

000-006M6001-070 Page 9 of 19 SLG6M6001V Preliminary Programmable NVM Settings ON1 and ON2 Pin Configuration ON1 and ON2 pins are inputs to a small NVM programmable logic cell “PLC”. * Denotes Power Up Default Note: Delay table not applicable to device turn off. Power On Ramp Options The Power On Ramp Options are NVM programmable via the followings bits. * Denotes Power Up Default Bits [2:0] ON Logic Functions 000* Pin1 = ON1 Pin2 = H/L Select, No Delay

001 ON1 AND ON2

010 ON1 OR ON2

011 ON1 XOR ON2

100 Pin1 = ON1 NOT

Pin2= H/L Select, No Delay

101 ON1 NAND ON2

110 ON1 NOR ON2

111 ON1 XNOR ON2

Bits [5:3] Turn ON Delay Functions 000* 0 ms Delay ON1 001 2.5 ms Delay ON1 010 5 ms Delay ON1 011 50 ms Delay ON1 100 0 ms Delay ON2 101 2.5 ms Delay ON2 110 5 ms Delay ON2 111 50 ms Delay ON2 Bits [7:6] Ramp Options (V D of 3.3V) Tolerance Typ Max 00* 2 ms linear ramp from output of programmable logic cell “PLC” to 90% of VD assuming < 500 μs delay from PLC out to start of ramp 1.6 V/ms 2.0 V/ms 01 3 ms linear ramp from PLC out to 90% of VD assuming < 500 μs delay from PLC out to start of ramp 1.2 V/ms 1.6 V/ms 10 4 ms linear ramp from PLC out to 90% of VD assuming < 500 μs delay from PLC out to start of ramp 0.8 V/ms 1.2 V/ms 11 6 ms linear ramp from PLC out to 90% of VD assuming < 500 μs delay from PLC out to start of ramp 0.4 V/ms 0.8 V/ms

000-006M6001-070 Page 10 of 19 SLG6M6001V Preliminary Power Good Reference Settings The Power Good feature is NVM programmable via the followings bits. * Denotes Power Up Default Power Good turns on ~ 100 μs after VD = 90% of PGD comparator threshold is met. Discharge Settings The discharge options are NVM programmable via the followings bits. * Denotes Power Up Default Temperature Shutdown Settings The temperature shutdown limit is NVM programmable via the followings bits. * Denotes Power Up Default Bits [10:8] V D [V] Under Voltage Detect Level Tolerance PG rising on rising input PG falling on falling input Typical @ 25 °C Max over PVT @ -20 to 70 °C 101 1.35 1.215 1.1475 ±3% ±5% 110 1.25 1.125 1.0625 ±3% ±5% 111 1.05 0.945 0.8925 ±3% ±5% Bits [12:11] Resistance [Ω] Min Typ Max 00* 75 150 225 01 150 300 450 10 500 1000 1500

11 No Discharge

Bits [15:13] Temperature [°C] Hysteresis [°C] Tolerance 000* 125 25 ±10 °C 001 135 25 ±10 °C 010 110 25 ±10 °C 011 100 25 ±10 °C 100 85 15 ±10 °C 101 125 15 ±10 °C 1 1 0 - -- -- -

111 Test Only

000-006M6001-070 Page 11 of 19 SLG6M6001V Preliminary Active Current Limit Settings The Active Current Limit is NVM programmable via the followings bits. * Denotes Power Up Default Short Circuit Current Limit Level * Denotes Power Up Default Bits [1023:21] are reserved. Bits [17:16] Current Limit [A] (High Current Mode) Current Limit [A] (Low Current Mode) Voltage Level of VS Tolerance 00* 12 (default) 1.5 (default) > 500 mV ±20% 01 10 1.25 > 500 mV ±20% 10 8 1.0 > 500 mV ±20% 11 6 0.75 > 500 mV ±20% Bits [20:18] Current Limit [A], VS < 500 mV Short Circuit Current Limit Tolerance 000 3.0 ±50% 001 2.5 ±50% 011* 2.0 ±50% 111 1.5 ±50%

000-006M6001-070 Page 12 of 19 SLG6M6001V Preliminary State Diagram Notes: 1. Pin 2 (MODE) must stay LOW during initial power up. After the device enters High Current Mode, the system can select Low Current Mode by driving Pin 2 to HIGH level 2. This state diagram is only applicable when one of the two "H/L Se lect" options is selected from the ON Logic Functions pull-down menu in the GUI. VDD Fall VDD Fall Low Current Mode High Current Mode Idle ModePower Off VDD Rise Pin2 Rise and Current Below Threshold Pin2 Rise and Current Above Threshold (PG Drive LOW) VDD Fall Pin2 Fall Pin 1 Fall Pin 1 Fall Pin 1 Rise Autoswitch IDS > IAS_TRIGGER

000-006M6001-070 Page 13 of 19 SLG6M6001V Preliminary Initialization Timing Diagram Note: Pin 2 must stay LOW before the rising edge of Pin 1. Pin 2 can go HIGH only after VS goes above 90% T_Initiate_Delay = 1ms VDD ON1 (PIN 1) 3.0V Power OFF MODE IDLE MODE (Loading NVM) 50% ON T_ON_DELAY (~500us) T_PROG DELAY (Programmable) 10% VS 90% VS T_slew (Programmable) T_TOTAL_ON VS T_PG_DELAY = 100us IDLE MODE VIL T_OFF_DELAY = 35us PG/ FAULT# T_SWITCH_DLY_LH (5ms Max) Mode Internal VGS > 5.0V High Current Mode ~1.0V < internal VGS < ~ 5.0V 0V < internal VGS < ~ 1.0V MODE (PIN 2)

000-006M6001-070 Page 14 of 19 SLG6M6001V Preliminary H->L & L->H Transition Timing Diagram IDS Pin 2 Low = HC High = LC PG/ FAULT# VS IDS < 750mA Mode High Current ModeLow Current Mode ISENSE X8 Scaling Normal Scaling T_SWITCH_DLY_HL ~ 500us Low Current Mode Allows IDS increase above 750mA. (e.g 10A) X8 Scaling T_SWITCH_DLY_LH ~5ms. IDS < 750mA Bring IDS below 750mA before Pin 2 Transition

000-006M6001-070 Page 15 of 19 SLG6M6001V Preliminary Auto Mode Transition Timing Diagram IDS Pin 2 Low = HC High = LC PG/ FAULT# VS > IBLK_HL_TRANS < IBLK_HL_TRANS High Current Mode Low Current mode Auto Switch back to High Current Mode T_PG_DELAY 100us T_PG_DELAY 100us High Current Mode Stay High ISENSE Normal Scaling X8 Scaling Normal Scaling Unable to switch to low current mode. Stay in high mode. FAULT# assert low Successfully switch to low current mode. INSENSE x8 Scaling T_SWITCH_DLY_LH ~ 5ms IDS >1.2A. Trigger Auto Switch L to H. FAULT# Drive Low Auto Switch may cause VS has slight voltage dip depending on IDS T_SWITCH_DLY_HL ~ 500us > IAS_TRIGGER T_PG_DELAY 100us T_PG_DELAY 100us Mode

000-006M6001-070 Page 16 of 19 SLG6M6001V Preliminary

Ordering Information

Part Number Type Production Flow SLG6M6001V STQFN 18L FC Industrial, -40 °C to 85 °C SLG6M6001VTR STQFN 18L FC (Tape and Reel) Industrial, -40 °C to 85 °C

000-006M6001-070 Page 17 of 19 SLG6M6001V Preliminary Package Top Marking System Definition PPPPP Part Code Pin 1 Identifier WWNNN Date Code + S/N Code ARR Assembly + Rev. Code

000-006M6001-070 Page 18 of 19 SLG6M6001V Preliminary Package Drawing and Dimensions

18 Lead TQFN Package 2 x 3 mm (Fused Lead)

JEDEC MO-220, Variation WCEE

000-006M6001-070 Page 19 of 19 SLG6M6001V Preliminary Tape and Reel Specifications Carrier Tape Drawing and Dimensions Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: late st revision for reflow profile based on package volume of 3.30 mm 3 (nominal). More information can be found at www.jedec.org. Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm]per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 18L FC Green 18 2 x 3 x 0.55 3,000 3,000 178 / 60 42 168 42 168 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W STQFN 18L Refer to EIA-481 specification