SLG59H1019V

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Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 41

Technical content

Features

• Wide Operating Input Voltage: 4.5 V to 25.2 V
• Maximum Continuous Switch Current: 5 A
• Automatic nFET SOA Protection
• High-performance MOSFET Switch Low RDS ON: 13 mΩ at VIN = 25.2 V Low ∆RDSON/∆VIN: <0.05 mΩ/V Low ∆RDSON/∆T: <0.06 mΩ/°C
• Capacitor-adjustable Inrush Current Control
• Two stage Current Limit Protection: Resistor-adjustable Active Current Limit Internal Short-circuit Current limit
• Open Drain FAULT Signaling
• MOSFET Current Analog Output Monitor: 10 µA/A
• Fast 0.75 k Ω Output Discharge
• Pb-Free / Halogen-Free / RoHS Compliant Packaging Pin Configuration

Applications

• Telecommunications Equipment
• High-performance Computing Point-of-Load Power Distribution
• Motor Drives ON 1 FAULT CAP GND GND 2 VIN 4 VOUT NC RSET IOUT VIN VIN 5 VIN 7 VOUT12 VOUT VOUT VIN VOUT 18-pin STQFN 1.6 x 3.0 mm, 0.40mm pitch (Top View) SLG59H1019V ON VOUT

3 V FS - Connect

4.5 V ≤ VIN ≤ 25.2 V 3 A Charge Pump CSLEW 10 nF RPU 100 kΩ Linear Ramp Control State Machine (CL/SC Detection and Over Temperature Protection) DischargeCMOS Input

3.1 V VIN

30.1 kΩ 47 µF RIOUT 84.5 kΩ GND OFF 22µF 0.1 µF VLOGIC CIOUT 180 pF 47μF 22μF CLOAD = C4 + C5 CIN = C1 + C2 + C3 VOUT CAP RSET VIN IOUT FAULTON 1 MΩ

000-0059H1019-050 Page 2 of 41 SLG59H1019V Preliminary Pin Description

Ordering Information

Pin # Pin Name Type Pin Description

1 ON Input

A low-to-high transition on this pin initiates the operation of the SLG59H1019V’s state machine. ON is an asserted HIGH, level-sensitive CMOS input with VIL < 0.3 V and VIH > 0.9 V. Even though the ON pin circuit has a 1 MΩ internal pull-down resistor internally grounded, connect this pin to a general-purpose output (GPO) of a microcontroller, an application processor, or a system controller. 2 GND GND Pin 2 is a low-current GND terminal for the SLG59H1019V. Connect directly to Pin 3 3G N DG N D Pin 3 is the main ground connection for the SLG59H1019V’s internal charge pump, its gate drive and current-limit circuits as well as its internal state machine. Therefore, use a short, stout connection from Pin 3 to the system’s analog or power plane. 4-8 VIN MOSFET VIN supplies the power for the operation of the SLG59H1019V, its internal control circuitry, and the drain terminal of the nFET power switch. With 5 pins fused together at VIN, connect a 47 μF (or larger) low-ESR capacitor from this pin to ground. Capacitors used at VIN should be rated at 50 V or higher. 9-13 VOUT MOSFET Source terminal of n-channel MOSFET (5 pins fused for VOUT). Connect a 47 μF (or larger) low-ESR capacitor from this pin to ground. Capacitors used at VOUT should be rated at 50 V or higher. 14 NC Null No Connect – Do not make any connection to this pin.

15 FAULT

An open drain output, FAULT is asserted within TFAULTLOW when a current-limit or an over-temperature condition is detected. FAULT is deasserted within TFAULTHIGH when the fault condition is removed. Connect an 100 kΩ external resistor from the FAULT pin to local system logic supply.

16 CAP Output

A low-ESR, stable dielectric, ceramic surface-mount capacitor connected from CAP pin to GND sets the VOUT slew rate and overall turn-on time of the SLG59H1019V. For best performance, the range for CSLEW values are 10 nF ≤ CSLEW ≤ 20 nF – please see typical characteristics for additional information. Capacitors used at the CAP pin should be rated at 10 V or higher. See equation for selecting capacitor and start-up slewing.

17 IOUT Output

IOUT is the SLG59H1019V’s power MOSFET load current monitor output. As an analog output current, this signal when applied to a ground-reference resistor generates a voltage proportional to the current through the n-channel MOSFET. The IOUT transfer characteristic is typically 10 μA/A with a voltage compliance range of 0.5 V ≤ VIOUT ≤ 4 V. Optimal IOUT linearity is exhibited for 0.5 A ≤ IDS ≤ 5 A. In addition, it is recommended to bypass the IOUT pin to GND with a 0.18 nF capacitor.

18 RSET Input

A 1%-tolerance, metal-film resistor between 18 kΩ and 91 kΩ sets the SLG59H1019V’s active current limit. A 91 kΩ resistor sets the SLG59H1019V’s active current limit to 1 A and a 18 kΩ resistor sets the active current limit to 5 A. Part Number Type Production Flow SLG59H1019V STQFN 18L FC Industrial, -40 °C to 85 °C SLG59H1019VTR STQFN 18L FC (Tape and Reel) Industrial, -40 °C to 85 °C

000-0059H1019-050 Page 3 of 41 SLG59H1019V Preliminary Absolute Maximum Ratings Parameter Description Conditions Min. Typ. Max. Unit VIN to GND Power Switch Input Voltage to GND Continuous -0.3 -- 30 V Maximum pulsed VIN, pulse width < 0.1s -- -- 32 V VOUT to GND Power Switch Output Voltage to GND -0.3 -- V IN V ON, CAP, RSET, IOUT, and FAULT to GND ON, CAP, RSET, IOUT, and FAULT Pin Voltages to GND -0.3 -- 7 V TS Storage Temperature -65 -- 150 °C ESDHBM ESD Protection Human Body Model 2000 -- -- V ESDCDM ESD Protection Charged Device Model 500 -- -- V MSL Moisture Sensitivity Level 1 θJA Thermal Resistance 1.6 x 3.0 mm 18L STQFN; De- termined with the device mount- ed onto a 1 in 2, 1 oz. copper pad of FR-4 material -- 40 -- °C/W TJ,MAX Maximum Junction Temperature -- 150 -- °C MOSFET IDSCONT Continuous Current from VIN to VOUT TJ < 150°C -- -- 5 A MOSFET IDSPEAK Peak Current from VIN to VOUT Maximum pulsed switch current, pulse width < 1 ms, 1% duty cy- cle -- -- 6 A Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above thos e indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Electrical Characteristics

4.5 V ≤ VIN ≤ 25.2 V; CIN = 47 μF, TA = -40°C to 85°C, unless otherwise noted. Typical values are at TA = 25°C Parameter Description Conditions Min. Typ. Max. Unit VIN Operating Input Voltage 4.5 -- 25.2 V VIN(UVLO) VIN Undervoltage Lockout Threshold VIN ↓ 2.4 -- 3.8 V IQ Quiescent Supply Current ON = HIGH; I DS = 0 A -- 0.5 0.6 mA ISHDN OFF Mode Supply Current ON = LOW; I DS = 0 A -- 1 3 µA RDSON ON Resistance TA = 25°C; IDS = 0.1 A -- 13 14 m Ω TA = 85°C; IDS = 0.1 A -- 17.2 19.2 m Ω MOSFET IDS Current from VIN to VOUT Continuous -- -- 5 A ILIMIT Short-circuit Current Limit, ISCL VOUT < 0.5 V -- 0.5 - A TACL Active Current Limit Response Time RSET = 51.6 kΩ -- 120 -- µs RDSCHRG Output Discharge Resistance 650 750 900 Ω

000-0059H1019-050 Page 4 of 41 SLG59H1019V Preliminary IOUT MOSFET Current Analog Monitor Output IDS = 1 A 9.3 10 11.1 µA IDS = 3 A 29 30.3 32 µA TIOUT IOUT Response Time to Change in Main MOSFET Current CIOUT = 180 pF; Step load 0 to 2.4 A; 0% to 90% IOUT -- 45 -- µs CLOAD Output Load Capacitance C LOAD connected from VOUT to GND 47 -- -- µF TON_Delay ON Delay Time 50% ON to 10% VOUT ↑; VIN = 4.5 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10 µF 300 400 600 µs 50% ON to 10% VOUT ↑; VIN = 25.2 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10µF 0.9 1.0 1.2 ms TTotal_ON Total Turn-on Time 50% ON to 90% VOUT ↑ Set by External CSLEW 1 ms 50% ON to 90% VOUT ↑; VIN = 4.5 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10 µF 1.8 1.9 2.1 ms 50% ON to 90% VOUT ↑; VIN = 25.2 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10 µF 8.9 9.0 9.2 ms VOUT(SR) VOUT Slew rate 50% ON to 90% VOUT ↑ Set by External CSLEW

1 V/ms

10% to 90% VOUT ↑; VIN = 4.5 to 25.2 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10 µF 33 . 2 3 . 5 V / m s TOFF_Delay OFF Delay Time 50% ON to VOUT ↓; RLOAD = 100 Ω, No CLOAD -- 15 -- µs TFALL VOUT Fall Time 90% VOUT to 10% VOUT ↓; ON = HIGH-to-LOW; VIN = 4.5 V to 25.2 V; RLOAD = 100 Ω, No CLOAD 10 12 18 µs TFAULTLOW FAULT Assertion Time Abnormal Step Load Current event to FAULT↓; IACL = 1 A; VIN = 25.2 V; RSET = 91 kΩ; switch in 20 Ω load -- 80 -- µs TFAULTHIGH FAULT De-assertion Time Delay to FAULT↑ after fault condition is removed; IACL = 1 A; VIN = 25.2 V; RSET = 91 kΩ; switch out 20 Ω load -- 180 -- µs FAULTVOL FAULT Output Low Voltage I FAULT = 1 mA -- 0.2 -- V ON_VIH ON Pin Input High Voltage Internal 1 MΩ ±20% from ON Pin to GND 0.9 -- 5 V ON_VIL ON Pin Input Low Voltage -0.3 0 0.3 V ION(Leakage) ON Pin Leakage Current 0.9 V ≤ ON ≤ 5 V or ON = GND -- -- 2 µA THERMON Thermal Protection Shutdown Threshold -- 145 -- °C THERMOFF Thermal Protection Restart Threshold -- 120 -- °C Notes: 1. Refer to typical Timing Parameter vs. C SLEW performance charts for additional information when available. Electrical Characteristics (continued) 4.5 V ≤ VIN ≤ 25.2 V; CIN = 47 μF, TA = -40°C to 85°C, unless otherwise noted. Typical values are at TA = 25°C Parameter Description Conditions Min. Typ. Max. Unit

000-0059H1019-050 Page 5 of 41 SLG59H1019V Preliminary TTotal_ON, TON_Delay and Slew Rate Measurement Timing Details 90% VOUT 50% ON TON_Delay VOUT(SR)(V/ms) ON* VOUT TTotal_ON 10% VOUT 50% ON 10% VOUT TOFF_Delay TFALL 90% VOUT * Rise and Fall times of the ON signal are 100 ns

000-0059H1019-050 Page 6 of 41 SLG59H1019V Preliminary Typical Performance Characteristics RDSON vs. Temperature and VIN IACL vs. Temperature and RSET

000-0059H1019-050 Page 7 of 41 SLG59H1019V Preliminary IACL vs. RSET and Temperature IOUT vs. MOSFET IDS and VIN

000-0059H1019-050 Page 8 of 41 SLG59H1019V Preliminary IOUT vs. Temperature and MOSFET IDS VOUT Slew Rate vs. Temperature, VIN, and CSLEW

000-0059H1019-050 Page 9 of 41 SLG59H1019V Preliminary TTotal_ON vs. CSLEW, VIN, and Temperature

000-0059H1019-050 Page 10 of 41 SLG59H1019V Preliminary Timing Diagram - Basic Operation including Active Current Limit Protection VIN ON Time LOW HIGH TFAULTHIGH VOUT IDS 90% 10% TON_Delay Active Current Limit Operation FAULT HIGH ISCL IACL ISCL IACL ON TFAULTLOW Nominal Steady State Operation ResumesACL Threshold Triggered Abnormal Step Load Current Event TRISE

000-0059H1019-050 Page 11 of 41 SLG59H1019V Preliminary Timing Diagram - Active Current Limit & Thermal Protection Operation VOUT IDS 90% 10% TON_Delay Active Current Limit Operation Thermal Protection Operation ISCL IACL ISCL IACL TFAULTHIGHFAULT VIN ON Time LOW HIGH Nominal Steady State Operation Resumes TFAULTLOW Die temp > THERMON Abnormal Step Load Current Event TRISE TTotal_ON Die temp < THERMOFF

000-0059H1019-050 Page 12 of 41 SLG59H1019V Preliminary Timing Diagram - Basic Operation including Active Current + Internal FET SOA Protection VIN ON Time LOW HIGH TFAULTHIGH VOUT IDS 90% 10% 0.2s TON_Delay Active Current Limit Operation FAULT HIGH ISCL IACL ISCL IACL ON TFAULTLOW ACL Threshold Triggered Nominal Steady State Operation resumes once overload condition is removed Automatic restart after 0.2s “cool off” delay and normal operation resumes if overload condition is removed FET SOA Threshold Triggered and FET is turned off ACL Threshold Triggered Abnormal Step Load Current Event SOA Threshold TRISE Decreasing RLOAD drops VOUT SOA Protection

000-0059H1019-050 Page 34 of 41 SLG59H1019V Preliminary Applications Information HFET1 Safe Operating Area Explained Silego’s HFET1 integrated power controllers incorporate a number of internal protection featur es that prevents them from damaging themselves or any other circuit or subcircuit downstr eam of them. One particular protection feature is their Safe Operation Area (SOA) protection. SOA pr otection is automatically activated under overpower and, in some cases, under overcurrent conditions. Overpower SOA is activated if package power dissipation exceeds an internal 15 W threshold and HFET1 devices will quickly switch off (open circuit) upon overpower detection and automatically resume (close) nominal operation once overpower condition no longer exists. One of the possible ways to have an overpower condition trigger SOA protection is when HFET1 products are enabled into heavy output resistive loads and/or into large load capacitors. It is under these conditions to follow carefully the “Safe Start-up Loading” guidance in the Applications section of the datasheet. During an overcurrent condition, HFET1 devices will try to limit the output current to the level set by the external R SET resistor. Limiting the output current, however, causes an increased voltage drop across the FET’s channel because the FET’s RDS ON increased as well. Since the FET’s RDS ON is larger, package power dissipation also increases. If the resultant increase in packa ge power dissipation is higher/equal than 15 W, internal SOA protection will be triggered and the FET will open circuit (switch off). Every time SOA protection is triggered, all HFET1 devices will automatically attempt to resume nominal operation after 160 ms. The automatic retry attempt only allows power-up with SOA at 5 W. This SOA fold back power ensures that the FET survives a short circuit condition. To clear the 5 W SOA fold back, switch the ON pin to “LOW” to power reset SOA to 15 W. Safe Start-up Condition SLG59H1019V has built-in protection to prevent over-heating during start-up into a heavy load. Overloading the VOUT pin with a capacitor and a resistor may result in non-monotonic VOUT ramping (Figure 42) or repeated restarts (Figure 38 to Figure 41) . In general, under light loading on VOUT, VOUT ramping can be controlled with CSLEW value. The following equation serves as a guide: where T RISE = Total rise time from 10% VOUT to 90% VOUT VIN = Input Voltage CSLEW = Capacitor value for CAP pin When capacitor and resistor loading on VOUT during start up, the following tables will ensure VOUT ramping is monotonic without triggering internal SOA protection: Safe Start-up Loading for VIN = 25.2 V (Monotonic Ramp) Slew Rate (V/ms) C SLEW (nF)2 CLOAD (μF) R LOAD (Ω) 0.5 66.7 500 60 1.0 33.3 250 60 1.5 22.2 160 60 2.0 16.7 120 60 2.5 13.3 100 60 CSLEW = TRISE VIN x 4,9 μA x 20

000-0059H1019-050 Page 35 of 41 SLG59H1019V Preliminary Note 2: Select the closest-value tolerance capacitor. Setting the SLG59H1019V’s Active Current Limit Note 3: Active Current Limit accuracy is ±15% over voltage range and over temperature range. Safe Start-up Loading for VIN = 15 V (Monotonic Ramp) Slew Rate (V/ms) C SLEW (nF)2 CLOAD (μF) R LOAD (Ω) 1 33.3 500 12 2 16.7 250 12 3 11.1 160 12 4 8.3 120 12 5 6.7 100 12 R SET (kΩ) Active Current Limit (A) 3 91 1 45 2 30 3 18 5

000-0059H1019-050 Page 36 of 41 SLG59H1019V Preliminary Power Dissipation The junction temperature of the SLG59H1 019V depends on different factors such as board layout, ambient temperature, and other environmental factors. The primary contributor to the increase in the junction temperature of the SLG59H1019V is the power dissipation of its power MOSFET. Its power dissipation and the junction temperature in nominal operating mode can be calculated using the following equations: where: PD = Power dissipation, in Watts (W) RDSON = Power MOSFET ON resistance, in Ohms (Ω) IDS = Output current, in Amps (A) and where: TJ = Junction temperature, in Celsius degrees (°C) θJA = Package thermal resistance, in Celsius degrees per Watt (°C/W) TA = Ambient temperature, in Celsius degrees (°C) In current-limit mode, the SLG59H1019V’s power dissipation can be calculated by taking into account the voltage drop across the power switch (VIN-VOUT) and the magnitude of the output current in current-limit mode (IACL): where: PD = Power dissipation, in Watts (W) VIN = Input Voltage, in Volts (V) RLOAD = Load Resistance, in Ohms (Ω) IACL = Output limited current, in Amps (A) VOUT = RLOAD x IACL PD = RDSON x IDS TJ = PD x θJA + TA PD = (VIN-VOUT) x IACL or PD = (VIN – (RLOAD x IACL)) x IACL

000-0059H1019-050 Page 37 of 41 SLG59H1019V Preliminary Package Top Marking System Definition 1019V Part Code Pin 1 Identifier WWNNN Date Code + LOT Code ARR Assembly + Rev. Code 1019V - Part ID Field WW - Date Code Field1 NNN - Lot Traceability Code Field1 A - Assembly Site Code Field 2 RR - Part Revision Code Field2 Note 1: Each character in code field can be alphanumeric A-Z and 0-9 Note 2: Character in code field can be alphabetic A-Z

000-0059H1019-050 Page 38 of 41 SLG59H1019V Preliminary Package Drawing and Dimensions 18 Lead TQFN Package 1.6 x 3 mm (Fused Lead) JEDEC MO-220, Variation WCEE

000-0059H1019-050 Page 39 of 41 SLG59H1019V Preliminary SLG59H1019V 18-pin STQFN PCB Landing Pattern Note: All dimensions shown in micrometers (μm)

000-0059H1019-050 Page 40 of 41 SLG59H1019V Preliminary Tape and Reel Specifications Carrier Tape Drawing and Dimensions Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: late st revision for reflow profile based on package volume of 2.64 mm 3 (nominal). More information can be found at www.jedec.org. Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm]per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 18L 0.4P FC Green 18 1.6 x 3 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W STQFN 18L 0.4P FC Green Refer to EIA-481 specification

000-0059H1019-050 Page 41 of 41 SLG59H1019V Preliminary

Revision History

11/3/2017 0.50 Preliminary Release