SLG59H1016V

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Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 23

Technical content

Features

• Wide Operating Supply Voltage: 4.5 V to 22 V
• Maximum Continuous Switch Current: 3.5 A
• Automatic nFET SOA Protection
• High-performance MOSFET Switch Low RDSON: 13.1 mΩ at V IN = 22 V Low ∆RDSON/∆VIN: <0.05 mΩ/V Low ∆RDSON/∆T: <0.06 mΩ/°C
• 4-Level, Pin-programmable VIN Overvoltage Lockout
• Capacitor-programmable Inrush Current Control
• Two stage Current Limit Protection: Resistor-programmable Active Current Limit Internal Short-circuit Current limit
• Open Drain FAULT Signaling
• MOSFET Current Analog Output Monitor: 10 µA/A
• F a s t 4 kΩ Output Discharge
• Pb-Free / Halogen-Free / RoHS Compliant Packaging Pin Configuration

Applications

• Power-Rail Switching
• Multifunction Printers
• Large-format Copiers
• Telecommunications Equipment
• High-performance Computing 5V, 9V, 12V, and 20V Point-of-Load Power Distribution
• Motor Drives ON 1 FAULT CAP GND SEL0 2 VIN 4 VOUT SEL1 RSET IOUT VIN VIN 5 VIN 7 VOUT12 VOUT VOUT VIN VOUT 18-pin STQFN 1.6 x 3.0 mm, 0.40mm pitch (Top View) SLG59H1016V 20VIN ±10% ON

3 V FS - Connect

100 kΩ Linear Ramp Control State Machine (CL/SC Detection and Over Temperature Protection) DischargeCMOS Input VIN OVLO 24V RSET 30.1 kΩ 47 μF 84.5 kΩ GND OFF CLOAD 22 μF 1 to 22μF 0.1 μF VLOGIC 0.18 nF RPU1 10 kΩ VLOGIC SEL0 SEL1 CAP VIN RSET IOUT VOUT ON

000-0059H1016-100 Page 2 of 23 SLG59H1016V Pin Description

Ordering Information

Pin # Pin Name Type Pin Description

1 ON Input

A low-to-high transition on this pin initiates the operation of the SLG59H1016V’s state machine. ON is an asserted HIGH, level-sensitive CMOS input with VIL < 0.3 V and VIH > 0.9 V. As the ON pin input circuit does not have an internal pull-down resistor, connect this pin to a general-purpose output (GPO) of a microcontroller, an application processor, or a system controller – do not allow this pin to be open-circuited.

2 SEL0 Input

As level-sensitive, CMOS inputs with VIL < 0.3 V and VIH > 1.65 V, the SEL0 (LSB) and the SEL1 (MSB) pins select one of four VIN overvoltage lockout thresholds. Please see the Applications Section for additional information and the Electrical Characteristics table for the VIN overvoltage thresholds. A logic LOW on either pin is achieved by connecting the pin of interest to GND; a logic HIGH on either pin is achieved by connecting a 10 kΩ external resistor from the pin in question to the system’s local logic supply. 3G N D G N D Pin 3 is the main ground connection for the SLG59H1016V’s internal charge pump, its gate drive and current-limit circuits as well as its internal state machine. Therefore, use a short, stout connection from Pin 3 to the system’s analog or power plane. 4-8 VIN MOSFET VIN supplies the power for the operation of the SLG59H1016V, its internal control circuit- ry, and the drain terminal of the nFET power switch. With 5 pins fused together at VIN, connect a 47 μF (or larger) low-ESR capacitor from this pin to ground. Capacitors used at VIN should be rated at 50 V or higher. 9-13 VOUT MOSFET Source terminal of n-channel MOSFET (5 pins fused for VOUT). Connect a 22 μF (or larger) low-ESR capacitor from this pin to ground. Capacitors used at VOUT should be rated at 50 V or higher.

14 SEL1 Input Please see SEL0 Pin Description above

15 FAULT Output

An open drain output, FAULT is asserted within TFAULTLOW when a VIN overvoltage, a current-limit, a nFET SOA, or an over-temperature condition is detected. FAULT is deas- serted within TFAULTHIGH when the fault condition is removed. Connect an 100 kΩ ex- ternal resistor from the FAULT pin to local system logic supply.

16 CAP Output

A low-ESR, stable dielectric, ceramic surface-mount capacitor connected from CAP pin to GND sets the VOUT slew rate and overall turn-on time of the SLG59H1016V. For best performance, the range for CSLEW values are 10 nF ≤ CSLEW ≤ 20 nF – please see typical characteristics for additional information. Capacitors used at the CAP pin should be rated at 10 V or higher. Please consult Applications Section on how to select CSLEW based on VOUT slew rate and loading conditions.

17 IOUT Output

IOUT is the SLG59H1016V’s power MOSFET load current monitor output. As an analog output current, this signal when applied to a ground-reference resistor generates a volt- age proportional to the current through the n-channel MOSFET. The IOUT transfer char- acteristic is typically 10 μA/A with a voltage compliance range of 0.5 V ≤ VIOUT ≤ 4V. Optimal IOUT linearity is exhibited for 0.5 A ≤ IDS ≤ 3.5 A. In addition, it is recommended to bypass the IOUT pin to GND with a 0.18 nF capacitor.

18 RSET Input

A 1%-tolerance, metal-film resistor between 23.5 kΩ and 95 kΩ sets the SLG59H1016V’s active current limit. A 95 kΩ resistor sets the SLG59H1016V’s active current limit to 1 A and a 23.5 kΩ resistor sets the active current limit to 4 A. Part Number Type Production Flow SLG59H1016V STQFN 18L FC Extended Industrial, -40 °C to 125 °C SLG59H1016VTR STQFN 18L FC (Tape and Reel) Extended Industrial, -40 °C to 125 °C

000-0059H1016-100 Page 3 of 23 SLG59H1016V Absolute Maximum Ratings Parameter Description Conditions Min. Typ. Max. Unit VIN to GND Power Switch Input Voltage to GND Continuous -0.3 -- 30 V Maximum pulsed VIN, pulse width <0.1s -- -- 32 V VOUT to GND Power Switch Output Voltage to GND -0.3 -- V IN V ON, SEL[1,0], CAP, RSET, IOUT, and FAULT to GND ON, SEL[1,0], CAP, RSET, IOUT, and FAULT Pin Voltages to GND -0.3 -- 7 V TS Storage Temperature -65 -- 150 °C ESDHBM ESD Protection Human Body Model 2000 -- -- V ESDCDM ESD Protection Charged Device Model 500 -- -- V MSL Moisture Sensitivity Level 1 θJA Thermal Resistance 1.6 x 3.0 mm 18L STQFN; De- termined with the device mount- ed onto a 1 in2, 1 oz. copper pad of FR-4 material -- 40 -- °C/W MOSFET IDSCONT Continuous Current from VIN to VOUT TJ < 150°C -- -- 4 A MOSFET IDSPEAK Peak Current from VIN to VOUT Maximum pulsed switch current, pulse width < 1 ms -- -- 5 A Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above thos e indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Electrical Characteristics

4.5 V ≤ VIN ≤ 22 V; CIN = 47 μF, TA = -40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C Parameter Description Conditions Min. Typ. Max. Unit VIN Operating Input Voltage 4.5 -- 22 V VIN(OVLO) VIN Overvoltage Lockout Threshold VIN(UVLO) VIN Undervoltage Lockout Threshold VIN ↓ 1.9 -- 3.8 V IQ Quiescent Supply Current ON = HIGH; IDS = 0 A -- 0.5 0.7 mA ISHDN OFF Mode Supply Current ON = LOW; IDS = 0 A -- 1 12 µA RDSON Static Drain to Source ON Resis- tance TA = 25°C; IDS = 0.1 A -- 13.1 14 m Ω TA = 125°C; IDS = 0.1 A -- 20 22 m Ω ILIMIT Short-circuit Current Limit, ISCL VOUT < 0.5 V -- 0.5 -- A TACL Active Current Limit Response Time -- 120 -- µs

000-0059H1016-100 Page 4 of 23 SLG59H1016V RDSCHRG Output Discharge Resistance 3.5 4.4 5.3 k Ω IOUT MOSFET Current Analog Monitor Output ILOAD = 1 A 8.8 9.9 11 µA ILOAD = 3 A 27 30 33 µA TIOUT IOUT Response Time to Change in Main MOSFET Current CIOUT = 180 pF; Step load 0 to 2.4 A; 0% to 90% IOUT -- 45 -- µs CLOAD Output Load Capacitance C LOAD connected from VOUT to GND -- 22 -- µF TON_Delay ON Delay Time 50% ON to 10% VOUT ↑; VIN = 4.5 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10 µF -- 0.4 0.5 ms 50% ON to 10% VOUT ↑; VIN = 22 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10µF -- 0.8 1.2 ms TTotal_ON Total Turn-on Time 50% ON to 90% VOUT ↑ Set by External CSLEW 1 ms 50% ON to 90% VOUT ↑; VIN = 4.5 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10 µF -- 1.4 2.1 ms 50% ON to 90% VOUT ↑; VIN = 22 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10 µF -- 5 8 ms VOUT(SR) VOUT Slew rate 10% VOUT to 90% VOUT ↑ Set by External CSLEW

1 V/ms

10% VOUT to 90% VOUT ↑; VIN = 4.5 to 22 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10 µF 2.4 3.2 4.0 V/ms TOFF_Delay OFF Delay Time 50% ON to VOUT ↓; RLOAD = 100 Ω, No CLOAD -- 18 -- µs TFall VOUT Fall Time ON = HIGH-to-LOW; RLOAD = 100 Ω, No CLOAD 81 3 2 0 µ s TFAULTLOW FAULT Assertion Time Abnormal Step Load Current event to Fault↓; IACL = 1 A; VIN = 22 V; RSET = 90 kΩ; switch in 20 Ω load; -- 80 -- µs TFAULTHIGH FAULT De-assertion Time Delay to FAULT↑ after fault condition is removed; IACL = 1 A; VIN = 22 V; RSET = 90 kΩ; switch out 20 Ω load -- 180 -- µs FAULTVOL FAULT Output Low Voltage I FAULT = 1 mA -- 0.2 -- V ON_VIH ON Pin Input High Voltage 0.9 -- 5 V ON_VIL ON Pin Input Low Voltage -0.3 0 0.3 V SEL[1,0]_VIH SEL[1,0] pins Input High Voltage 1.65 -- 4.5 V SEL[1,0]_VIL SEL[1,0] pins Input Low Voltage -0.3 -- 0.3 V ION(Leakage) ON Pin Leakage Current 1V ≤ ON ≤ 5V or ON = GND -- -- 1 µA THERMON Thermal Protection Shutdown Threshold -- 150 -- °C THERMOFF Thermal Protection Restart Thresh- old -- 125 -- °C Notes: 1. Refer to typical Timing Parameter vs. C SLEW performance charts for additional information when available. Electrical Characteristics (continued) 4.5 V ≤ VIN ≤ 22 V; CIN = 47 μF, TA = -40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C Parameter Description Conditions Min. Typ. Max. Unit

000-0059H1016-100 Page 5 of 23 SLG59H1016V TTotal_ON, TON_Delay and Slew Rate Measurement Timing Details 90% VOUT 50% ON TON_Delay VOUT(SR) (V/ms) ON VOUT TTotal_ON 10% VOUT 50% ON 10% VOUT TOFF_Delay TFALL 90% VOUT

000-0059H1016-100 Page 6 of 23 SLG59H1016V Typical Performance Characteristics RDSON vs. Temperature and VIN IACL vs. Temperature, RSET, and VIN

000-0059H1016-100 Page 7 of 23 SLG59H1016V IOUT vs. MOSFET IDS and VIN IOUT vs. Temperature, MOSFET IDS, and VIN

000-0059H1016-100 Page 8 of 23 SLG59H1016V VOUT Slew Rate vs. Temperature, VIN, and CSLEW TTotal_ON vs. CSLEW, VIN, and Temperature

000-0059H1016-100 Page 13 of 23 SLG59H1016V Timing Diagram - Basic Operation including Active Current Limit Protection VIN ON Time LOW HIGH 3.5 V TFAULTHIGH VOUT IDS 90% 10% TRISE Active Current Limit Operation FAULT 0.25 V HIGH ISCL IACL ISCL IACL ON TFAULTLOW Nominal Steady State Operation ResumesACL Threshold Triggered Abnormal Step Load Current Event TON_Delay TTotal_ON

000-0059H1016-100 Page 14 of 23 SLG59H1016V Timing Diagram - Active Current Limit & Thermal Protection Operation VOUT IDS 90% 10% TRISE TON_Delay Active Current Limit Operation Thermal Protection Operation ISCL IACL ISCL IACL TFAULTHIGHFAULT VIN ON Time LOW HIGH 3.5 V Nominal Steady State Operation Resumes TFAULTLOW Die temp > THERMON Abnormal Step Load Current Event Die temp < THERMOFF TTotal_ON

000-0059H1016-100 Page 15 of 23 SLG59H1016V Timing Diagram - Basic Operation including Active Current + Internal FET SOA Protection VIN ON Time LOW HIGH 3.5 V TFAULTHIGH VOUT IDS 90% 10% 0.2s Active Current Limit Operation FAULT 0.25 V HIGH ISCL IACL ISCL IACL ON TFAULTLOW ACL Threshold Triggered Nominal Steady State Operation Resumes Automatic restart after 0.2s “cool off” delay FET SOA Threshold Triggered and FET is turned off ACL Threshold Triggered Abnormal Step Load Current Event SOA Threshold TON_Delay TTotal_ON TRISE

000-0059H1016-100 Page 16 of 23 SLG59H1016V Applications Information HFET1 Safe Operating Area Explained Silego’s HFET1 integrated power controllers incorporate a number of internal protection featur es that prevents them from damaging themselves or any other circuit or subcircuit downstr eam of them. One particular protection feature is their Safe Operation Area (SOA) protection. SOA pr otection is automatically activated under overpower and, in some cases, under overcurrent conditions. Overpower SOA is activated if package power dissipation exceeds an internal 5W threshold longer than 2.5 ms. HFET1 devices will quickly switch off (open circuit) upon overpower detection and automatically resume (close) nominal operation once overpower condition no longer exists. One possible way to have an overpower condition trigger SOA protection is when HFET1 products are enabled into heavy output resistive loads and/or into large load capacitors. It is u nder these conditions to follow carefully the “Safe Start-up Loading” guidance in the Applications section of the datasheet. During an overcurrent condition, HFET1 devices will try to limit the output current to the level set by the external R SET resistor. Limiting the output current, however, causes an increased voltage drop across the FET’s channel because the FET’s RDS ON increased as well. Since the FET’s RDS ON is larger, package power dissipation also increases. If the resultant increase in package power dissipation is higher/equal than 5 W for longer than 2.5 ms, internal SOA protection will be triggered a nd the FET will open circuit (switch off). Every time SOA protection is triggered, a ll HFET1 devices will automatically attempt to resume nominal operation after 160 ms. Safe Start-up Condition SLG59H1016V has built-in protection to prevent over-heating during start-up into a heavy load. Overloading the VOUT pin with a capacitor and a resistor may result in non-monotonic V OUT ramping. In general, under light loading on VOUT, V OUT ramping can be controlled with CSLEW value. The following equation serves as a guide: where T RAMP = Total ramping time for VOUT to reach VIN VIN = Input Voltage CSLEW = Capacitor value for CAP pin When capacitor and resistor loading on VOUT during start up, the following tables will ensure VOUT ramping is monotonic without triggering internal protection: Safe Start-up Loading for VIN = 22 V (Monotonic Ramp) Slew Rate (V/ms) C SLEW Control (nF)3 CLOAD (μF) R LOAD (Ω) 0.5 66.7 500 80 1.0 33.3 250 80 1.5 22.2 160 80 2.0 16.7 120 80 2.5 13.3 100 80 CSLEW = TRAMP VIN x 4.9 μA x 20

000-0059H1016-100 Page 17 of 23 SLG59H1016V Note 3: Select the closest-value tolerance capacitor. Setting the SLG59H1016V’s Active Current Limit Setting the SLG59H1016V’s Input Overvoltage Lockout Threshold As shown in the table below, SEL[1,0] selects the VIN overvoltage threshold at which the SLG59H1016V’s internal state machine will turn OFF (open circuit) the power MOSFET if VIN exceeds the selected threshold. For example, SEL[1,1] would be the most appropriate setting for applications where the steady-state VIN can extend up to 20 V without causing any damage to the SLG59H1016V since the IC is 29-V tolerant. With an activated SLG59H1016V (ON=HIGH) and at any time VIN crosses the programmed VIN overvoltage threshold, the state machine opens the power switch and asserts the FAULT pin within TFAULTLOW. In applications with a deactivated or inactive SLG59H1016V (VIN > VIN(UVLO) and ON=LOW) and if the applied VIN is higher than the programmed VIN(OVLO) threshold, the SLG59H1016V’s state machine will keep the power switch open circuited if the ON pin is toggled LOW-to-HIGH. In these cases, the FAULT pin will also be asserted within TFAULTLOW and will remain asserted until VIN resumes nominal, steady-state operation. In all cases, the SLG59H1016V’s VIN undervoltage lockout threshold is fixed at VIN(UVLO). Safe Start-up Loading for VIN = 12 V (Monotonic Ramp) Slew Rate (V/ms) C SLEW Control (nF)3 CLOAD (μF) R LOAD (Ω) 1 33.3 500 20 2 16.7 250 20 3 11.1 160 20 4 8.3 120 20 5 6.7 100 20 R SET (kΩ) Active Current Limit (A) 95 1 45 2 30 3 23.5 4 SEL1 SEL0 V IN(OVLO) (Typ) 00 6 V 0 1 10.8 V 1 0 14.4 V 11 2 4 V

000-0059H1016-100 Page 18 of 23 SLG59H1016V Power Dissipation The junction temperature of the SLG59H1 016V depends on different factors such as board layout, ambient temperature, and other environmental factors. The primary contributor to the increase in the junction temperature of the SLG59H1016V is the power dissipation of its power MOSFET. Its power dissipation and the junction temperature in nominal operating mode can be calculated using the following equations: where: PD = Power dissipation, in Watts (W) RDSON = Power MOSFET ON resistance, in Ohms (Ω) IDS = Output current, in Amps (A) and where: TJ = Junction temperature, in Celsius degrees (°C) θJA = Package thermal resistance, in Celsius degrees per Watt (°C/W) TA = Ambient temperature, in Celsius degrees (°C) In current-limit mode, the SLG59H1016V’s power dissipation can be calculated by taking into account the voltage drop across the power switch (VIN - VOUT) and the magnitude of the output current in current-limit mode (IACL): where: PD = Power dissipation, in Watts (W) VIN = Input Voltage, in Volts (V) RLOAD = Load Resistance, in Ohms (Ω) IACL = Output limited current, in Amps (A) VOUT = RLOAD x IACL PD = RDSON x IDS TJ = PD x θJA + TA PD = (VIN-VOUT) x IACL or PD = (VIN – (RLOAD x IACL)) x IACL

000-0059H1016-100 Page 19 of 23 SLG59H1016V Package Top Marking System Definition 1016V Part Code Pin 1 Identifier WWNNN Date Code + LOT Code ARR Assembly + Rev. Code 1016V - Part ID Field WW - Date Code Field1 NNN - Lot Traceability Code Field1 A - Assembly Site Code Field 2 RR - Part Revision Code Field2 Note 1: Each character in code field can be alphanumeric A-Z and 0-9 Note 2: Character in code field can be alphabetic A-Z

000-0059H1016-100 Page 20 of 23 SLG59H1016V Package Drawing and Dimensions 18 Lead TQFN Package 1.6 x 3 mm (Fused Lead) JEDEC MO-220, Variation WCEE

000-0059H1016-100 Page 21 of 23 SLG59H1016V SLG59H1016V 18-pin STQFN PCB Landing Pattern Note: All dimensions shown in micrometers (μm)

000-0059H1016-100 Page 22 of 23 SLG59H1016V Tape and Reel Specifications Carrier Tape Drawing and Dimensions Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: late st revision for reflow profile based on package volume of 2.64 mm 3 (nominal). More information can be found at www.jedec.org. Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm]per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 18L 0.4P FC Green 18 1.6 x 3 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W STQFN 18L 0.4P FC Green Refer to EIA-481 specification

000-0059H1016-100 Page 23 of 23 SLG59H1016V

Revision History

2/24/2017 1.00 Production Release