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Document overview

  • Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 8

Technical content

Features

  • 5V ±5% Power supply
  • SLG55021 Drain Voltage Range 1.0V to 20V
  • Internal Gate Voltage Charge Pump
  • Controlled Turn on Delay
  • Controlled Load Discharge Rate
  • Controlled Turn on Slew Rate
  • Stable Slew Rate (±2% typ) over Temperature Range
  • TDFN-8 Package

Applications

  • Power Rail Switches
  • Hot Plugging Applications
  • Soft Switching
  • Personal computers and Servers
  • Data Communications Equipment Pin Configuration DGND S G PG SHDN# TDFN-8 ON VCC (Top View) SLG55021 D LOAD G S ON G CC D Timing & Logic SHDN# Q-PUMP PG8 Discharge SLG55021 For N-MOSFETS with VGS < 20V

000-0055021-102 Page 2 of 8 SLG55021-200010V Pin Description Overview The SLG55021 N-Channel FET Gate Driver is used for controlling a delayed turn on and ramping slew rate of the source voltage on N-Channel FET switches from a CMOS logic level input. Intended as a supporting control element for switched voltage rails in energy efficient, advanced power management systems, the SLG55021 also integrates circuits to discharge opened switched voltage rails. The gate driver is available in a variety of co nfigurations supporting a range of turn-on slew rates from 0.80V /ms up to 4V/ms which, depending on load supplying source voltages in the range of 1.0V to 20V results in ramp times from 200 s up to over 20ms (see Application Section). Delays until the ramp begins are source voltage independent and range from 250s to 5ms. A power good condition is output to indicate that the ramp-up slew of the s ource voltage is finished. Additionally, a n internal discharge circuit provides a controlled path to remo ve charge from open power ra ils. The SLG55021 gate drive is packaged in an 8 pin DFN package. When used with external N-Channel FETs, the SLG55021 supports low transient, energy efficient switching of high current loads at source voltages ranging from 1.0V to 20V. Pin Name Pin Number Type Pin Description VCC 1 Power Supply Voltage ON 2 Input CMOS Logic Level. High True SHDN# 3 Input Shut Down# - Low True Signal which immediately turns FET off GND 4 GND Ground D 5 Input FET Drain Connection S 6 Input Source Connection G 7 Output FET Gate Drive PG 8 Output Output CMOS Open Drain - Power Good, indicates external FET fully on

Ordering Information

(Volts/ms) Delay Time (ms) Discharge Resistor (ohms) Package Type SLG55021-200010V 2.0 0.15 200 TDFN-8 SLG55021-200010VTR 2.0 0.15 200 TDFN-8 - Tape and Reel (3k units)

000-0055021-102 Page 3 of 8 SLG55021-200010V * If using an open drain to drive SHDN#; pull up with 10k to VCC Absolute Maximum Conditions Parameter Min. Max. Unit VD or VS to GND -0.3 40.0 V Voltage at Logic Input pins -0.3 6.5 V Current at input pin -1.0 1.0 mA Storage temperature range -65 150 °C Operating temperature range -55 125 °C Junction temperature -- 150 °C ESD Human Body Model -- 2000 V ESD Machine Model -- 200 V Electrical Characteristics (-10°C to 75°C) Symbol Parameter Condition/Note Min. Typ. Max. Unit VCC Supply Voltage 4.75 5.0 5.25 V Iq Quiescent Current VG not ramping FET = ON -- <7 10 A VG not ramping FET = OFF -- 0.1 1 A VD FET Drain Voltage SLG55021 1.0 -- 20 V VGS Gate-Source Voltage SLG55021 8.0 11.5 13 V CG FET Gate Capacitance 500 -- 8000 pF TDELAY Ramp Delay Range 1.5ms Default, 500s step 0.105 0.15 0.195 ms TSLEW FET Turn on Slew Rate 1.4 2.0 2.6 V/ms IDISCHARGE Internal Discharge Resistor Nominal discharge time of ~100ms 10mA max rate 100 200 300  VIH HIGH-level input voltage ON, SHDN# (200mV Hysteresis) 2.4 -- 5.5 V VIL LOW-level Input voltage ON, SHDN# (200mV Hysteresis) -- -- 0.4 V VOH HIGH-level output voltage PG Open Drain -- -- 5.5 V IOL_LOGIC Logic LOW level output PG Sink Current 1 2 3 mA IIH * SHDN# VIH = 3.3V -- -- <1.0 A IG_OL Gate Drive Sink Current 400 -- -- A IG_OH Gate Drive Source Current 32 -- -- A ID_IH Drain Pin Current VD = 20V in Standby -- -- <1.0 A IS_IH Source Pin Current Qu- iesent VS = 20V -- -- <1.0 A

000-0055021-102 Page 4 of 8 SLG55021-200010V Application Example In a typical application, de-asserting ON (low) or asserting the low true Shut Down signal (SHDN#) turns off the external power N-FET. SHDN# is provided as an asynchronous override to the ON signal. When the FET is turned off, the voltage at the load is discharged through a resistor (typically 200 ohms) internal to the SLG55021 with the discharge current limited to a maximum of 10mA. When ON is asserted (high), gate voltage is not applied to the gate of the external power N-FET until after TDELAY then the gate source (Vgs) voltage is ramped up to 11.5V above the source voltage VS at a slew rate determined by the internal slew rate control element internal to the SLG55021. Monotonic rise of Vs is maintained even as ID increases dramatically after the load device turn on threshold voltage is reached. After the source voltage has ramped up to its maximum steady state value, the Open Drain PG (Power Good) signal is asserted. PG may be used as the ON control of a second SLG55021 thereby providing power on sequence control of a number of swit ched power rails, or used in a ‘wired and’ with other PG signals to indicate all switched power rails are in a power good condition. The devices will not operate if Vcc is below 3.5V. The waveforms shown illustrate the monotonic rise of the source voltage of a FET as gate voltage is controlled to accommodate for variations in load current as the voltage is applied.

000-0055021-102 Page 5 of 8 SLG55021-200010V Package Top Marking System Definition Part ID Assembly Code Datecode Lot Revision 8 7 6 5 1 2 3 4 – Part ID Field: identifies the specific device configuration – Assembly Code Field: Assembly Location of the device. – Date Code Field: Coded date of manufacture – Lot Code: Designates Lot # – Revision Code: Device Revision XX A DD L R

000-0055021-102 Page 6 of 8 SLG55021-200010V Package Drawing and Dimensions

8 Lead TDFN Package

Note: Bottom side metal plate is at ground potential

000-0055021-102 Page 7 of 8 SLG55021-200010V Tape and Reel Specifications Tape and Reel Drawing Package Type # of Pins Nominal Package Size Units per Reel Trailer A Leader B Pocket Tape(mm) Reel Diameter (mm)Pockets Length (mm) Pockets Length( mm) Width Pitch 8TDFN 8 2x2mm 3,000 42 168 42 168 8 4 178

000-0055021-102 Page 8 of 8 SLG55021-200010V

Revision History

9/26/2016 1.02 Removed TBD values Fixed typos