SLG46580

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Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 194

Technical content

Features

• Programmable Asynchronous State Machine
• Logic & Mixed Signal Circuits
• Highly Versatile Macrocells
• Read Back Protection (Read Lock)
• Four 150 mA LDO R egulators (SLG46580)
• Two 300 mA LDO Regulators (SLG46582)
• One 600 mA LDO Regulators (SLG46583) 2C Interface
• 2.5 V (±8%) to 5 V (±10%) Supply
• Operating Temperature Range: -40°C to 85°C
• RoHS Compliant / Halogen-Free
• 20-pin STQFN: 2 x 3 x 0.55 mm, 0.4 mm pitch Pin Configuration STQFN-20 (Top View) LDO VOUT* LDO VIN* LDO VOUT* IO3 IO2 IO1 IO0 IO5 IO4 LDO VIN* LDO VOUT* LDO VOUT* SDA SCL IO6 IO8 IO7 GND AGND VDD Note*: See LDO Connection Block Diagram 161 8 9 10 20 17 IO3 ACMP Vref Programmable Delay with Edge Detector IO0 ACMP0 ACMP1 ACMP2 ACMP3 Additional Logic Functions Combination Function Macrocells 3-bit LUT3_0 or DFF3 3bit LUT3_1 or DFF4 3-bit LUT3_4 or DFF7 I2C Serial Communication Asynchronous State Machine 8 states 3-bit LUT3_6 or CNT/DLY0 3-bit LUT3_7 or CNT/DLY1 3-bit LUT3_9 or CNT/DLY3 3-bit LUT3_10 or CNT/DLY4 FILTER_0 with Edge Detect

8 Byte RAM +

LUT3_3 or DFF6 Analog Temperature Sensor 2-bit LUT2_0 or DFF0 2-bit LUT2_1 or DFF1 3-bit LUT3_8 or CNT/DLY2 3-bit LUT3_11 or Pipe Delay/ Ripple CNT 3-bit LUT3_2 or DFF5 2-bit LUT2_2 or DFF2 IO1 Analog IO2 IO4 Analog IO5 VDD AGND LDO VOUT SCL SDA IO6 Analog GND IO8 Analog IO7 Analog FILTER_1 with Edge Detect Oscillators 25kHz / 2 MHz 2 kHz RTC CNT 4-bit LUT4x2_0 POR 3-bit LUT3_5 or DFF8 Tri-Mode LDO Regulator LDO VIN LDO VOUT LDO VOUT LDO VIN LDO VOUT 2x300 mA LDO for SLG46582 1x600 mA LDO for SLG46583 4x150 mA LDO for SLG46580

SLG46580/82/83_DS_062 Page 1 of 193 SLG46580/82/83 Preliminary LDO Connection Block Diagram Note 1: For SLG46582 both LDO0 VOUT (Pins 11 and 13) must be connected together externally, both LDO1 VOUT (Pins 14 and 16) must be connected together externally. Note 2: For SLG46583 both LDO VIN (Pins 12 and 15) must be connected together externally. All four LDO VOUT (Pins 11, 13, 14 and 16) must be connected together externally. LDO3 VOUT LDO2/3 VIN LDO2 VOUT LDO1 VOUT LDO0/1 VIN LDO0 VOUT150 mA LDO0 150 mA LDO1 150 mA LDO2 150 mA LDO3 LDO1 VOUT LDO1 VIN LDO1 VOUT LDO0 VOUT LDO0 VIN LDO0 VOUT 300 mA LDO0 300 mA LDO1 LDO VOUT LDO VIN LDO VOUT LDO VOUT LDO VIN LDO VOUT 600 mA LDO SLG46580 SLG46582 SLG46583

SLG46580/82/83_DS_062 Page 2 of 193 SLG46580/82/83 Preliminary

1.0 Overview

The SLG46580/82/83 is a small, low power component commonly use d to integrate mixed-signal functions under control of an asynchronous state machine. The user creates the circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macrocel ls of the SLG46580/82/83. This highly versatile device allows a wide variety of functions and control logic to be designed with in a very small, low power monol ithic integrated circuit. The macrocells in the device include the following:

• Four Analog Comparators (ACMP)
• Voltage Reference (Vref) for ACMPs
• Analog Temperature Sensor
• Fifteen Combination Function Macrocells
• Three Selectable DFF/Latch or 2-bit LUTs
• Six Selectable DFF/Latch or 3-bit LUTs
• One Selectable Pipe Delay or Ripple Counter or 3-bit LUT
• Five 8-bit delays/counters or 3-bit LUTs
• Combinatorial Logic
• One 4-bit LUT with two outputs
• Asynchronous State Machine
• Eight States
• Flexible input logic from state transitions
• Real Time Clock (RTC) Binary Counter
• Four Tri-Mode 150 mA LDO R egulators (for SLG46580):
• High Power Mode (HP Mode): 150 mA output, see Table 9.
• Low Power Mode (LP Mode): 100 µA output, see Table 9.
• Bypass Mode: Acts like a load switch
• Two Tri-Mode 300 mA LDO Regulators (for SLG46582):
• High Power Mode (HP Mode): 300 mA output, see Table 9.
• Low Power Mode (LP Mode): 200 µA output, see Table 9.
• Bypass Mode: Acts like a load switch
• One Tri-Mode 600 mA LDO R egulators (for SLG46583):
• High Power Mode (HP Mode): 600 mA output, see Table 9.
• Low Power Mode (LP Mode): 400 µA output, see Table 9.
• Bypass Mode: Acts like a load switch
• Serial Communications 2C Slave Protocol Interface
• Programmable Delay wi th Edge Detector Output
• Additional Logic Functions
• 2 Deglitch Filters with Edge Detectors
• Two Oscillators (OSC)
• Configurable 25 kHz/2 MHz
• 2 kHz Low Power Oscillator
• Eight Byte RAM + OTP User Memory
• RAM Memory space that is readable and writable via I
• User defined initial values transferred from OTP
• P O R

SLG46580/82/83_DS_062 Page 3 of 193 SLG46580/82/83 Preliminary

2.0 Pin Description

2.1 Functional Pin Description for SLG46580

20L Pin # Pin Name Signal Name Function Input Options Output Options

1 IO0 IO0

with OE* Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input -- EXT_CLK Digital Input without Schmitt Trigger -- Digital Input with Schmitt Trigger -- Low Voltage Digital Input --

2 IO1

Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input Open Drain PMOS (1x) (2x) ACMP0+ Analog Comparator 0 Positive Input Analog --

3 IO2 IO2 General Purpose I/O

Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input Open Drain PMOS (1x) (2x)

4 IO3 IO3 General Purpose I/O

Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input Open Drain PMOS (1x) (2x)

5 IO4

with OE* Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input -- ACMP1+ Analog Comparator 1 Positive Input Analog --

6 IO5 IO5 General Purpose Input

Low Voltage Digital Input --

SLG46580/82/83_DS_062 Page 4 of 193 SLG46580/82/83 Preliminary 7V D D VDD Power Supply -- -- ACMP0+ Analog Comparator 0 Positive Input Analog -- ACMP0- Analog Comparator 0 Negative Input Analog -- ACMP1- Analog Comparator 1 Negative Input Analog -- ACMP2- Analog Comparator 2 Negative Input Analog -- ACMP3- Analog Comparator 3 Negative Input Analog -- 8S C L SCL I 2C Serial Clock Digital Input without Schmitt Trigger -- SCL I 2C Serial Clock Digital Input with Schmitt Trigger -- SCL I 2C Serial Clock Low Voltage Digital Input -- 9S D A SDA I 2C Serial Data Digital Input without Schmitt Trigger Open Drain NMOS SDA I 2C Serial Data Digital Input with Schmitt Trigger -- SDA I 2C Serial Data Low Voltage Digital Input --

10 IO6

with OE* Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input -- EXT_VREF Analog Comparator Negative Input Analog --

11 LDO0 VOUT

LDO0 VOUT LDO0 Output Voltage -- -- ACMP3+ Analog Comparator 3 Positive Input Analog --

12 LDO0/1 VIN

LDO0/1 VIN LDO0/LDO1 Input Voltage -- -- ACMP0+ Analog Comparator 0 Positive Input Analog --

13 LDO1 VOUT LDO1 VOUT LDO1 Output Voltage -- --

14 LDO2 VOUT

LDO2 VOUT LDO2 Output Voltage -- -- ACMP3+ Analog Comparator 3 Positive Input Analog --

15 LDO2/3 VIN

LDO2/3 VIN LDO2/LDO3 Input Voltage -- -- ACMP1+ Analog Comparator 1 Positive Input Analog --

16 LDO3 VOUT LDO3 VOUT LDO3 Output Voltage -- --

17 AGND AGND Analog Ground for

20L Pin # Pin Name Signal Name Function Input Options Output Options

SLG46580/82/83_DS_062 Page 5 of 193 SLG46580/82/83 Preliminary

2.2 Functional Pin Description for SLG46582

18 IO7

Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input Open Drain PMOS (1x) (2x) ACMP2+ Analog Comparator 2 Positive Input Analog --

19 IO8

with OE* Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input -- ACMP3+ Analog Comparator 3 Positive Input Analog --

20 GND GND Ground -- --

Note *: General Purpose I/O's with OE can be used to implement bidirectional signals under user control via Connec- tion Matrix to OE signal in I/O structure. STQFN 20L Pin # Pin Name Signal Name Function Input Options Output Options with OE* Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input -- EXT_CLK Digital Input without Schmitt Trigger -- Digital Input with Schmitt Trigger -- Low Voltage Digital Input -- 2I O 1 IO1 General Purpose I/O Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input Open Drain PMOS (1x) (2x) ACMP0+ Analog Comparator 0 Positive Input Analog -- Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input Open Drain PMOS (1x) (2x) STQFN 20L Pin # Pin Name Signal Name Function Input Options Output Options

SLG46580/82/83_DS_062 Page 6 of 193 SLG46580/82/83 Preliminary Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input Open Drain PMOS (1x) (2x) 5I O 4 IO4 General Purpose I/O with OE* Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input -- ACMP1+ Analog Comparator 1 Positive Input Analog -- Low Voltage Digital Input -- 7V D D VDD Power Supply -- -- ACMP0+ Analog Comparator 0 Positive Input Analog -- ACMP0- Analog Comparator 0 Negative Input Analog -- ACMP1- Analog Comparator 1 Negative Input Analog -- ACMP2- Analog Comparator 2 Negative Input Analog -- ACMP3- Analog Comparator 3 Negative Input Analog -- 8S C L SCL I 2C Serial Clock Digital Input without Schmitt Trigger -- SCL I 2C Serial Clock Digital Input with Schmitt Trigger -- SCL I 2C Serial Clock Low Voltage Digital Input -- 9S D A SDA I 2C Serial Data Digital Input without Schmitt Trigger Open Drain NMOS SDA I 2C Serial Data Digital Input with Schmitt Trigger -- SDA I 2C Serial Data Low Voltage Digital Input -- with OE* Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input -- EXT_VREF Analog Comparator Negative Input Analog -- 11 LDO0 VOUT LDO0 VOUT LDO0 Output Voltage -- -- ACMP3+ Analog Comparator 3 Positive Input Analog -- STQFN 20L Pin # Pin Name Signal Name Function Input Options Output Options

SLG46580/82/83_DS_062 Page 7 of 193 SLG46580/82/83 Preliminary

2.3 Functional Pin Description or SLG46583

12 LDO0 VIN

ACMP0+ Analog Comparator 0 Positive Input Analog -- 13 LDO0 VOUT LDO0 VOUT LDO0 Output Voltage -- -- 14 LDO1 VOUT LDO1 VOUT LDO1 Output Voltage -- -- ACMP3+ Analog Comparator 3 Positive Input Analog --

15 LDO1 VIN

ACMP1+ Analog Comparator 1 Positive Input Analog -- 16 LDO1 VOUT LDO1 VOUT LDO1 Output Voltage -- -- Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input Open Drain PMOS (1x) (2x) ACMP2+ Analog Comparator 2 Positive Input Analog -- with OE* Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input -- ACMP3+ Analog Comparator 3 Positive Input Analog -- Note 1: * General Purpose I/O's with OE can be used to implement bidirectional signals under user control via Connection Matrix to OE signal in I/O structure. Note 2: ** All LDO0 VOUT pins should be connected together externally, and all LDO1 VOUT pins should also be connected together externally for reliable operation. STQFN 20L Pin # Pin Name Signal Name Function Input Options Output Options with OE* Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input -- EXT_CLK Digital Input without Schmitt Trigger -- Digital Input with Schmitt Trigger -- Low Voltage Digital Input -- STQFN 20L Pin # Pin Name Signal Name Function Input Options Output Options

SLG46580/82/83_DS_062 Page 8 of 193 SLG46580/82/83 Preliminary 2I O 1 IO1 General Purpose I/O Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input Open Drain PMOS (1x) (2x) ACMP0+ Analog Comparator 0 Positive Input Analog -- Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input Open Drain PMOS (1x) (2x) Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input Open Drain PMOS (1x) (2x) 5I O 4 IO4 General Purpose I/O with OE* Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input -- ACMP1+ Analog Comparator 1 Positive Input Analog -- Low Voltage Digital Input -- 7V D D VDD Power Supply -- -- ACMP0+ Analog Comparator 0 Positive Input Analog -- ACMP0- Analog Comparator 0 Negative Input Analog -- ACMP1- Analog Comparator 1 Negative Input Analog -- ACMP2- Analog Comparator 2 Negative Input Analog -- ACMP3- Analog Comparator 3 Negative Input Analog -- 8S C L SCL I 2C Serial Clock Digital Input without Schmitt Trigger -- SCL I 2C Serial Clock Digital Input with Schmitt Trigger -- SCL I 2C Serial Clock Low Voltage Digital Input -- STQFN 20L Pin # Pin Name Signal Name Function Input Options Output Options

SLG46580/82/83_DS_062 Page 9 of 193 SLG46580/82/83 Preliminary 9S D A SDA I 2C Serial Data Digital Input without Schmitt Trigger Open Drain NMOS SDA I 2C Serial Data Digital Input with Schmitt Trigger -- SDA I 2C Serial Data Low Voltage Digital Input -- with OE* Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input -- EXT_VREF Analog Comparator Negative Input Analog -- LDO VOUT LDO Output Voltage -- -- ACMP3+ Analog Comparator 3 Positive Input Analog -- 12 LDO VIN LDO VIN LDO Input Voltage -- -- ACMP0+ Analog Comparator 0 Positive Input Analog -- 13* LDO VOUT* LDO VOUT LDO Output Voltage -- -- LDO VOUT LDO Output Voltage -- -- ACMP3+ Analog Comparator 3 Positive Input Analog -- 15 LDO VIN LDO VIN LDO Input Voltage -- -- ACMP1+ Analog Comparator 1 Positive Input Analog -- 16* LDO VOUT* LDO VOUT LDO Output Voltage -- -- Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input Open Drain PMOS (1x) (2x) ACMP2+ Analog Comparator 2 Positive Input Analog -- with OE* Digital Input without Schmitt Trigger Push-Pull (1x) (2x) Digital Input with Schmitt Trigger Open Drain NMOS (1x) (2x) Low Voltage Digital Input -- ACMP3+ Analog Comparator 3 Positive Input Analog -- 20L Pin # Pin Name Signal Name Function Input Options Output Options

SLG46580/82/83_DS_062 Page 10 of 193 SLG46580/82/83 Preliminary Note 1: * General Purpose I/O's with OE can be used to implement bidirectional signals under user control via Connection Matrix to OE signal in I/O structure. Note 2: All LDO VIN pins should be connected together externally for reliable operation. Note 3: * All LDO VOUT pins should be connected together externally for reliable operation. STQFN 20L Pin # Pin Name Signal Name Function Input Options Output Options

SLG46580/82/83_DS_062 Page 11 of 193 SLG46580/82/83 Preliminary

2.4 Pin Configuration - STQFN20L

Pin # Signal Name Pin Functions

1 IO0 GPIO with OE* / EXT_CLK

2 IO1 GPIO / ACMP0+

3 IO2 GPIO

4 IO3 GPIO

5 IO4 GPIO with OE*/ ACMP1+

7 VDD Power Supply

10 IO6 GPIO with OE* / EXT_VREF

11 LDO0 VOUT (SLG46580) LDO0 Output Voltage LDO0 VOUT (SLG46582) LDO0 Output Voltage LDO VOUT (SLG46583) LDO Output Voltage 12 LDO0/1 VIN (SLG46580) LDO0/LDO1 Input Voltage LDO0 VIN (SLG46582) LDO0 Input Voltage LDO VIN (SLG46583) LDO Input Voltage 13 LDO1 VOUT (SLG46580) LDO1 Output Voltage LDO0 VOUT (SLG46582) LDO0 Output Voltage LDO VOUT (SLG46583) LDO Output Voltage 14 LDO2 VOUT (SLG46580) LDO2 Output Voltage LDO1 VOUT (SLG46582) LDO1 Output Voltage LDO VOUT (SLG46583) LDO Output Voltage 15 LDO2/3 VIN (SLG46580) LDO2/LDO3 Input Voltage LDO1 VIN (SLG46582) LDO1 Input Voltage LDO VIN (SLG46583) LDO Input Voltage 16 LDO3 VOUT (SLG46580) LDO3 Output Voltage LDO1 VOUT (SLG46582) LDO1 Output Voltage LDO VOUT (SLG46583) LDO Output Voltage

17 AGND Analog Ground for LDOs

18 IO7 GPIO / ACMP2+

19 IO8 GPIO with OE*/ ACMP3+

20 GND Ground

Note*: General Purpose I/O's with OE can be used to implement bidirec- tional signals under user control via Connection Matrix to OE signal in I/O structure. Note**: For SLG46582 both LDO0 VOUT (Pins 11 and 13) must be con- nected together externally, both LDO1 VOUT (Pins 14 and 16) must be connected together externally. For SLG46583 both LDO VIN (Pins 12 and 15) must be connected together externally. All four LDO VOUT (Pins 11, 13, 14 and 16) must be connected together externally. LDO VOUT LDO VIN LDO VOUT IO3 IO2 IO1 IO0 1 IO5 IO4 5 LDO VIN LDO VOUT LDO VOUT11 SDA SCL 8 9 IO6 IO8 IO7 1819 GND STQFN-20 AGND VDD (Marking View)

3.0 User Programmability

configure the connection matrix and macrocells. A programming development kit allows the user the ability to create initial devices. Once the design is finalized, the programming code (.gpx file) is forwarded to Silego to integrate into a production process. Figure 1. Steps to create a custom Silego GreenPAK device

SLG46580/82/83_DS_062 Page 13 of 193 SLG46580/82/83 Preliminary

4.0 Ordering Information

Note*: The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: Silego has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in produc tion to support existing customers, but Silego does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: Silego has discontinued the production of the device. Part Number Type Status* SLG46580V 20-pin STQFN ACTIVE SLG46580VTR 20-pin STQFN - Tape and Reel (3k units) ACTIVE SLG46582V 20-pin STQFN PREVIEW SLG46582VTR 20-pin STQFN - Tape and Reel (3k units) PREVIEW SLG46583V 20-pin STQFN PREVIEW SLG46583VTR 20-pin STQFN - Tape and Reel (3k units) PREVIEW

SLG46580/82/83_DS_062 Page 14 of 193 SLG46580/82/83 Preliminary

5.0 Electrical Specifications

5.1 Absolute Maximum Conditions

5.2 Electrical Characteristics

Parameter Min. Max. Unit Supply Voltage on VDD relative to GND -0.3 7 V DC Input Voltage GND - 0.5 V VDD + 0.5 V V Maximum Average or DC Current (Through pin) Push-Pull 1x -- 31 mA Push-Pull 2x -- 43 OD 1x -- 41 OD 2x -- 65 Current at Input Pin -1.0 1.0 mA Input leakage (Absolute Value) -- 1000 nA Storage Temperature Range -65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1300 -- V Moisture Sensitivity Level 1 Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage (see Note 1) 2.3 3.3 5.5 V VPP Programming Voltage 7.25 7.50 7.75 V TA Operating Temperature -40 25 85 °C CVDD Capacitor Value at VDD -- 0.1 -- F VAIR Analog Input Common Mode Range Negative ACMP Input 0 -- 1.2 V VAIH Analog Input Voltage HIGH-Level Allowable Input Voltage at Analog Pins 0 -- V DD V VIH HIGH-Level Input Voltage Logic Input (see Note 2) 0.7x VDD -- VDD+ 0.3 V Logic Input with Schmitt Trigger 0.8x VDD -- VDD+ 0.3 V Low-Level Logic Input (see Note 2) 1.25 -- VDD+ 0.3 V VIL LOW-Level Input Voltage Logic Input (see Note 2) GND- 0.3 -- 0.3x VDD V Logic Input with Schmitt Trigger GND- 0.3 -- 0.2x VDD V Low-Level Logic Input (see Note 2) GND- 0.3 -- 0.5 V VHYS Schmitt Trigger Hysteresis Voltage VO Maximal Voltage Applied to any PIN in High Impedance State -- -- V DD+ 0.3 V

SLG46580/82/83_DS_062 Page 15 of 193 SLG46580/82/83 Preliminary VOH HIGH-Level Output Voltage Push-Pull, 1X Drive, Push-Pull, 1X Drive, Push-Pull, 1X Drive, VDD = 5 V +/- 10%, IOH = 5 mA 4.19 4.78 -- V Push-Pull, 2X Drive, Push-Pull, 2X Drive, Push-Pull, 2X Drive, VDD = 5 V +/- 10%, IOH = 5 mA 4.32 4.89 -- V VOL LOW-Level Output Voltage Push-Pull, 1X Drive, Push-Pull, 1X Drive, Push-Pull, 1X Drive, Push-Pull, 2X Drive, Push-Pull, 2X Drive, Push-Pull, 2X Drive, VDD = 5 V +/- 10%, IOL = 5 mA -- 0.08 0.14 V NMOS OD, 1X Drive, NMOS OD, 1X Drive, NMOS OD, 1X Drive, VDD = 5 V +/- 10%, IOL = 5 mA -- 0.10 0.18 V NMOS OD, 2X Drive, NMOS OD, 2X Drive, NMOS OD, 2X Drive, VDD = 5 V +/- 10%, IOL = 5 mA -- 0.05 0.11 V IOH HIGH-Level Output Current Push-Pull, 1X Drive, Push-Pull, 1X Drive, Push-Pull, 1X Drive, VDD = 5 V +/- 10%, VOH = 2.4 V 22.08 34.04 -- mA Push-Pull, 2X Drive, Push-Pull, 2X Drive, Push-Pull, 2X Drive, VDD = 5 V +/- 10%, VOH = 2.4 V 41.46 68.08 -- mA Symbol Parameter Condition/Note Min. Typ. Max. Unit

SLG46580/82/83_DS_062 Page 16 of 193 SLG46580/82/83 Preliminary IOL LOW-Level Output Current Push-Pull, 1X Drive, Push-Pull, 1X Drive, Push-Pull, 1X Drive, Push-Pull, 2X Drive, Push-Pull, 2X Drive, Push-Pull, 2X Drive, VDD = 5 V +/- 10%, VOL = 0.4 V 13.83 23.16 -- mA NMOS OD, 1X Drive, NMOS OD, 1X Drive, NMOS OD, 1X Drive, VDD = 5 V +/- 10%, VOL = 0.4 V 10.82 17.38 -- mA NMOS OD, 2X Drive, NMOS OD, 2X Drive, NMOS OD, 2X Drive, VDD = 5 V +/- 10%, VOL = 0.4 V 17.34 34.76 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 3) IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 3) T TSU Startup Time From V DD rising past PONTHR -- 1.3 -- ms PONTHR Power On Threshold V DD Level Required to Start Up the Chip 1.34 1.55 1.74 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 1.05 1.25 1.45 V RPUP Pull Up Resistance

1 M Pull Up 748 1039 1378 k 

100 k Pull Up 85 105 130 k  10 k Pull Up 8 11 14 k  RPDWN Pull Down Resistance

1 M Pull Down 855 1046 1333 k 

100 k Pull Down 85 105 131 k  10 k Pull Down 8 11 14 k  CIN Input Capacitance -- 4 -- pF Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: No hysteresis. Note 3: The GreenPAK’s power rails are divided in two sides. IOs 0, 1, 2, 3, 4 and 5 are connected to one side, IOs 6, 7, 8, SCL and SDA to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

SLG46580/82/83_DS_062 Page 17 of 193 SLG46580/82/83 Preliminary

5.3 I2C Specifications

5.4 Asynchronous State Machine (ASM) Specifications

Symbol Parameter Condition/Note Fast-Mode Fast-Mode Plus Unit tI Input Filter Spike Suppression (SCL, SDA) tBUF Bus Free Time between Stop Note: Timing diagram can be found in the Figure 83. Symbol Parameter Condition/Note Min. Typ. Max. Unit tst_out_delay Asynchronous State Machine Output Delay Time VDD = 2.5 V ± 8% 225 -- 275 nsVDD = 3.3 V ± 10% 95 118 VDD = 5.0 V ± 10% 67 -- 77 tst_out Asynchronous State Machine Output Transition Time nsVDD = 3.3 V ± 10% 70 tst_pulse Asynchronous State Machine Input Pulse Acceptance Time nsVDD = 3.3 V ± 10% 14 tst_comp Asynchronous State Machine Input Compete Time nsVDD = 3.3 V ± 10% 14

5.5 IDD Estimator

5.6 Macrocells Timing

Table 1. Typical Current Estimated for Each Macrocell at T=25°C. Table 2. Typical Delay Estimated for Each Macrocell at T=25°C.

Table 3. Programmable Delay Expected Delays and Pulse Widths (typical). Table 4. Typical Pulse Width that will be Filtered out by Filter Macrocell (at T=25°C).

5.7 Counter/Delay Specifications

5.7.1 OSC Power On delay

Table 5. Typical Counter/Delay Offset. Table 6. Oscillators Power On delay at room temperature, DLY/CNT Counter data = 100; RC OSC power setting: "Auto Table 7. Oscillators Power On delay at room temperature, DLY/CNT Counter data = 100; RC OSC power setting: "Auto

5.8 ACMP Specifications

Table 8. ACMP Specifications

SLG46580/82/83_DS_062 Page 23 of 193 SLG46580/82/83 Preliminary VHYS Built-in Hysteresis VHYS = 25 mV VIL = Vin - VHYS/2 VIH = Vin + VHYS/2 LB - Enabled, T = 25°C 3.48 -- 38.4 mV LB - Disabled, T = 25°C 14.6 -- 36.7 mV VHYS = 50 mV VIL = Vin - VHYS VIH = VHYS LB - Enabled, T = 25°C 43.9 -- 57.1 mV LB - Disabled, T = 25°C 44.1 -- 53.7 mV VHYS = 200 mV VIL = Vin - VHYS VIH = VHYS LB - Enabled, T = 25°C 194.0 -- 206.8 mV LB - Disabled, T = 25°C 194.4 -- 203.3 mV VHYS = 25 mV VIL = Vin - VHYS/2 VIH = Vin + VHYS/2 LB - Enabled, LB - Disabled, VHYS = 50 mV VIL = Vin - VHYS VIH = VHYS LB - Enabled, LB - Disabled, VHYS = 200 mV VIL = Vin - VHYS VIH = VHYS LB - Enabled, LB - Disabled, Rsin Series Input Resistance PROP Propagation Delay, Response Time for ACMP0 to ACMP3 Low Bandwidth - Enable, Gain = 1, Overdrive=10 mV Low to High, High to Low, Low Bandwidth - Disable, Gain = 1, Overdrive=10 mV Low to High, High to Low, Low Bandwidth - Enable, Gain = 1, Overdrive=100 mV Low to High, High to Low, Low Bandwidth - Disable, Gain = 1, Overdrive=100 mV Low to High, High to Low, Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit

5.9 Low Drop Out “LDO” Regulator Electrical Specifications

when the LDO MOSFET simply turns into a load switch passing VIN to VOUT. the LDO MOSFET simply turns into a load switch passing VIN to VOUT. Table 9. LDO Current Consumption for SLG46580 Table 10. LDO Current Consumption for SLG46582

Table 11. LDO Current Consumption for SLG46583 Table 12. LDO Regulator Thermal Limitations

1. Please note that Max Watt LDO multiplied by number of LDOs can easily exceed the Max Watt for the total IC package.
2. Lower Thermal shutdown levels may be achieved by using the temperature sensor and comparator.

Table 13. LDO HP MODE Electrical Specifications

100 Hz to 100 kHz -- 50 -- dB

1. Accuracy specifies all the effects of line regulation (VLINE), load regulation (VLOAD), and temperature coefficient (VTC),
2. X7R-type and X5R-type capacitors are recommended

Table 14. LDO LP MODE Electrical Specifications

1. X7R-type and X5R-type capacitors are recommended

Table 15. LDO Bypass Mode Electrical Specifications

SLG46580/82/83_DS_062 Page 28 of 193 SLG46580/82/83 Preliminary

6.0 Summary of Macrocell Function

6.1 I/O Pins

• Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
• Open Drain Output s (NMOS and PMOS)
• Push Pull Output s (1x and 2x)
• Analog I/O
• 10 k /100 k/1 Mpull-up/pull-down resistors
• IO0, IO4, IO6 and IO8 can be c onfigured as bidirectional I/O

6.2 Low Dropout Regulators

• Four Tri-Mode 150 mA LDO R egulators (for SLG46580):
• High Power Mode (HP Mode): 150 mA output with Quiescent Current at ~32 µA per LDO
• Low Power Mode (LP Mode): 100 µA output with Quiescent Current at ~2 µA per LDO
• Bypass Mode: Acts like a load switch
• Two Tri-Mode 300 mA LDO Regulators (for SLG46582):
• High Power Mode (HP Mode): 300 mA output with Quiescent Current at ~48 µA per LDO
• Low Power Mode (LP Mode): 200 µA output with Quiescent Current at ~3 µA per LDO
• Bypass Mode: Acts like a load switch
• One Tri-Mode 600 mA LDO R egulators (for SLG46583):
• High Power Mode (HP Mode): 600 mA output with Quiescent Current at ~80 µA
• Low Power Mode (LP Mode): 400 µA output with Quiescent Current at ~5 µA
• Bypass Mode: Acts like a load switch

6.3 Connection Matrix

• Digital matrix for circuit co nnections based on user design

6.4 Analog Comparators (4 total)

• Selectable hysteresis 0 m V / 25 mV / 50 mV / 200 mV
• Additionally ACMP2 and ACMP3 support 100 mV and 150 mV
• Wake and Sleep Control (Part of Combination Function Macrocell)

6.5 Voltage Reference

• Used for references on Analog Comparators

6.6 Combination Function Macrocells (15 total)

• Three Selectable DFF/Latch or 2-bit LUTs
• Six Selectable DFF/ Latch or 3-bit LUTs
• One Selectable Pipe Delay or Ripple Counter or 3-bit LUT
• Five Selectable 8-bit CNT/DLY or 3-bit LUT

6.7 Combinatorial Logic (1 total)

• One 4-bit LUT with two outputs

6.8 Asynchronous State Machine

• Eight States
• Flexible input logic from state transitions

SLG46580/82/83_DS_062 Page 29 of 193 SLG46580/82/83 Preliminary

6.9 Serial Communications

• I 2C Protocol compliant - Fast-Mode, and Fast-Mode Plus

6.10 Programmable Delay

• 125 ns/250 ns/375 ns/500 ns @ 3.3 V
• Includes Edge Detection function

6.11 Additional Logic Functions (2 total)

• Two Deglitch filter macrocells with Edge Detection function

6.12 Oscillators

• 25 kHz and 2 MHz s electable frequency
• First stage divider (4): OSC/1, OSC/2, OSC/4, and OSC/8
• Second stage divider for 25 kHz and 2 MHz (5): Output to Matrix: OSC/1, OSC/2, OSC/3, OSC/4, OSC/8, OSC/12, OSC/24, OSC/64
• 2 kHz Low Power Oscillator

6.13 Eight byte RAM + OTP User Memory

• RAM Memory space that is readable and writable via I2C
• User defined initial valu es transferred from OTP

6.14 Real Time Clock (RTC) Binary Counter

6.15 Power On Reset

SLG46580/82/83_DS_062 Page 30 of 193 SLG46580/82/83 Preliminary

7.0 I/O Pins

The SLG46580/82/83 has a total of 9 multi-function I/O pins which can function as either a user defined Input or Output, as well as serving as a special function (such as outputting the voltage reference), or serving as a signal for programming of the on-chip Non Volatile Memory (NVM). Normal Mode pin definitions are as follows:

• IO0: General Purpose I nput or Output with OE
• IO1 General Purpose Input or Outp ut or Analog Comparator 0(+)
• IO2: General Purpose Input or Output
• IO3: General Purpose Input or Output
• IO4: General Purpose Input or Ou tput with OE or Analog Comparator 1(+)
• IO5: General Purpose Input
• VDD: V DD Power supply
• SCL: I2C_SCL
• SDA: I2C_SDA
• IO6: General Purpose Input or Ou tput with OE or Analog Comparator (-)
• SLG46580:
• LDO0 VOUT: LDO0 Output or Analog Comparator 3(+)
• LDO0/1 VIN: LDO0 & LDO1 Input or Analog Comparator 0(+)
• LDO1 VOUT: LDO1 Output
• LDO2 VOUT: LDO2 Output or Analog Comparator 3(+)
• LDO2/3 VIN: LDO2 & LDO3 Input or Analog Comparator 1(+)
• LDO3 VOUT: LDO3 Output
• SLG46582:
• LDO0 VOUT: LDO0 Output or Analog Comparator 3(+)
• LDO0 VIN: LDO0 Input or Analog Comparator 0(+)
• LDO0 VOUT: LDO0 Output
• LDO1 VOUT: LDO1 Output or Analog Comparator 3(+)
• LDO1 VIN: LDO1 Input or Analog Comparator 1(+)
• LDO1 VOUT: LDO1 Output
• SLG46583:
• LDO VOUT: LDO Output or Analog Comparator 3(+)
• LDO VIN: LDO Input or Analog Comparator 0(+)
• LDO VOUT: LDO Output
• LDO VOUT: LDO Output or Analog Comparator 3(+)
• LDO VIN: LDO Input or Analog Comparator 1(+)
• LDO VOUT: LDO Output
• AGND: LDO Ground
• IO7: General Purpose Input or Ou tput or Analog Comparator 2(+)
• IO8: General Purpose Input or Ou tput with OE or Analog Comparator 3(+)
• GND: Ground Programming Mode pin definitions are as follows:
• IO5: V PP Programming voltage
• VDD: V DD Power supply
• SCL: Programming SCL
• SDA: Programming SDA
• IO7: Programming Mode Control
• GND: Ground

SLG46580/82/83_DS_062 Page 31 of 193 SLG46580/82/83 Preliminary Of the 9 user defined I/O pins on the SLG46580/82/83, all but o ne of the pins (IO5) can serve as both digital input and digita l output. IO5 can only serve as a digital input pin with RESET function, which has settings as follows:

• Level polarity:
• Non-inverted
• Inverted
• Reset mode:
• Level sensitive
• Edge triggered
• Edge detection:
• Rising edge
• Falling edge

7.1 Input Modes

Each I/O pin can be configured as a digital input pin with/with out Schmitt Trigger and low voltage input. IO1, IO4, IO7, and IO8 can also be configured to serve as analog inputs to the on-chip comparators. IO6 can also be configured as ACMP reference voltage input.

7.2 Output Modes

Pins IO0, IO1, IO2, IO3, IO4, IO6, IO7, and IO8 can all be configured as digital output pins.

7.3 Pull Up/Down Resistors

All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors are 10 k, 100 k and 1 M. In the case of IO5, the resistors are fixed to a pull-down configuration. In the case of all other I/O pins, the internal resistors can be configured as either pull-up or pull-downs.

7.4 I/O Register Settings

7.4.1 IO0 Register Settings

7.4.2 IO1Register Settings

Table 16. IO0 Register Settings Table 17. IO1 Register Settings

7.4.3 IO2 Register Settings

7.4.4 IO3 Register Settings

Table 18. IO2 Register Settings Table 19. IO3 Register Settings

7.4.5 IO4 Register Settings

7.4.6 IO5 Register Settings

7.4.7 SCL Register Settings

Table 20. IO4 Register Settings Table 21. IO5 Register Settings Table 22. SCL Register Settings

7.4.8 SDA Register Settings

7.4.9 IO6 Register Settings

Table 23. SDA Register Settings Table 24. IO6 Register Settings

7.4.10 IO7 Register Settings

7.4.11 IO8 Register Settings

Table 25. IO7 Register Settings Table 26. IO8 Register Settings

7.5 GPI Structure

7.5.1 GPI Structure (for IO5)

Figure 2. IO5 GPI Structure Diagram

7.6 Matrix OE IO Structure

7.6.1 Matrix OE IO Structure (for IO0, IO4, IO6, IO8)

Figure 3. Matrix OE IO Structure Diagram

7.6.2 Matrix OE IO Structure (for SCL and SDA)

Figure 4. Matrix OE IO Structure Diagram

7.7 IO Structure

7.7.1 IO Structure (for IO1, IO2, IO3, and IO7)

Figure 5. IO Structure Diagram

8.0 Connection Matrix

fully custom circuit will be created. output of a particular source macrocell, including I/O pins, LUTs, analog comparators, other digital resources and VDD and GND. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines. Package Top Marking System Definition. Figure 6. Connection Matrix Figure 7. Connection Matrix Example

8.1 Matrix Input Table

Table 27. Matrix Input Table

0 G N D 000000

1 IO0 Digital Input 0 0 0 0 0 1

2 IO1 Digital Input 0 0 0 0 1 0

3 IO2 Digital Input 0 0 0 0 1 1

4 IO3 Digital Input 0 0 0 1 0 0

5 IO4 Digital Input 0 0 0 1 0 1

6 LUT2_0 / DFF0 Output 0 0 0 1 1 0

7 LUT2_1 / DFF1 Output 0 0 0 1 1 1

8 LUT2_2 / DFF2 Output 0 0 1 0 0 0

9 LUT3_0 / DFF3 Output 0 0 1 0 0 1

10 LUT3_1 / DFF4 Output 0 0 1 0 1 0

11 LUT3_2 / DFF5 Output 0 0 1 0 1 1

12 LUT3_3 / DFF6 Output 0 0 1 1 0 0

13 LUT3_4 / DFF7 Output 0 0 1 1 0 1

14 LUT3_6 / CNT_DLY0(8bit) Output 0 0 1 1 1 0

15 LUT3_7 / CNT_DLY1(8bit) Output 0 0 1 1 1 1

16 LUT3_8 / CNT_DLY2(8bit) Output 0 1 0 0 0 0

17 LUT3_9 / CNT_DLY3(8bit) Output 0 1 0 0 0 1

18 LUT3_10 / CNT_DLY4(8bit) Output 0 1 0 0 1 0

19 LUT3_11 / Pipe Delay (1st stag e) Output / Ripple CNT Output0 0 10011

20 LUT3_5 / DFF8 Output 0 1 0 1 0 0

21 LUT4X2_0 Output0 0 1 0 1 0 1

22 LUT4X2_0 Output1 0 1 0 1 1 0

23 RTC CNT 1 second Output 0 1 0 1 1 1

24 RTC DCOMP Output 0 1 1 0 0 0

25 Pipe Delay Output0 / Ripple CNT Output1 0 1 1 0 0 1

26 Pipe Delay Output1 / Ripple CNT Output2 0 1 1 0 1 0

27 Internal OSC Post-Divided by 1/2/3/4/8/12/24/64 Output

28 Internal OSC Post-Divided by 1/2/3/4/8/12/24/64 Output

30 Filter0 / Edge Detect0 Output 0 1 1 1 1 0

31 Filter1 / Edge Detect1 Output 0 1 1 1 1 1

32 I2C_virtual_0 Input 1 0 0 0 0 0

33 I2C_virtual_1 Input 1 0 0 0 0 1

34 I2C_virtual_2 Input 1 0 0 0 1 0

35 I2C_virtual_3 Input 1 0 0 0 1 1

36 I2C_virtual_4 Input 1 0 0 1 0 0

37 I2C_virtual_5 Input 1 0 0 1 0 1

38 I2C_virtual_6 Input 1 0 0 1 1 0

39 I2C_virtual_7 Input 1 0 0 1 1 1

40 ASM-stateX-dout0 1 0 1 0 0 0

41 ASM-stateX-dout1 1 0 1 0 0 1

42 ASM-stateX-dout2 1 0 1 0 1 0

43 ASM-stateX-dout3 1 0 1 0 1 1

44 ASM-stateX-dout4 1 0 1 1 0 0

45 ASM-stateX-dout5 1 0 1 1 0 1

46 ASM-stateX-dout6 1 0 1 1 1 0

47 ASM-stateX-dout7 1 0 1 1 1 1

48 BG_OK Output 1 1 0 0 0 0

49 LDO0 nFault (SLG46580 and SLG46582)

50 LDO1 nFault (SLG465 80 and SLG46582) 1 1 0 0 1 0

51 LDO2 nFault (SLG46580) 1 1 0 0 1 1

52 LDO3 nFault (SLG46580) 1 1 0 1 0 0

53 IO5 Digital Input (GPI) 1 1 0 1 0 1

54 IO6 Digital Input 1 1 0 1 1 0

55 IO7 Digital Input 1 1 0 1 1 1

56 IO8 Digital Input 1 1 1 0 0 0

57 ACMP_0 Output 1 1 1 0 0 1

58 ACMP_1 Output 1 1 1 0 1 0

59 ACMP_2 Output 1 1 1 0 1 1

60 ACMP_3 Output 1 1 1 1 0 0

61 Programmable Delay with Edge Detector Output 1 1 1 1 0 1

8.2 Matrix Output Table

Table 28. Matrix Output Table

SLG46580/82/83_DS_062 Page 47 of 193 SLG46580/82/83 Preliminary

8.3 Connection Matrix Virtual Inputs

As mentioned previously, the Connection Matrix inputs come from the outputs of various digital macrocells on the device. Eight of the Connection Matrix inputs have the special characteristic that the state of these signal lines comes from a correspondin g data bit written as a register value via I 2C. This gives the user the ability to write data via the serial channel, and have this information translated into sig nals that can be driven into the Connection Matrix and from the Connection Matrix to the digita l inputs of other macrocells on the device. The I2C address for reading and writing these register values is at 0xF4 (0244). Eight Connection Matrix Virtual Inputs are dedicated to this virtual input function. An I2C write command to these register bits will set the signal values going into the Connection Matrix to the desired state. A read command to these register bits will read either the original data values coming from the NVM memory bits (that were loaded during the initial device startup), or the values from a previous write command (if that has happened). See table below for Connection Matrix Virtual Inputs.

8.4 Connection Matrix Virtual Outputs

The digital outputs of the various macrocells are routed to the Connection Matrix to enable interconnections to the inputs of other macrocells in the device. At the same time, it is possible to read the state of each of the macrocell outputs as a register value via I2C. This option, called Connection Matrix Virtual Outputs, allows the user to remotely read the values of each macrocell output. The I2C addresses for reading these register values are 0x70 (0112) t o 0x71 (0113). Write commands to these same register values will be ignored (with the exception of the Virtual Input register bits at 0xF4 (0244)). Matrix Input Number Matrix Input Signal Function Register Bit Addresses (d)

32 I2C_virtual_0 Input reg<1952>

33 I2C_virtual_1 Input reg<1953>

34 I2C_virtual_2 Input reg<1954>

35 I2C_virtual_3 Input reg<1955>

36 I2C_virtual_4 Input reg<1956>

37 I2C_virtual_5 Input reg<1957>

38 I2C_virtual_6 Input reg<1958>

39 I2C_virtual_7 Input reg<1959>

9.0 Combination Function Macrocells

• Three macrocells that can serve as either 2-bit LUTs or as D Flip Flops.
• Six macrocells that can serve as either 3-bit LUTs or as D Flip Flops with Set/Reset Input
• One macrocell that can serve as either 3-bit LUT or as Pipe Delay or as a Ripple Counter
• Five macrocells that can serve as either 3-bit LUTs or as 8-Bi t Counter / Delays Inputs/Outputs for the 15 combination function macrocells are configured from the connection matrix with specific logic functions being defined by the state of NVM bits. When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR). 9.1 2-Bit LUT or D Flip Flop Macrocells There are three macrocells that can serve as either 2-bit LUT s or as D Flip Flops. When used to implement LUT functions, the 2-bit LUTs each take in two input signals from the connection m atrix and produce a single output, which goes back into the connection matrix. When used to implement D Flip Flop function, the two input signals from the connection matrix go to the data (D) and clock (CLK) inputs for the Flip Flop, with the output going back to the connection matrix. The operation of the D Flip-Flop and Latch will follow the functional descriptions below:
• DFF: CLK is rising edge trigger ed, then Q = D; otherwise Q will not change
• Latch: if CLK = 0, then Q = D

Figure 8. 2-bit LUT0 or DFF0

created within each of the two 2-bit LUT logic cells. Table 32. 2-bit LUT Standard Digital Functions. Table 29. 2-bit LUT0 Truth Table. Table 30. 2-bit LUT1 Truth Table. Table 31. 2-bit LUT2 Truth Table.

Table 33. DFF0 Register Settings Table 34. DFF1 Register Settings Table 35. DFF2 Register Settings

9.2 Initial Polarity Operations

Figure 11. DFF Polarity Operations

Figure 12. 3-bit LUT0 or DFF3

Figure 17. 3-bit LUT5 or DFF8

Table 36. 3-bit LUT0 Truth Table. Table 37. 3-bit LUT1 Truth Table. Table 38. 3-bit LUT2 Truth Table. Table 39. 3-bit LUT3 Truth Table. Table 40. 3-bit LUT4 Truth Table. Table 41. 3-bit LUT5 Truth Table.

created within each of the six 3-bit LUT logic cells. Table 42. 3-bit LUT Standard Digital Functions. Table 43. DFF3 Register Settings Table 44. DFF4 Register Settings

Table 45. DFF5 Register Settings Table 46. DFF6 Register Settings Table 47. DFF7 Register Settings

Table 48. DFF8 Register Settings

9.4 Initial Polarity Operations

Figure 18. DFF Polarity Operations with nReset

Figure 19. DFF Polarity Operations with nSet

SLG46580/82/83_DS_062 Page 63 of 193 SLG46580/82/83 Preliminary 9.5 3-Bit LUT or Pipe Delay / Ripple Counter Macrocell There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay / Ripple Counter. When used to implement LUT functions, the 3-bit LUT takes in th ree input signals from the connection matrix and produces a single output, which goes back into the connection matrix. When used as a pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK) and Reset (RST). The pipe delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell input (IN). Both of the two outputs (OUT0 and OUT1) provide user selectable options for 1 – 16 stages of delay There are delay output points for each set of the OUT0 and OUT1 outputs to a 16-input MUX that is controlled by reg <1227:1224> for OUT0 and reg <1231:1228> for OUT1. The 16-input MUX is used to select the amount of delay. The overall time of the delay is based on the clock used in the SLG46580/82/83 design. Each DFF cell has a time delay of the inverse of the clock time (either external clock or the RC Oscillator within the SLG46580/82/83). The sum of the number of DFF cells used will be the total time delay of the Pipe Delay logic cell. OUT1 Output can be inverted (as selected by reg <1239>) In the Ripple Counter mode there are 3 options for setting, whi ch use 7 bits. There are 3 bits to set nSET value (SV) in range from 0 to 7. It is a value, which will be set into the Ripple Counter outputs when nSET input goes LOW. End value (EV) will use 3 bits for setting outputs code, which will be last code in the cycle. After reaching the EV, the Ripple Counter goes to the first code by the rising edge on CLK input. The Functionality mode option uses 1 bit. This setting defines how exactly Ripple Counter will operate. We can select one of the functionality modes by the register: RANGE or FULL. If the RANGE option is selected, the count starts from SV. If UP input is LOW the count goes down: SV->EV->EV-1…. SV+1->SV etc. (if SV is smaller than EV) or SV->SV-1….EV+1->EV->SV (if SV is bigger than EV). If UP input is HIGH, count starts from SV up to EV etc. In the FULL range configuration the Ripple Counter functions as follows. If UP input is LOW, the count starts from SV and goes down to 0. Then current counter value jumps to EV and goes down to 0 etc. If UP input is HIGH, count goes up starting from SV. Then current counter value jumps to 0 and counts up to EV etc. Please see Ripple counter functionality example in Figure 21. Every step is executed by the rising edge on CLK input.

Figure 20. 3-bit LUT11 / Pipe Delay / Ripple Counter

16 Flip-FlopsnRST

3 Flip-Flops

Figure 21. Example: Ripple Counter Functionality Table 49. 3-bit LUT11 Truth Table.

Table 50. Pipe Delay Register Settings

These macrocells can also operate in a one-shot mode, which will generate an output pulse of user-defined width. These macrocells can also operate in a frequency detection or edge detection mode. Figure 22. 3-bit LUT6 or CNT/DLY0

Table 51. 3-bit LUT6 Truth Table. Table 52. 3-bit LUT7 Truth Table. Table 53. 3-bit LUT8 Truth Table. Table 54. 3-bit LUT9 Truth Table. Table 55. 3-bit LUT10 Truth Table.

Table 56. CNT/DLY0 Register Settings Table 57. CNT/DLY1 Register Settings

Table 58. CNT/DLY2 Register Settings Table 59. CNT/DLY3 Register Settings

Table 60. CNT/DLY4 Register Settings

9.6.4 CNT/DLY Timing Diagrams

Figure 27. Delay Mode Timing Figure 28. Counter Mode Timing with Reset Signal offset = approx. 4-22 s at room temp. offset = approx. 4-22 s at room temp.

Figure 29. Counter Mode Timing with SET Signal

9.6.4.1 One-shot mode

is showing one-shot function for non-inverted output. The following diagram is showing one-shot function for non-inverted output. not restart while pulse is high. Figure 30. One-Shot Function Timing Diagram

9.6.4.2 Frequency Detection Mode

second rising edge has not come after the last rising edge in specified time. second falling edge has not come after the last falling edge in specified time. the length of the pulse. The output goes low if after the last rising/falling edge and specified time, the second edge has not come. The output goes low if the second edge has not come after the last rising/falling edge in specified time. Figure 31. Frequency Detection Mode Timing Diagram

9.6.4.3 Edge Detection Mode

The macrocell generates high level short pulse when detecting the respective edge. Figure 32. Edge Detection Mode Timing Diagram

9.6.4.4 Delayed Edge Detection Mode

if the corresponding edge was detected on the input. If the input signal is changed during the set delay time, the pulse will not be generated. See Figure 33. Figure 33. Delay Mode Timing Diagram

9.6.4.5 Delay Mode

shorter than the delay time. Figure 34. Delay Mode Timing Diagram

9.7 Wake and Sleep controller (WS)

on selected bit of 8-bit counter. Figure 35. Wake/Sleep controller Figure 36. Wake/Sleep Timing Diagram or From Connection Matrix Output<60> for 2 kHz Low Power Osc.

SLG46580/82/83_DS_062 Page 82 of 193 SLG46580/82/83 Preliminary To use any ACMP under WS controller the following settings must be done:

• ACMP Power Up Input f rom matrix = 1 (for each ACMP separately)
• CNT/DLY0 must be set to Wake an d Sleep Controller function (for all ACMPs)
• Register WS => enable (f or each ACMP separately)
• CNT/DLY0 set/reset inpu t = 0 (for all ACMPs) For the OSC, any oscillator with any pre-divider can be used. The user can select a period of time while the ACMPs are sleeping in a range of 1 - 255 clock cycles. Before they are sent to sleep their outputs are latched so the ACMPs remain their state (High or Low) while sleeping. When the WS signal is High, it takes a BG time (100 µS ~ 550 µS) to turn the ACMPs on. The wake time must be longer than BG/Analog power on time. Note: If 25 kHz / 2 MHz Oscillator is used for WS, the 2 kHz Low Power Osc must be set to Force Power On. The WS controller has the following settings:
• Wake and Sleep Output State (High/Low) If OSC is powered off (Power Down option is selected; power down input = 1) and Wake and Sleep Output State = High, the ACMP is continuously on If OSC is powered off (Power Down option is selected; power down input = 1) and Wake and Sleep Output State = Low, the ACMP is continuously off Both cases WS function is turned off
• Counter Data (Range: 1 - 255) User can select wake and sleep ratio of the ACMP; counter data = sleep time, one clock = wake time
• Q mode - defines the state of WS counter data when Set/Reset signal appears Reset - when active signal appears, the WS counter will reset to zero and High level signal on its output will turn the ACMPs on. When Reset signal goes out, the WS counter will go Low and turn the ACMPs off until the counter counts up to the end Set - when active signal appears, the WS counter will stop and Low level signal on its output will turn the ACMPs off. When Set signal goes out, the WS counter will go on counting and High level signal will turn the ACMPs on while counter is counting up to the end
• Edge Select defines the edge for Q mode High level Set/Reset - switches mode Set/Reset when level is High Note: Q mode operates only in case of "High Level Set/Reset"

10.0 Combinatorial Logic

LUTs. For more details, please see Section 9.0 Combination Function Macrocells. devices (AND, NAND, OR, NOR, XOR, XNOR). Figure 37. 4-bit LUT0 with two outputs Table 61. 4-bit LUT0 Truth Table

logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created within the 4-bit LUT logic cell. Table 62. 4-bit LUT Standard Digital Functions

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11.0 Analog Comparators (ACMP)

There are four Analog Comparator (ACMP) macrocells in the SLG46 580/82/83. In order for the ACMP cells to be used in a GreenPAK design, the power up signals (ACMP0_pd, ACMP1_pd, ACMP2_pd and ACMP3_pd) need to be active. By connecting to signals coming from the Connection Matrix, it is possible to have each ACMP be on continuously, off continuously, or switched on periodically based on a digital signal coming from the Connection Matrix. When ACMP is powered down, output is LOW. Each of the ACMP cells has a positive input signal that can be provided by a variety of exter nal sources, and can also have a selectable gain stage before connection to the analog comparato r. Each of the ACMP cells has a negative input signal that is either created from an internal VREF or provided by way of the external sources. PWR UP = 1 => ACMP is powered up. PWR UP = 0 => ACMP is powered down. During power-up, the ACMP output will remain low, and then become valid 2 ms (max) after ACMP power up signal goes HIGH. If VDD is greater than 2.7 V, then power up time will decrease. Vref accuracy is optimized near 1000 mV selection. Input bias current < 1 nA (typ). The Gain divider is unbuffered and consists of 1 M resistors. IN- voltage range: 0 - 1.2 V. Can use Vref selection VDD/4 and VDD/3 to maintain this input range. To ensure proper chip startup operation, it is recommended to enable the ACMPs with the POR signal, and not the VDD signal. Each of the ACMP cells has a selection for the bandwidth of the input signal, which can be used to save power when low bandwidth signals are input into the analog comparator. Low bandwidth: For VDD 2.3 V or less, this option will connect a low pass fil ter with 180 kHz upper frequency. And if input frequency > 200 kHz, the output will retain its previous value. Buffer can be used only for VDD > 2.7 V. Enabling the Analog buffer will influence the ACMP response time. Note that power supply control options have influence on Analog macrocells operation. Note: Any ACMP powered ON enables the BandGap circuit as well, and an analog voltage will appear on Vref (even when Force BandGap is disabled). Each cell also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV or 200 mV. ACMP2 and ACMP3 has additional hysteresis options for 100 mV and 150 mV. Note: the 25 mV hysteresis option works with either internal or external Vref, while all other options work with internal Vref only. The 50 mV, 100 mV, 150 mV, and 200 mV hysteresis options are one way hysteresis. This means that actual thresholds will be Vref (high threshold) and Vref - hysteresis (low threshold). The ACMP output will retain its output value if the input voltage is within the threshold window (between Vref and Vref - hysteresis). The 25 mV hysteresis option threshold levels will be Vref + hysteresis/2 (high threshold) and Vref - hysteresis /2 (low threshold). Hysteresis: Input signal hysteresis options are disable, 25 mV, 50 mV, 200 mV (and additionally 100 mV and 150 mV for ACMP2 and ACMP3. ACMP0 IN+ options are IO1, buffered IO1, VDD, LDO0/1 VIN for SLG46580, LDO0 VIN for SLG46582, LDO VIN for SLG46583 ACMP1 IN+ options are IO4, buffer ed IO4, ACMP0 IN+, LDO2/3 VIN for SLG46580, LDO VIN1 for SLG46582, LDO VIN 0 for SLG46583 ACMP2 IN+ options are IO7, ACMP0 IN+, Temp. Sensor ACMP3 IN+ options are IO8, ACMP2 IN+, LDO0 VOUT and LDO2 VOUT f or SLG46580, LDO VOT0 and LDO1 VOUT for SLG46582, LDO VOUT for SLG46583

11.1 ACMP0 Block Diagram

Figure 38. ACMP0 Block Diagram Note*: See sections 2.2 to 2.4.

11.2 ACMP0 Register Settings

Table 63. ACMP0 Register Settings

11.3 ACMP1 Block Diagram

Figure 39. ACMP1 Block Diagram Note*: See sections 2.2 to 2.4.

11.4 ACMP1 Register Settings

Table 64. ACMP1 Register Settings

11.5 ACMP2 Block Diagram

Figure 40. ACMP2 Block Diagram

11.6 ACMP2 Register Settings

Table 65. ACMP2 Register Settings

11.7 ACMP3 Block Diagram

Figure 41. ACMP3 Block Diagram Note*: See sections 2.2 to 2.4.

11.8 ACMP3 Register Settings

Table 66. ACMP3 Register Settings

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12.0 Pipe Delay (PD)

The SLG46580/82/83 has a pipe delay logic cell that is shared with the 3-bit LUT11 in one of the Combination Function macrocells. The user can select one of these functions to use in a design, but not both. Ple ase see Section 9.5 3-Bit LUT or Pipe Delay / Ripple Counter Macrocell for the description of this Combination Function macrocell.

13.0 Programmable Delay / Edge Detector

the delay period. See the timing diagrams below for further information. Note: The input signal must be longer than the delay, otherwise it will be filtered out.

13.1 Programmable Delay Timing Diagram - Edge Detector Output

Please refer to Table 3. Programmable Delay Expected Delays and Pulse Widths (typical). Figure 42. Programmable Delay Figure 43. Edge Detector Output

13.2 Programmable Delay Register Settings

Table 67. Programmable Delay Register Settings

14.0 Additional Logic Functions

The SLG46580/82/83 has two additional logic functions that are connected directly to the Connection Matrix inputs and outputs. There are two deglitch filters, each with edge detector functions.

14.1 Deglitch Filter / Edge Detector

14.2 Deglitch Filter Register Settings

Figure 44. Deglitch Filter / Edge Detector Table 68. Deglitch Filter Register Settings

15.0 RTC Binary Counter

consists of three components and can be programmed serially through an I2C serial interface. clock source, in which case the output will be a pulse at 1 second intervals, with high time of ~30.5 µS. Figure 45. RTC Counter Macrocell

15.1 RTC Binary Counter Shadow Buffer

(from the shadow buffer to RTC counter).

• Reg <990> defines the source of the trigger signal for the cop y to shadow buffer, either from the Connection Matrix or from the designated I2C address read. The trigger source can be changed though an I2C write command to change this bit setting.
• Reg <989> defines the direction of whether RTC Counter data will be copied to 48-bit shadow buffer or the 48-bit shadow buffer data will be copied to the RTC Counter. The direction can be changed though an I2C write command to change this bit setting.

15.1.1 RTC Binary Counter Shadow Buffer Operating Modes

the signal that will latch the data. Figure 46. RTC Counter Shadow Buffer bits Table 69. Shadow Buffer Register Settings

16.0 Voltage Reference (VREF)

16.1 Voltage Reference Overview

supplied voltage references from IO6. See table below for the available selections for each analog comparator.

16.2 VREF Selection Table

Note: the ACMP external reference voltage (IN-) is limited by 1.2 V for full power supply range. Table 70. VREF Selection Table.

11011 IO6: EXT_VREF /2 IO6: EXT_VREF /2 IO6: EXT_VREF /2 IO6: EXT_V REF /2

11010 IO6: EXT_VREF IO6: EXT_VRE F IO6: EXT_VREF IO6: EXT_VREF

11001 VDD: ACMP0- / 4 VDD: ACMP1- / 4 VDD: ACMP2- / 4 VDD: ACMP3- / 4

11000 VDD: ACMP0- / 3 VDD: ACMP1- / 3 VDD: ACMP2- / 3 VDD: ACMP3- / 3

17.0 Analog Temperature Sensor

Centigrade temperature. This feature was designed with a range from 50°C to 150°C as a tool to protect the chip from overheating. TS's analog output voltage decreases. output can lower the chip's junction temperature by disabling the LDOs. note that there will be a chip to chip variation of about ±2°C. To enable the TS, set the TS enable register high in the "Temp Sensor" macrocell or the "ACMP2" macrocell's IN+ source settings.

Figure 47. Analog Temperature Sensor Structure Diagram

18.0 Clocking

• Low Power Oscillator (2 kHz)
• Configurable Oscillator (25 kHz or 2 MHz) There are two divider stages that give the user flexibility for introducing clock signals to connection matrix, as well as various other Macrocells. The predivider (first stage) for Configurable Oscillator allows the selection of /1, /2, /4 or /8 to divide down frequency from the fundamental. The second stage divider has an input of frequency from the predivider, and outputs one of eight different frequencies divided by /1, /2, /3, /4, /8, /12, /24 or /64 on Connection Matrix Input lines <27> and <28>. The second stage divider is available to the configurable OSC (25 kHz or 2 MHz) only while the Low Power OSC is connected to Connection Matrix Input <29> directly after the pre-divider /1, /2, /4 or /16 for LP OSC. The Matrix Power Down/Force On function allows switching off or force on the oscillator using an external pin. The Matrix Power Down/Force On (Connection Matrix Output <59> and <60) signal ha s the highest priority. The OSC operates according to the following table: The SLG46580/82/83 has a 25 kHz / 2 MHz OSC Fast Start-up optio n up function controlled by reg <1293> (1: Enabled; 0: Disabled). It allows the OSC to have faster start up time, less than one OSC cycle when this option is enabled). Note: The quiescent current consumption will increase when the OSC Fast Start-up option is enabled.

Table 72. Oscillator Operation Mode Configuration Settings

001 O N

010 O F F

011 O F F

101 O N

110 O N

111 O N

Note *: the OSC will run only when any macrocell that uses OSC is powered on.

18.1 Low Power OSC(2 kHz)

Figure 48. Low Power Oscillator Block Diagram

18.2 Configurable OSC (25 kHz / 2 MHz)

Figure 49. Configurable OSC Block Diagram

18.3 Oscillator Power On delay

Note 1: OSC power mode: "Auto Power On". Note 2: 'OSC enable' signal appears when any macrocell that uses OSC is powered on. Figure 50. Oscillator Startup Diagram Figure 51. RC Oscillator Maximum Power On Delay vs. VDD at room temperature, OSC0 = 2 MHz

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19.0 Power On Reset (POR)

The SLG46580/82/83 has a power-on reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first ramping to the device, and also while the VDD is falling during power-down. To accomplish this goal, the POR drives a defined sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of the I/O pins.

19.1 General Operation

The SLG46580/82/83 is guaranteed to be powered down and non-operational when the VDD voltage (voltage on VDD pin) is less than Power Off Threshold (see in Electrical Characteristics table), but not less than -0.6 V. Another essential condition for the chip to be powered down is that no voltage higher (see Note 1) than the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3 V, applying a voltage higher than 0.3 V to any other PIN is incorrect and can lead to incorrect or unexpected device behavior. Note 1: There is a 0.6V margin due to forward drop voltage of the ESD protection diodes. To start the POR sequence in the SLG46580/82/83, the voltage ap plied on the VDD should be higher than the Power_ON means that the VDD voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power_ON threshold. After the POR sequence has started, the SLG46580/82/83 will have a typical period of time to go through all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after the POR sequence is complete. Note 2: The Power_ON threshold is defined in Electrical Characteristics table. Note 3: LDOs begin to operate when VDD ≥ 2.3 V. To power down the chip the VDD voltage should be lower than the operational and to guarantee that chip is powered down it should be less than Power Off Threshold. All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step in the POR sequence releases the I/O structures from the high impedance state, at which time the device is operational. The pin configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.

19.2 POR Sequence

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 54. impedance to active at this point. LDOs begin to operate in 500 s after PINs become active. environmental factors, such as: slew rate, VDD value, temperature and even will vary from chip to chip (process influence). Figure 54. POR sequence

19.3 Macrocells Output States During POR Sequence

states during the POR sequence (Figure 55 describes the output signals states). matrix signal switches from LOW to HIGH. The last are output PINs that become active and determined by the input signals. Figure 55. Internal Macrocell States during POR sequence

19.3.1 Initialization

1. Input PINs, ACMP , pull up/down;
2. DFFs, Delays/Counters, Pipe Delay;
3. Output PIN corresponds to the internal logic

Note 1: LDOs begin to operate above 2.3 V. the input PIN.There is no effect from input pin when input voltage is applied at the same time as VDD.

19.3.2 Power Down

note that during a slow rampdown, outputs can possibly switch state during this time.

19.4 External reset

The SLG46580/82/83 has an optional External Reset function on IO5. It allows to reset the chip while powered on. 1 -enabled. Unlike POR, External Reset affects only GPI, LUTs, D L Y , RC OSC, DFFs, Latches, Pipe Delay , Matrix and GPO. While NVM remains its previous state, see Figure 57 to Figure 59. Figure 56. Power Down

Figure 57. External reset sequence (High active).

Figure 58. External reset sequence (Rising edge detect).

Figure 59. External reset sequence (Falling edge detect). Table 73. External reset Register Settings

20.0 Asynchronous State Machine (ASM) Macrocell

20.1 ASM Macrocell Overview

will cause transitions from one state to another state, as shown in Figure 60. which will drive an immediate state transition to the user-defined Initial / Reset state when active, shown in red, in the Figure 60. signals are properly processed, and state transitions are deterministic. The GPAK Designer development tools support user designs for th e ASM macrocell at both the physical level and logic level. a physical mapping of the input and outputs required for the desired functionality. Figure 60. Asynchronous State Machine States and Transitions Diagram

Figure 61. Asynchronous State Machine

20.2 ASM Inputs

selectable for driving general state transitions, and 1 is for driving a state transition to an Initial / Reset state. user selected transition from one state to another, shown in Figure 63. user can select going into a particular state to be 3, shown in Figure 64. have transitions going from a state to all other states, shown in Figure 65. state within the ASM Editor inside GPAK Designer is the initial state. Figure 62. Asynchronous State Machine Inputs

20.3 ASM Outputs

8 bits per state. The values loaded in each of the 8 bits define the signal level on each of the 8 ASM macrocell outputs. Figure 66. Connection Matrix Output RAM

Note: Each state output is user configurable. Table 74. ASM Editor - Connection Matrix Output RAM

20.4 Basic ASM Timing

longest state transition (input on matrix output and output on matrix input).

1. No clock source is needed, it reacts only to input signals
2. The input signals do not have to be synchronized to each other, the macrocell will react to the earliest valid signal for state
3. This macrocell does not have traditional set-up and hold time specifications which are related to incoming clock, as this

macrocell has no clock source.

1. The macrocell only consumes power while in state transition.

20.6 ASM Power Considerations

only during state transitions. See Section 5.5 IDD Estimator to find average current during state transitions. Figure 67. State Transition Figure 68. State Transition Timing Figure 69. State Transition

20.8 ASM Special Case Timing Considerations

20.8.1 State Transition Pulse Input Timing

that does meet minimum pulse width. Figure 70. State Transition Timing and Power Consumption Figure 71. State Transition Figure 72. State Transition Pulse Input Timing

20.8.2 State Transition Competing Input Timing

There will be situations where two input signals can be valid inputs that will drive two different state transitions from a given state. satisfies the pulse width criteria described in the paragraph above, as shown in Figure 75. Figure 73. State Transition - Competing Inputs Figure 74. State Transition Timing - Competing Inputs Indeterminate Figure 75. State Transition Timing - Competing Inputs Determinable

20.8.3 ASM State Transition Sequential Timing

example of this sequential behavior is shown in Figure 76 and the associated timing is shown in Figure 77.

20.8.4 State Transition Closed Cycling

cycling of this nature. Figure 79 shows the associated timing for closed cycling. Figure 76. State Transition - Sequential Figure 77. State Transition - Sequential Timing Figure 78. State Transition - Closed Cycling Figure 79. State Transition - Closed Cycling Timing

20.8.5 ASM State Transition Using Edge Detector Option

transition as shown in Figure 80 and Figure 81. Figure 80. State Transition - Rising Edge Transition Figure 81. State Transition - Rising Edge Transition Timing

21.0 I2C Serial Communications Macrocell

21.1 I2C Serial Communications Macrocell Overview

signals in the manner most appropriate for the user’s application. the device, giving an I2C bus Master the capability to remotely read the current value of any macrocell. 21.4.7.1 Register Read/Write Protection for more details on I2C read/write memory protection. Note: GreenPAK I2C is fully compatible with standard I2C protocol.

21.2 I2C Serial Communications Device Addressing

by an Acknowledge bit (ACK), which is sent by this device to indicate successful communication of the Control Byte data. be “0” for all commands to the SLG46580/82/83. Address. Figure 82 shows this basic command structure. Figure 82. Basic Command Structure

21.3 I2C Serial General Timing

found in the AC Characteristics section.

21.4 I2C Serial Communications Commands

21.4.1 Byte Write Command

the data will take place at the time that the SLG46580/82/83 generates the Acknowledge bit. Figure 83. I2C General Timing Characteristics Figure 84. Byte Write Command, R/W = 0

21.4.2 Sequential Write Command

that the SLG46580/82/83 generates the Acknowledge bit.

21.4.3 Current Address Read Command

bits for the requested byte. The Master will not issue an Acknowledge bit, and follow immediately with a Stop condition. Figure 85. Sequential Write Command, R/W = 0 Figure 86. Current Address Read Command, R/W = 1

21.4.4 Random Read Command

R/W bit set to “1”, after which the SLG46580/82/83 issues an Acknowledge bit, followed by the requested eight data bits.

21.4.5 Sequential Read Command

a random read. The Master can continue reading sequential bytes of data, and will terminate the command with a Stop condition. Figure 87. Random Read Command Figure 88. Sequential Read Command

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21.4.6 I2C Serial Command Address Space

In the read and write command address structure, there are a to tal of 11 bits of addressing, each pointing to a unique byte of information, resulting in a total address space of 2K bytes. Of this 2K byte address space, the valid addresses accessible to the I2C Macrocell on the SLG46580/82/83 are in the range from 0 (0x00) to 255 (0xFF). The MSB address bits (A10, A9 and A8) will be “0” for all commands to the SLG46580/82/83.

21.4.7 I2C Serial Command Register Map

21.4.7.1 Register Read/Write Protection

There are several read/write protect modes for the design sequence from being corrupted or copied. See Table 75 for details. Table 75. Read/Write Protection Options

SLG46580/82/83_DS_062 Page 133 of 193 SLG46580/82/83 Preliminary It is possible to read some data from macrocells, such as count er current value, ASM current s tate, connection matrix, and connection matrix virtual inputs. The I2C write does not have any impact on data in case data comes from macrocell output, except Connection Matrix Virtual Inputs. The silicon identification service bits allow identifying silicon family, its revision, etc. Note 1: If reg<1663> = 1, all outputs are latched while inputs and internal macrocells retain their status during I2C write. Note 2: Any write commands that come to the device via I 2C that are not blocked, based on the protection bits, will change the contents of the RAM register bits that mirror the NVM bits. These write commands will not change the NVM bits themselves, and a POR event will restore the register bits to original programmed contents of the NVM. See Section 25.0 Appendix A - SLG46580/82/83 Register Definition Package Top Marking System Definition for detailed infor- mation on all registers

21.4.7.2 I2C Serial Reset Command

If I2C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including configuration of all macrocells, and all connections provided by the Connection Matrix. This is implemented by setting reg<1662> I2C reset bit to “1”, which causes the device to re-enable the Power On Reset (POR) sequence, including the reload of all register data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has taken place, the contents of reg<1662> will be set to “0” automatically. The timing diagr am shown below illustrates the s equence of events for this rese t function. R/W Allow Read and Write Data W Allow Write Data Only R Allow Read Data Only - The Data is protected for Read and Write

Figure 89. Reset Command Timing

21.4.7.3 Reading Counter Data via I2C

additional functionality are 8-bit counters CNT2 and CNT4.

21.4.7.4 User RAM and OTP Memory Array

and the highest order byte in this array is located at I2C address 0xDF. Table 76. RAM Array Table

22.0 SLG46580 Low Dropout Regulators

22.1 LDO Regulator Description

passing the voltage applied to VIN directly to VOUT. share the same VIN called LDO2/3 VIN. Figure 90. LDO0 Regulator Block Diagram

Figure 91. LDO1 Regulator Block Diagram

Figure 92. LDO2 Regulator Block Diagram

22.1.1 Voltage Selection

Each LDO has access to 32 voltage levels derived from a bandgap voltage reference. level through the I2C by writing the corresponding LDO output voltage selection number according to Table 77. Figure 93. LDO3 Regulator Block Diagram Table 77. LDO Output Voltage Selection

22.1.2 LDO HP Mode Operation

to enable analog circuitry before the LDO output starts to rise with the desired ramping slope selected through the register bits.

22.1.3 LDO LP Mode Operation

enabled in the SLG46580 chip.

22.1.4 Power Switch Mode Operation

quiescent current consumption is ~1 A in power switch mode. Note1: The combination of VIN, VDD and VOUT must satisfy the rule: VDD ≥ VIN ≥ VOUT + 0.3 V. Note2: VIN and VDD should not exceed 5.5 V. Table 77. LDO Output Voltage Selection (continued)

following register bits: reg <1452> for LDO0, reg <1448> for LDO1, reg <1460> for LDO2, and reg <1456> for LDO3. <100> for LDO0, LDO1, LDO2 and LDO3 respectively.

22.2 Over-Current Limit and Short-Circuit Detection

Detection, if output voltage drops below 0.5 V with the current limited by 20 mA). connection matrix input when LDO when the over-current limit is detected.

22.3 LDO Thermal Considerations

should be properly selected for the higher of the desired LDO output voltages. for ACMP2. Other temperature shut off levels may be achieved by incorporating the temperature sensor into ACMP3’s input.

22.4 Soft Start Function (SS)

the bit settings and slew rate selection options for each LDO. Table 78. LDO0 Ramp Rate Selection Table Table 79. LDO1 Ramp Rate Selection Table Table 80. LDO2 Ramp Rate Selection Table

22.5 ACMPs: Under Voltage Lockout capability, Power Good

reg <1585>. for LDO0 and LDO1, and UVLO_1 by reg <1584> for LDO2 and LDO3. use UVLO_1 for LDO2 and LDO3. A lockout level below 2.3 V is not useful as the lowest acceptable power supply voltage is 2.3 V. ACMP3 has a selectable input from the output of LDO0 or 2 for the purpose of a power good. The ACMPs connection to VDD may be reused for the purpose stated above.

22.6 Regulator Stability Considerations

22.7 LDO Regulator Cold Start up

SLG46580 is ~2 ms typical, and 3 ms max. start and the ~2-3 ms when SLG46580/82/83 takes control.

22.8 LDO Regulator Hot Start up

22.9 Discharge Resistors

on a VOUT capacitor the discharge resistor should not be selected. The discharge resistor is set by reg <1455> for LDO0, reg <1451> for LDO1, reg <1463> for LDO2, and reg <1459> for LDO3. Table 81. LDO3 Ramp Rate Selection Table Table 80. LDO2 Ramp Rate Selection Table (continued)

22.10 SLG46580 LDO Typical Application Circuit

Figure 94. SLG46580 LDO Typical Application Circuit Note: All internal connections shown inside the SLG46580 are hardwired connections that cannot be changed. Note*: Keep decoupling capacitors close to the SLG46580. Note**: Keep output capacitors close to the SLG46580. Long distances negatively impact LDO stability.

23.0 SLG46582 Low Dropout Regulators

23.1 LDO Regulator Description

passing the voltage applied to VIN directly to VOUT. The LDO regulators each have a VIN called LDO0 VIN for LDO0 and LDO1 VIN for LDO1. Figure 95. LDO0 Regulator Block Diagram Note*: Both LDO0 VOUT (Pins 11 and 13) must be connected together externally.

23.1.1 Voltage Selection

Each LDO has access to 32 voltage levels derived from a bandgap voltage reference. level through the I2C by writing the corresponding LDO output voltage selection number according to Table 88. Figure 96. LDO1 Regulator Block Diagram Table 82. LDO Output Voltage Selection

23.1.2 LDO HP Mode Operation

HP Mode is the standard active LDO mode with a 300 mA per LDO output loading capability. output starts to rise with the desired ramping slope selected through the register bits. Note1: The combination of VIN, VDD and VOUT must satisfy the rule: VDD ≥ VIN ≥ VOUT + 0.3 V. Note2: VIN and VDD should not exceed 5.5 V. Table 82. LDO Output Voltage Selection (continued)

23.1.3 LDO LP Mode Operation

enabled in the SLG46582 chip.

23.1.4 Power Switch Mode Operation

quiescent current consumption is ~2 A in power switch mode. following register bits: reg <1452> for LDO0 and reg <1460> for LDO1.

23.2 Over-Current Limit and Short-Circuit Detection

Detection, if output voltage drops below 0.5 V with the current limited by 20 mA). connection matrix input when LDO when the over-current limit is detected.

23.3 LDO Thermal Considerations

should be properly selected for the higher of the desired LDO output voltages. for ACMP2. Other temperature shut off levels may be achieved by incorporating the temperature sensor into ACMP3’s input.

23.4 Soft Start Function

the bit settings and slew rate selection options for each LDO. Table 83. LDO0 Ramp Rate Selection Table Table 84. LDO1 Ramp Rate Selection Table

23.5 ACMPs: Under Voltage Lockout capability, Power Good

control the LDO or through the Connection Matrix. The UVLO_0 hardware connection to the LDO can be enabled by reg <1585>. for LDO0, and UVLO_1 by reg <1584> for LDO1. A lockout level below 2.3 V is not useful as the lowest acceptable power supply voltage is 2.3 V. ACMP3 has a selectable input from the output of LDO0 for the purpose of a power good. The ACMPs connection to VDD may be reused for the purpose stated above.

23.6 Regulator Stability Considerations

23.7 LDO Regulator Cold Start up

SLG46582 is ~2 ms typical, and 3 ms max. start and the ~2-3 ms when SLG46582 takes control.

23.8 LDO Regulator Hot Start up

23.9 Discharge Resistors

on a VOUT capacitor the discharge resistor should not be selected. The discharge resistor is set by reg <1455> for LDO0 and reg <1463> for LDO1. Table 84. LDO1 Ramp Rate Selection Table (continued)

23.10 SLG46582 LDO Typical Application Circuit

Figure 97. SLG46582 LDO Typical Application Circuit Note: All internal connections shown inside the SLG46582 are hardwired connections that cannot be changed. Note*: Keep decoupling capacitors close to the SLG46582. Note**: Keep output capacitors close to the SLG46582. Long distances negatively impact LDO stability.

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24.0 SLG46583 Low Dropout Regulator

24.1 LDO Regulator Description

The SLG46583 comes with a single low dropout regulators rated a t 600 mA. The LDO regulator has 3 modes which are: HP MODE is the standard active mode supporting full 600 mA output; LP MODE is a low power mode with maximum 400 µA and finally BYPASS MODE in which th e LDO regulator ceases to reg ulate and the Regulator MOSFET is turned on as a power switch, passing the voltage applied to VIN directly to VOUT.

Figure 98. LDO Regulator Block Diagram Note*: Both LDO VIN (Pins 12 and 15) must be connected together externally. All four LDO VOUT (Pins 11, 13, 14 and 16) must be connected together externally.

24.1.1 Voltage Selection

sponding LDO output voltage selection number according to Table 91. Table 85. LDO Output Voltage Selection Note1: The combination of VIN, VDD and VOUT must satisfy the rule: VDD ≥ VIN ≥ VOUT + 0.3 V. Note2: VIN and VDD should not exceed 5.5 V.

24.1.2 LDO HP Mode Operation

HP Mode is the standard active LDO mode with a 600 mA per LDO output loading capability. ramping slope selected through the register bits.

24.1.3 LDO LP Mode Operation

~6A per LDO (without load). LP Mode can be enabled through Connection Matrix Output <92> in the SLG46583 chip.

24.1.4 Power Switch Mode Operation

quiescent current consumption is ~4 A in power switch mode. The Power Switch Mode can be selected by applying a high-level signal to the Connection Matrix Output <97>.

24.2 Over-Current Limit and Short-Circuit Detection

Detection, if output voltage drops below 0.5 V with the current limited by 20 mA). connection matrix input when LDO when the over-current limit is detected.

24.3 LDO Thermal Considerations

resistor should be properly selected for the higher of the desired LDO output voltages. for ACMP2. Other temperature shut off levels may be achieved by incorporating the temperature sensor into ACMP3’s input.

24.4 Soft Start Function

the bit settings and slew rate selection options for the LDO. Table 86. LDO0 Ramp Rate Selection Table

24.5 ACMPs: Under Voltage Lockout capability, Power Good

control the LDO or through the Connection Matrix. The UVLO_0 hardware connection to the LDO can be enabled by reg <1585>. for LDO0, and UVLO_1 by reg <1584> for LDO1. Note: ACMP0 needs to be properly configured to use UVLO_0 for the LDO. A lockout level below 2.3 V is not useful as the lowest acceptable power supply voltage is 2.3 V. ACMP3 has a selectable input from the output of LDO for the purpose of a power good. The ACMPs connection to VDD may be reused for the purpose stated above.

24.6 Regulator Stability Considerations

24.7 LDO Regulator Cold Start up

SLG46583 is ~2 ms typical, and 3 ms max. start and the ~2-3 ms when SLG46583 takes control.

24.8 LDO Regulator Hot Start up

24.9 Discharge Resistors

on a VOUT capacitor the discharge resistor should not be selected. The discharge resistor is set by reg <1455>. Table 86. LDO0 Ramp Rate Selection Table (continued)

24.10 SLG46583 LDO Typical Application Circuit

Figure 99. SLG46583 LDO Typical Application Circuit Note: All internal connections shown inside the SLG46583 are hardwired connections that cannot be changed. Note*: Keep decoupling capacitors close to the SLG46583. Note**: Keep output capacitors close to the SLG46583. Long distances negatively impact LDO stability.

SLG46580/82/83_DS_062 Page 156 of 193 SLG46580/82/83 Preliminary

25.0 Appendix A - SLG46580/82/83 Register Definition Package Top Marking System Definition

Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write Note: For reg<0> to reg<1495>, I2C Read is valid (assuming reg <1832> = 0), I2C Write is valid (assuming reg <1871> = 0) Matrix Output reg<5:0> Matrix OUT: ASM-state0-EN0 Valid Valid reg<7:6> Reserved Valid Valid reg<13:8> Matrix OUT: ASM-state0-EN1 Valid Valid reg<15:14> Reserved Valid Valid reg<21:16> Matrix OUT: ASM-state0-EN2 Valid Valid reg<23:22> Reserved Valid Valid reg<29:24> Matrix OUT: ASM-state1-EN0 Valid Valid reg<31:30> Reserved Valid Valid reg<37:32> Matrix OUT: ASM-state1-EN1 Valid Valid reg<39:38> Reserved Valid Valid reg<45:40> Matrix OUT: ASM-state1-EN2 Valid Valid reg<47:46> Reserved Valid Valid reg<53:48> Matrix OUT: ASM-state2-EN0 Valid Valid reg<55:54> Reserved Valid Valid reg<61:56> Matrix OUT: ASM-state2-EN1 Valid Valid reg<63:62> Reserved Valid Valid reg<69:64> Matrix OUT: ASM-state2-EN2 Valid Valid reg<71:70> Reserved Valid Valid reg<77:72> Matrix OUT: ASM-state3-EN0 Valid Valid reg<79:78> Reserved Valid Valid reg<85:80> Matrix OUT: ASM-state3-EN1 Valid Valid reg<87:86> Reserved Valid Valid reg<93:88> Matrix OUT: ASM-state3-EN2 Valid Valid reg<95:94> Reserved Valid Valid reg<101:96> Matrix OUT: ASM-state4-EN0 Valid Valid reg<103:102> Reserved Valid Valid reg<109:104> Matrix OUT: ASM-state4-EN1 Valid Valid reg<111:110> Reserved Valid Valid reg<117:112> Matrix OUT: ASM-state4-EN2 Valid Valid reg<119:118> Reserved Valid Valid reg<125:120> Matrix OUT: ASM-state5-EN0 Valid Valid reg<127:126> Reserved Valid Valid reg<133:128> Matrix OUT: ASM-state5-EN1 Valid Valid reg<135:134> Reserved Valid Valid reg<141:136> Matrix OUT: ASM-state5-EN2 Valid Valid reg<143:142> Reserved Valid Valid reg<149:144> Matrix OUT: ASM-state6-EN0 Valid Valid reg<151:150> Reserved Valid Valid reg<157:152> Matrix OUT: ASM-state6-EN1 Valid Valid

SLG46580/82/83_DS_062 Page 157 of 193 SLG46580/82/83 Preliminary reg<159:158> Reserved Valid Valid reg<165:160> Matrix OUT: ASM-state6-EN2 Valid Valid reg<167:166> Reserved Valid Valid reg<173:168> Matrix OUT: ASM-state7-EN0 Valid Valid reg<175:174> Reserved Valid Valid reg<181:176> Matrix OUT: ASM-state7-EN1 Valid Valid reg<183:182> Reserved Valid Valid reg<189:184> Matrix OUT: ASM-state7-EN2 Valid Valid reg<191:190> Reserved Valid Valid reg<197:192> Matrix OUT: ASM-state-nRST Valid Valid reg<199:198> Reserved Valid Valid reg<205:200> Matrix OUT: IN0 of LUT3_6 or Delay0 Input (or Counter0 RST Input) Valid Valid reg<207:206> Reserved Valid Valid reg<213:208> Matrix OUT: IN1 of LUT3_6 or External Clock Input of Delay0 (or Counter0) Valid Valid reg<215:214> Reserved Valid Valid reg<221:216> Matrix OUT: IN2 of LUT3_6 Valid Valid reg<223:222> Reserved Valid Valid reg<229:224> Matrix OUT: IN0 of LUT3_7 or Delay1 Input (or Counter1 RST Input) Valid Valid reg<231:230> Reserved Valid Valid reg<237:232> Matrix OUT: IN1 of LUT3_7 or External Clock Input of Delay1 (or Counter1) Valid Valid reg<239:238> Reserved Valid Valid reg<245:240> Matrix OUT: IN2 of LUT3_7 Valid Valid reg<247:246> Reserved Valid Valid reg<253:248> Matrix OUT: IN0 of LUT3_8 or Delay2 Input (or Counter2 RST Input) Valid Valid reg<255:254> Reserved Valid Valid reg<261:256> Matrix OUT: IN1 of LUT3_8 or External Clock Input of Delay2 (or Counter2) Valid Valid reg<263:262> Reserved Valid Valid reg<269:264> Matrix OUT: IN2 of LUT3_8 Valid Valid reg<271:270> Reserved Valid Valid reg<277:272> Matrix OUT: IN0 of LUT3_9 or Delay3 Input (or Counter3 RST Input) Valid Valid reg<279:278> Reserved Valid Valid reg<285:280> Matrix OUT: IN1 of LUT3_9 or External Clock Input of Delay3 (or Counter3) Valid Valid reg<287:286> Reserved Valid Valid reg<293:288> Matrix OUT: IN2 of LUT3_9 Valid Valid reg<295:294> Reserved Valid Valid reg<301:296> Matrix OUT: IN0 of LUT3_10 or Delay4 Input (or Counter4 RST Input) Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 158 of 193 SLG46580/82/83 Preliminary reg<303:302> Reserved Valid Valid reg<309:304> Matrix OUT: IN1 of LUT3_10 or External Clock Input of Delay4 (or Counter4) Valid Valid reg<311:310> Reserved Valid Valid reg<317:312> Matrix OUT: IN2 of LUT3_10 Valid Valid reg<319:318> Reserved Valid Valid reg<325:320> Matrix OUT: IO0 Digital Output Source Valid Valid reg<327:326> Reserved Valid Valid reg<333:328> Matrix OUT: IO0 Output Enable Valid Valid reg<335:334> Reserved Valid Valid reg<341:336> Matrix OUT: IO1 Digital Output Source Valid Valid reg<343:342> Reserved Valid Valid reg<349:344> Matrix OUT: IO2 Digital Output Source Valid Valid reg<351:350> Reserved Valid Valid reg<357:352> Matrix OUT: IO3 Digital Output Source Valid Valid reg<359:358> Reserved Valid Valid reg<365:360> Matrix OUT: IO4 Digital Output Source Valid Valid reg<367:366> Reserved Valid Valid reg<373:368> Matrix OUT: IO4 Output Enable Valid Valid reg<375:374> Reserved Valid Valid reg<381:376> Matrix OUT: IO6 Digital Output Source Valid Valid reg<383:382> Reserved Valid Valid reg<389:384> Matrix OUT: IO6 Output Enable Valid Valid reg<391:390> Reserved Valid Valid reg<397:392> Matrix OUT: IO7 Digital Output Source Valid Valid reg<399:398> Reserved Valid Valid reg<405:400> Matrix OUT: IO8 Digital Output Source Valid Valid reg<407:406> Reserved Valid Valid reg<413:408> Matrix OUT: IO8 Output Enable Valid Valid reg<415:414> Reserved Valid Valid reg<421:416> Matrix OUT: ACMP0 PD (Power Down) Valid Valid reg<423:422> Reserved Valid Valid reg<429:424> Matrix OUT: ACMP1 PD (Power Down) Valid Valid reg<431:430> Reserved Valid Valid reg<437:432> Matrix OUT: ACMP2 PD (Power Down) Valid Valid reg<439:438> Reserved Valid Valid reg<445:440> Matrix OUT: ACMP3 PD (Power Down) Valid Valid reg<447:446> Reserved Valid Valid reg<453:448> Matrix OUT: Input of Filter_0 with fixed time edge detector Valid Valid reg<455:454> Reserved Valid Valid reg<461:456> Matrix OUT: Input of Filter_1 with fixed time edge detector Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 159 of 193 SLG46580/82/83 Preliminary reg<463:462> Reserved Valid Valid reg<469:464> Matrix OUT: Input of Programmable Delay & Edge Detector Valid Valid reg<471:470> Reserved Valid Valid reg<477:472> Matrix OUT: OSC 25kHz/2MHz PD (Power Down) Valid Valid reg<479:478> Reserved Valid Valid reg<485:480> Matrix OUT: LPOSC PD (Power Down) Valid Valid reg<487:486> Reserved Valid Valid reg<493:488> Matrix OUT: IN0 of LUT2_0 or Clock Input of DFF0 Valid Valid reg<495:494> Reserved Valid Valid reg<501:496> Matrix OUT: IN1 of LUT2_0 or Data Input of DFF0 Valid Valid reg<503:502> Reserved Valid Valid reg<509:504> Matrix OUT: IN0 of LUT2_1 or Clock Input of DFF1 Valid Valid reg<511:510> Reserved Valid Valid reg<517:512> Matrix OUT: IN1 of LUT2_1 or Data Input of DFF1 Valid Valid reg<519:518> Reserved Valid Valid reg<525:520> Matrix OUT: IN0 of LUT2_2 or Clock Input of DFF2 Valid Valid reg<527:526> Reserved Valid Valid reg<533:528> Matrix OUT: IN1 of LUT2_2 or Data Input of DFF2 Valid Valid reg<535:534> Reserved Valid Valid reg<541:536> Matrix OUT: IN0 of LUT3_0 or Clock Input of DFF3 Valid Valid reg<543:542> Reserved Valid Valid reg<549:544> Matrix OUT: IN1 of LUT3_0 or Data Input of DFF3 Valid Valid reg<551:550> Reserved Valid Valid reg<557:552> Matrix OUT: IN2 of LUT3_0 or nRST (nSET) of DFF3 Valid Valid reg<559:558> Reserved Valid Valid reg<565:560> Matrix OUT: IN0 of LUT3_1 or Clock Input of DFF4 Valid Valid reg<567:566> Reserved Valid Valid reg<573:568> Matrix OUT: IN1 of LUT3_1 or Data Input of DFF4 Valid Valid reg<575:574> Reserved Valid Valid reg<581:576> Matrix OUT: IN2 of LUT3_1 or nRST (nSET) of DFF4 Valid Valid reg<583:582> Reserved Valid Valid reg<589:584> Matrix OUT: IN0 of LUT3_2 or Clock Input of DFF5 Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 160 of 193 SLG46580/82/83 Preliminary reg<591:590> Reserved Valid Valid reg<597:592> Matrix OUT: IN1 of LUT3_2 or Data Input of DFF5 Valid Valid reg<599:598> Reserved Valid Valid reg<605:600> Matrix OUT: IN2 of LUT3_2 or nRST (nSET) of DFF5 Valid Valid reg<607:606> Reserved Valid Valid reg<613:608> Matrix OUT: IN0 of LUT3_3 or Clock Input of DFF6 Valid Valid reg<615:614> Reserved Valid Valid reg<621:616> Matrix OUT: IN1 of LUT3_3 or Data Input of DFF6 Valid Valid reg<623:622> Reserved Valid Valid reg<629:624> Matrix OUT: IN2 of LUT3_3 or nRST (nSET) of DFF6 Valid Valid reg<631:630> Reserved Valid Valid reg<637:632> Matrix OUT: IN0 of LUT3_4 or Clock Input of DFF7 Valid Valid reg<639:638> Reserved Valid Valid reg<645:640> Matrix OUT: IN1 of LUT3_4 or Data Input of DFF7 Valid Valid reg<647:646> Reserved Valid Valid reg<653:648> Matrix OUT: IN2 of LUT3_4 or nRST (nSET) of DFF7 Valid Valid reg<655:654> Reserved Valid Valid reg<661:656> Matrix OUT: IN0 of LUT3_11 or Input of Pipe Delay or Up/Down selection of Ripple Count- er Valid Valid reg<663:662> Reserved Valid Valid reg<669:664> Matrix OUT: IN1 of LUT3_11 or nRST of Pipe Delay or nRST of Ripple Counter Valid Valid reg<671:670> Reserved Valid Valid reg<677:672> Matrix OUT: IN2 of LUT3_11 or Clock of Pipe Delay or Clock of Ripple Counter Valid Valid reg<679:678> Reserved Valid Valid reg<685:680> Matrix OUT: IN0 of LUT3_5 or Clock Input of DFF8 Valid Valid reg<687:686> Reserved Valid Valid reg<693:688> Matrix OUT: IN1 of LUT3_5 or Data Input of DFF8 Valid Valid reg<695:694> Reserved Valid Valid reg<701:696> Matrix OUT: IN2 of LUT3_5 or nRST (nSET) of DFF8 Valid Valid reg<703:702> Reserved Valid Valid reg 709:704> Matrix OUT: IN0 of LUT4x2_0 Valid Valid reg<711:710> Reserved Valid Valid reg<717:712> Matrix OUT: IN1 of LUT4x2_0 Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 161 of 193 SLG46580/82/83 Preliminary reg<719:718> Reserved Valid Valid reg<725:720> Matrix OUT: IN2 of LUT4x2_0 Valid Valid reg<727:726> Reserved Valid Valid reg<733:728> Matrix OUT: IN3 of LUT4x2_0 Valid Valid reg<735:734> Reserved Valid Valid reg<741:736> Matrix OUT: LDO MODE1 Enable for LDO0/1/2/3 (for SLG46580) Matrix OUT: LDO MODE1 Enable for LDO0/1 (for SLG46582) Matrix OUT: LDO MODE1 Enable for LDO (for SLG46583) Valid Valid reg<743:742> Reserved Valid Valid reg<749:744> Matrix OUT: LDO0_EN (for SLG46580 and SLG46582) Matrix OUT: LDO_EN (for SLG46583) Valid Valid reg<751:750> Reserved Valid Valid reg<757:752> Matrix OUT: LDO1_EN (for SLG46580) Reserved (for SLG46582 and SLG46583) Valid Valid reg<759:758> Reserved Valid Valid reg<765:760> Matrix OUT: LDO2_EN (for SLG46580) Matrix OUT: LDO1_EN (for SLG46582) Reserved (for SLG46583) Valid Valid reg<767:766> Reserved Valid Valid reg<773:768> Matrix OUT: LDO3_EN (for SLG46580) Reserved (for SLG46582 and SLG46583) Valid Valid reg<775:774> Reserved Valid Valid reg<781:776> Matrix OUT: LDO0 2nd VOUT Selection En- able (for SLG46580 and SLG46582) Matrix OUT: LDO 2nd VOUT Selection En- able (for SLG46583) Valid Valid reg<783:782> Reserved Valid Valid reg<789:784> Matrix OUT: LDO1 2nd VOUT Selection En- able (for SLG46580) Reserved (for SLG46582 and SLG46583) Valid Valid reg<791:790> Reserved Valid Valid reg<797:792> Matrix OUT: LDO2 2nd VOUT Selection En- able (for SLG46580) Matrix OUT: LDO1 2nd VOUT Selection En- able (for SLG46582) Reserved (for SLG46583) Valid Valid reg<799:798> Reserved Valid Valid reg<805:800> Matrix OUT: LDO3 2nd VOUT Selection En- able (for SLG46580) Reserved (for SLG46582 and SLG46583) Valid Valid reg<807:806> Reserved Valid Valid reg<813:808> Matrix OUT: RTC Clock Valid Valid reg<815:814> Reserved Valid Valid reg<821:816> Matrix OUT: RTC Trigger signal to read/write RTC CNT values Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 162 of 193 SLG46580/82/83 Preliminary reg<823:822> Reserved Valid Valid reg<829:824> Matrix OUT: ON/OFF command for BUCK Valid Valid reg<831:830> Reserved Valid Valid reg<837:832> Matrix OUT: Reserved Valid Valid reg<839:838> Reserved Valid Valid reg<845:840> Matrix OUT: Reserved Valid Valid reg<847:846> Reserved Valid Valid reg<853:848> Matrix OUT: Reserved Valid Valid reg<855:854> Reserved Valid Valid reg<861:856> Matrix OUT: Reserved Valid Valid reg<863:862> Reserved Valid Valid reg<869:864> Matrix OUT: Reserved Valid Valid reg<871:870> Reserved Valid Valid reg<877:872> Reserved Valid Valid reg<879:878> Reserved Valid Valid reg<881:880> Reserved Valid Valid reg<884:882> LDO2/3 VDD minimum Power Selection for LDO3 (for SLG46580) Reserved (for SLG46582 and SLG46583) 100: 3.6V, 101: 3.9V, 110: 4.3V, 111: 4.65V Valid Valid reg<887:885> LDO2/3 VDD minimum Power Selection for LDO2 (for SLG46580) LDO1 VDD minimum Power Selection for LDO1 (for SLG46582) Reserved (for SLG46583) 100: 3.6V, 101: 3.9V, 110: 4.3V, 111: 4.65V Valid Valid reg<895:888> Reserved Valid Invalid reg<903:896> CNT2 Counted Value for I2C read Valid Invalid reg<911:904> CNT4 Counted Val ue for I2C read Valid Invalid reg<919:912> Reserved Valid Invalid reg<927:920> and Reserved Valid Invalid reg<935:928> Reserved (for SLG4 6582 and SLG46583) Valid Invalid reg<943:936> Shadow buffer for RTC counter <7:0> Valid Valid reg<950:944> Shadow buffer for RTC counter <14:8> Valid Valid reg<951> Reserved Valid Valid reg<959:952> Shadow buffer for R TC counter <23:16> Valid Valid reg<967:960> Shadow buffer for R TC counter <31:24> Valid Valid reg<975:968> Shadow buffer for R TC counter <39:32> Valid Valid reg<983:976> Shadow buffer for R TC counter <47:40> Valid Valid reg<988:984> Reserved Valid Valid reg<989> Shadow buffer data transfer direction selec- tion Valid Valid reg<990> Shadow buffer trigger signal selection Valid Valid reg<991> RTC 32-bit time counter clock source 0: From 15-bit counter divider 1: From RTC clock Valid Valid reg<999:992> Alarm DCMP <23:16> Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 163 of 193 SLG46580/82/83 Preliminary reg<1007:1000> Alarm DCMP <31:24> Valid Valid reg<1015:1008> Alarm DCMP <39:32> Valid Valid reg<1023:1016> Alarm DCMP <47:40> Valid Valid IO0 reg<1024> Reserved Valid Valid reg<1025> IO0 Pull Up/Dow n Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1027:1026> IO0 Pull Up/Down Resistor Value Selection 00: Floating 01: 10K 10: 100K 11: 1M Valid Valid reg<1029:1028> IO0 Mode Control (sig_io0_oe=0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved Valid Valid reg<1031:1030> IO0 Mode Control (sig_io0_oe=1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X Valid Valid IO1 reg<1032> Reserved Valid Valid reg<1033> IO1 Driver S trength Selection 0: 1X 1: 2X Valid Valid reg<1034> IO1 Pull Up/Dow n Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1036:1035> IO1 Pull Up/Down Resistor Value Selection 00: Floating 01: 10K 10: 100K 11: 1M Valid Valid reg<1039:1037> IO1 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Analog Input/Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input & Open Drain NMOS Valid Valid IO2 reg<1040> Reserved Valid Valid reg<1041> IO2 Driver S trength Selection 0: 1X 1: 2X Valid Valid reg<1042> IO2 Pull Up/Dow n Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1044:1043> IO2 Pull Up/Down Resistor Value Selection 00: Floating 01: 10K 10: 100K 11: 1M Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 164 of 193 SLG46580/82/83 Preliminary reg<1047:1045> IO2 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Open Drain NMOS Valid Valid IO3 reg<1048> Reserved Valid Valid reg<1049> IO3 Driver S trength Selection 0: 1X 1: 2X Valid Valid reg<1050> IO3 Pull Up/Dow n Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1052:1051> IO3 Pull Up/Down Resistor Value Selection 00: Floating 01: 10K 10: 100K 11: 1M Valid Valid reg<1055:1053> IO3 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Open Drain NMOS Valid Valid IO4 reg<1056> Reserved Valid Valid reg<1057> IO4 Pull Up/Dow n Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1059:1058> IO4 Pull Down Resistor Value Selection 00: Floating 01: 10K 10: 100K 11: 1M Valid Valid reg<1061:1060> IO4 Mode Control (sig_io4_oe=0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Analog Input/Output Valid Valid reg<1063:1062> IO4 Mode Control (sig_io4_oe=1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X Valid Valid IO5 reg<1064> Reserved Valid Valid reg<1065> Reserved Valid Valid reg<1067:1066> Reserved Valid Valid reg<1069:1068> IO5 Pull Down Resistor Value Selection 00: Floating 01: 10K 10: 100K 11: 1M Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 165 of 193 SLG46580/82/83 Preliminary reg<1071:1070> IO5 Mode Control 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved Valid Valid SCL reg<1072> Reserved Valid Valid reg<1073> Reserved Valid Valid reg<1074> Reserved Valid Valid reg<1076:1075> Reserved Valid Valid reg<1078:1077> SCL Mode Control 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved Valid Valid reg<1079> Reserved Valid Valid SDA reg<1080> Reserved Valid Valid reg<1081> SDA Driver Strength Selection 0: 1X 1: 2X Valid Valid reg<1082> Reserved Valid Valid reg<1084:1083> Reserved Valid Valid reg<1086:1085> SDA Mode Control 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved Valid Valid reg<1087> Reserved Valid Valid IO6 reg<1088> Reserved Valid Valid reg<1089> IO6 Pull Up/Dow n Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1091:1090> IO6 Pull Up/Down Resistor Value Selection 00: Floating 01: 10K 10: 100K 11: 1M Valid Valid reg<1093:1092> IO6 Mode Control (sig_io6_oe=0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Analog Input/Output Valid Valid reg<1095:1094> IO6 Mode Control (sig_io6_oe=1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X Valid Valid IO7 reg<1096> Reserved Valid Valid reg<1097> IO7 Driver S trength Selection 0: 1X 1: 2X Valid Valid reg<1098> IO7 Pull Up/Dow n Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 166 of 193 SLG46580/82/83 Preliminary reg<1100:1099> IO7 Pull Up/Down Resistor Value Selection 00: Floating 01: 10K 10: 100K 11: 1M Valid Valid reg<1103:1101> IO7 Mode Control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Analog Input/Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input & Open Drain NMOS Valid Valid IO8 reg<1104> Reserved Valid Valid reg<1105> IO8 Pull Up/Dow n Resistor Selection 0: Pull Down Resistor 1: Pull Up Resistor Valid Valid reg<1107:1106> IO8 Pull Up/Down Resistor Value Selection 00: Floating 01: 10K 10: 100K 11: 1M Valid Valid reg<1109:1108> IO8 Mode Control (sig_io8_oe=0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Analog Input/Output Valid Valid reg<1111:1110> IO8 Mode Control (sig_io8_oe=1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X Valid Valid ACMP reg<1112> ACMP1 Positive Input Source Select - ACMP0 IN+ Source 0: Disable 1: Enable Valid Valid reg<1113> ACMP1 Analog Buffer Enable (Max. BW 1MHz) 0: Disable analog buffer 1: Enable analog buffer Valid Valid reg<1115:1114> ACMP1 Hysteresis Enable 00: 0 mV 01: 25 mV 10: 50 mV 11: 200 mV (01: for both external & internal VREF, 10 & 11: for only internal VREF, External VREF will not have 50 mV & 200 mV hysteresis.) Valid Valid reg<1116> ACMP0 Positive I nput Source Select VDD 0: Disable 1: Enable Valid Valid reg<1117> ACMP0 Analog Buffer Enable (Max. BW 1MHz) 0: Disable analog buffer 1: Enable analog buffer Valid Valid reg<1119:1118> ACMP0 Hysteresis Enable 00: 0 mV 01: 25 mV 10: 50 mV 11: 200 mV (01: for both external & internal VREF, 10 & 11: for only internal VREF, External VREF will not have 50 mV & 200 mV hysteresis.) Valid Valid reg<1120> ACMP3 Positive Input Source Select - ACMP2 IN+ Source 0: Disable 1: Enable Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 167 of 193 SLG46580/82/83 Preliminary reg<1123:1121> ACMP3 Hysteresis Enable 000: 0 mV 001: 25 mV 010: 50 mV 011: 200 mV 100: Reserved 101: Reserved 110: 100 mV 111: 150 mV (001: for both external & internal VREF, 010 & 011 & 110 & 111: for only internal VREF, External VREF will not have 50 mV, 100 mV, 150 mV & 200 mV hysteresis.) Valid Valid reg<1124> ACMP2 Positive Input Source Select - ACMP0 IN+ Source 0: Disable 1: Enable Valid Valid reg<1127:1125> ACMP2 Hysteresis Enable 000: 0 mV 001: 25 mV 010: 50 mV 011: 200 mV 100: Reserved 101: Reserved 110: 100 mV 111: 150 mV (001: for both external & internal VREF, 010 & 011 & 110 & 111: for only internal VREF, External VREF will not have 50 mV, 100 mV, 150 mV & 200 mV hysteresis.) Valid Valid LUT reg<1128> LUT3_4 or DFF7 with nRST/nSET Select 0: LUT3_4 1: DFF7 with nRST/nSET Valid Valid reg<1129> LUT3_3 or DFF6 with nRST/nSET Select 0: LUT3_3 1: DFF6 with nRST/nSET Valid Valid reg<1130> LUT3_2 or DFF5 with nRST/nSET Select 0: LUT3_2 1: DFF5 with nRST/nSET Valid Valid reg<1131> LUT3_1 or DFF4 with nRST/nSET Select 0: LUT3_1 1: DFF4 with nRST/nSET Valid Valid reg<1132> LUT3_0 or DFF3 with nRST/nSET Select (Two consecutive DFFs if reg<1431>=1 for ASM) 0: LUT3_0 1: DFF3 with nRST/nSET Valid Valid reg<1133> LUT2_2 or DFF2 Select 0: LUT2_2 1: DFF2 Valid Valid reg<1134> LUT2_1 or DFF1 Select 0: LUT2_1 1: DFF1 Valid Valid reg<1135> LUT2_0 or DFF0 Select 0: LUT2_0 1: DFF0 Valid Valid LUT3 reg<1136> Reserved Valid Valid reg<1137> Reserved Valid Valid reg<1138> LUT3_5 or DFF8 with nRST/nSET Select 0: LUT3_5 1: DFF8 with nRST/nSET Valid Valid reg<1139> LUT3_10 or DLY/CNT4(8bits) Select 0: LUT3_10 1: DLY/CNT4(8bits) Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 168 of 193 SLG46580/82/83 Preliminary reg<1140> LUT3_9 or DLY/CNT3(8bits) Select 0: LUT3_9 1: DLY/CNT3(8bits) Valid Valid reg<1141> LUT3_8 or DLY/CNT2(8bits) Select 0: LUT3_8 1: DLY/CNT2(8bits) Valid Valid reg<1142> LUT3_7 or DLY/CNT1(8bits) Select 0: LUT3_7 1: DLY/CNT1(8bits) Valid Valid reg<1143> LUT3_6 or DLY/CNT0(8bits) Select 0: LUT3_6 1: DLY/CNT0(8bits) Valid Valid LUT2 reg<1144> LUT2_1 <0> Valid Valid reg<1145> LUT2_1 <1> / DFF1 Initial Polarity Select 0: Low 1: High Valid Valid reg<1146> LUT2_1 <2> / DFF1 Output Select 0: Q output 1: nQ output Valid Valid reg<1147> LUT2_1 <3> / DFF1 or Latch1 Select 0: DFF function 1: Latch function Valid Valid reg<1148> LUT2_0 <0> Valid Valid reg<1149> LUT2_0 <1> / DFF0 Initial Polarity Select 0: Low 1: High Valid Valid reg<1150> LUT2_0 <2> / DFF0 Output Select 0: Q output 1: nQ output Valid Valid reg<1151> LUT2_0 <3> / DFF0 or Latch0 Select 0: DFF function 1: Latch function Valid Valid LUT3 reg<1155:1152> Reserved Valid Valid reg<1156> LUT2_2 <0> Valid Valid reg<1157> LUT2_2 <1> / DFF2 Initial Polarity Select 0: Low 1: High Valid Valid reg<1158> LUT2_2 <2> / DFF2 Output Select 0: Q output 1: nQ output Valid Valid reg<1159> LUT2_2 <3> / DFF2 or Latch2 Select 0: DFF function 1: Latch function Valid Valid reg<1163:1160> LUT3_0 <3:0> Valid Valid reg<1164> LUT3_0 <4> / DFF3 Initial Polarity Select 0: Low 1: High Valid Valid reg<1165> LUT3_0 <5> / DFF3 nRST or nSET Select 0: nRST from Matrix Output 1: nSET from Matrix Output Valid Valid reg<1166> LUT3_0 <6> / DFF3 Output Select 0: Q output 1: nQ output Valid Valid reg<1167> LUT3_0 <7> / DFF3 or Latch3 Select 0: DFF function 1: Latch function Valid Valid reg<1171:1168> LUT3_1 <3:0> Valid Valid reg<1172> LUT3_1 <4> / DFF4 Initial Polarity Select 0: Low 1: High Valid Valid reg<1173> LUT3_1 <5> / DFF4 nRST or nSET Select 0: nRST from Matrix Output 1: nSET from Matrix Output Valid Valid reg<1174> LUT3_1 <6> / DFF4 Output Select 0: Q output 1: nQ output Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 169 of 193 SLG46580/82/83 Preliminary reg<1175> LUT3_1 <7> / DFF4 or Latch4 Select (for SLG46580) 0: DFF function 1: Latch function Valid Valid reg<1179:1176> LUT3_2 <3:0> Valid Valid reg<1180> LUT3_2 <4> / DFF5 Initial Polarity Select 0: Low 1: High Valid Valid reg<1181> LUT3_2 <5> / DFF5 nRST or nSET Select 0: nRST from Matrix Output 1: nSET from Matrix Output Valid Valid reg<1182> LUT3_2 <6> / DFF5 Output Select 0: Q output 1: nQ output Valid Valid reg<1183> LUT3_2 <7> / DFF5 or Latch5 Select 0: DFF function 1: Latch function Valid Valid reg<1187:1184> LUT3_3 <3:0> Valid Valid reg<1188> LUT3_3 <4> / DFF6 Initial Polarity Select 0: Low 1: High Valid Valid reg<1189> LUT3_3 <5> / DFF6 nRST or nSET Select 0: nRST from Matrix Output 1: nSET from Matrix Output Valid Valid reg<1190> LUT3_3 <6> / DFF6 Output Select 0: Q output 1: nQ output Valid Valid reg<1191> LUT3_3 <7> / DFF6 or Latch6 Select 0: DFF function 1: Latch function Valid Valid reg<1195:1192> LUT3_4 <3:0> Valid Valid reg<1196> LUT3_4 <4> / DFF7 Initial Polarity Select 0: Low 1: High Valid Valid reg<1197> LUT3_4 <5> / DFF7 nRST or nSET Select 0: nRST from Matrix Output 1: nSET from Matrix Output Valid Valid reg<1198> LUT3_4 <6> / DFF7 Output Select 0: Q output 1: nQ output Valid Valid reg<1199> LUT3_4 <7> / DFF7 or Latch7 Select 0: DFF function 1: Latch function Valid Valid reg<1203:1200> LUT3_5 <3:0> Valid Valid reg<1204> LUT3_5 <4> / DFF8 Initial Polarity Select 0: Low 1: High Valid Valid reg<1205> LUT3_5 <5> / DFF8 nRST or nSET Select 0: nRST from Matrix Output 1: nSET from Matrix Output Valid Valid reg<1206> LUT3_5 <6> / DFF8 Output Select 0: Q output 1: nQ output Valid Valid reg<1207> LUT3_5 <7> / DFF8 or Latch8 Select 0: DFF function 1: Latch function Valid Valid Reserved reg<1215:1208> Reserved Valid Valid reg<1223:1216> Reserved Reserved for Valid Invalid LUT3 & DLY/CNT reg<1227:1224> LUT3_11 <3:0> / Pipe Delay OUT0 Select / Ripple Counter END<0>,nSET<2:0> Valid Valid reg<1231:1228> LUT3_11 <7:4> / Pipe Delay OUT1 Select / Ripple Counter RSVD,MODE,END<2:1> Valid Valid reg<1232> Reserved Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 170 of 193 SLG46580/82/83 Preliminary reg<1233> DLY/CNT4 Delayed Edge Output Selection 0: Default function from reg<1277> 1: Delayed edge detect Valid Valid reg<1234> DLY/CNT3 Delayed Edge Output Selection 0: Default function from reg<1269> 1: Delayed edge detect Valid Valid reg<1235> DLY/CNT2 Delayed Edge Output Selection 0: Default function from reg<1261> 1: Delayed edge detect Valid Valid reg<1236> DLY/CNT1 Delayed Edge Output Selection 0: Default function from reg<1253> 1: Delayed edge detect Valid Valid reg<1237> Pipe Delay Select or Ripple counter Select 0: Pipe Delay 1: Ripple Counter Valid Valid reg<1238> LUT3_11 or Pipe Delay Select 0: LUT3_11 1: Pipe Delay / Ripple counter by reg<1237> Valid Valid reg<1239> Pipe Delay OUT1 Polarity Select 0: Non-Inverted 1: Inverted Valid Valid DLY/CNT0 reg<1241:1240> DLY0 Edge Select or Asynchronous CNT0 Reset 00: On both Falling and Rising Edges 01: on Falling Edge only 10: on Rising Edge only 11: No Delay on either Falling or Rising Edges / High Level Counter Reset Valid Valid reg<1244:1242> DLY/CNT0 Clock Source Select 000: OSC 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: LPOSC Clock 110: External Clock 111: Counter1 Overflow Valid Valid reg<1245> CNT0/FSM0's Q are Set to data or Reset to 0s Selection (8bits) 0: Reset to 0s 1: Set to data (Reg<1543:1536>) Valid Valid reg<1247:1246> DLY/CNT0 Mode Selection 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Valid Valid DLY/CNT1 reg<1249:1248> DLY1 Edge Select or Asynchronous CNT1 Reset 00: On both Falling and Rising Edges 01: On Falling Edge only 10: On Rising Edge only 11: No Delay on either Falling or Rising Edges / High Level Counter Reset Valid Valid reg<1252:1250> DLY/CNT1 Clock Source Select 000: OSC 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: LPOSC Clock 110: External Clock 111: Counter1 Overflow Valid Valid reg<1253> DLY/CNT1 Output Selection 0: Default Output 1: Edge Detector Output Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 171 of 193 SLG46580/82/83 Preliminary reg<1255:1254> DLY/CNT1 Mode Selection 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Valid Valid DLY/CNT2 reg<1257:1256> DLY2 Edge Select or Asynchronous CNT2 Reset 00: On both Falling and Rising Edges 01: on Falling Edge only 10: on Rising Edge only 11: No Delay on either Falling or Rising Edges / High Level Counter Reset Valid Valid reg<1260:1258> DLY/CNT2 Clock Source Select 000: OSC 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: LPOSC Clock 110: External Clock 111: Counter1 Overflow Valid Valid reg<1261> DLY/CNT2 Output Selection 0: Default Output 1: Edge Detector Output Valid Valid reg<1263:1262> DLY/CNT2 Mode Selection 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Valid Valid DLY/CNT3 reg<1265:1264> DLY3 Edge Select or Asynchronous CNT3 Reset 00: On both Falling and Rising Edges 01: On Falling Edge only 10: On Rising Edge only 11: No Delay on either Falling or Rising Edges / High Level Counter Reset Valid Valid reg<1268:1266> DLY/CNT3 Clock Source Select 000: OSC 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: LPOSC Clock 110: External Clock 111: Counter1 Overflow Valid Valid reg<1269> DLY/CNT3 Output Selection 0: Default Output 1: Edge Detector Output Valid Valid reg<1271:1270> DLY/CNT3 Mode Selection 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Valid Valid DLY/CNT4 reg<1273:1272> DLY4 Edge Select or Asynchronous CNT4 Reset 00: On both Falling and Rising Edges 01: On Falling Edge only 10: On Rising Edge only 11: No Delay on either Falling or Rising Edges / High Level Counter Reset Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 172 of 193 SLG46580/82/83 Preliminary reg<1276:1274> DLY/CNT4 Clock Source Select 000: OSC 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: LPOSC Clock 110: External Clock 111: Counter1 Overflow Valid Valid reg<1277> DLY/CNT4 Output Selection 0: Default Output 1: Edge Detector Output Valid Valid reg<1279:1278> DLY/CNT4 Mode Selection 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Valid Valid Reserved reg<1280> Reserved Valid Valid reg<1281> Reserved Valid Valid reg<1282> External Clock Source Select instead of 25kHz/2MHz 0: Internal Oscillator, 1: External Clock (EXT_CLK) Valid Valid DLY/CNT Polarity Select reg<1283> Select the Polarit y of DLY/CNT4's Output 0: Default Output 1: Inverted Output Valid Valid reg<1284> Select the Polarit y of DLY/CNT3's Output 0: Default Output 1: Inverted Output Valid Valid reg<1285> Select the Polarit y of DLY/CNT2's Output 0: Default Output 1: Inverted Output Valid Valid reg<1286> Select the Polarit y of DLY/CNT1's Output 0: Default Output 1: Inverted Output Valid Valid reg<1287> Select the Polarit y of DLY/CNT0's Output 0: Default Output 1: Inverted Output Valid Valid OSC reg<1289:1288> LPOSC Clock Pre-divider 00: Div1, 01:Div2, 10: Div4, 11: Div16 Valid Valid reg<1290> Force LPOS C Oscillator ON 0: Auto Power ON (if any CNT/DLY use LPOSC source) 1: Force Power ON Valid Valid reg<1292:1291> OSC Clock Pre-divider 00: Div1 01: Div2 10: Div4 11: Div8 Valid Valid reg<1293> OSC Fast Start-Up Enable 0: Disable 1: Enable Valid Valid reg<1294> Oscillator (25kHz: RC-OSC, 2M: RC-OSC) Select 0: 25 kHz RC-OSC 1: 2 MHz RC-OSC Valid Valid reg<1295> Force Oscillator ON 0: Auto Power ON (if any CNT/DLY use 25K source) 1: Force Power ON Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 173 of 193 SLG46580/82/83 Preliminary reg<1298:1296> Internal OSC 25 kHz Frequency Divider Control for matrix input <28> 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 Valid Valid reg<1299> OSC Clock 25 kHz to matrix input <28> en- able 0: Disable 1: Enable Valid Valid reg<1302:1300> Internal OSC 25 kHz Frequency Divider Control for matrix input <27> 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 Valid Valid reg<1303> OSC Clock 25 kHz to matrix input <27> en- able 0: Disable 1: Enable Valid Valid IO5 reg<1304> IO5 reset level polarity selection 0: Non-inverted 1: Inverted Valid Valid reg<1305> IO5 reset bypass selection 0: Edge selection 1: Level selection Valid Valid reg<1306> IO5 reset edge selection 0: Rising edge 1: Falling edge Valid Valid reg<1307> IO5 reset enable 0: Disable 1: Enable Valid Valid reg<1309:1308> Select the Edge Mode of Programmable De- lay & Edge Detector 00: Rising Edge Detector 01: Falling Edge Detector 10: Both Edge Detector 11: Both Edge Delay Valid Valid reg<1311:1310> Delay Value Select for Programmable Delay & Edge Detector (VDD = 3.3V, typical) 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns Valid Valid ASM reg<1314:1312> ASM_reg_init<2:0> for ASM state default setup bits Valid Valid reg<1319:1315> Reserved Valid Valid reg<1322:1320> ASM_state0_dec8x1_EN1 Valid Valid reg<1323> Reserved Valid Valid reg<1326:1324> ASM_state0_dec8x1_EN0 Valid Valid reg<1327> Reserved Valid Valid reg<1330:1328> ASM_state1_dec8x1_EN0 Valid Valid reg<1331> Reserved Valid Valid reg<1334:1332> ASM_state0_dec8x1_EN2 Valid Valid reg<1335> ASM Rising Edge Detect Enable on EN2 of state0 0: Disable 1: Enable Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 174 of 193 SLG46580/82/83 Preliminary reg<1338:1336> ASM_state1_dec8x1_EN2 Valid Valid reg<1339> ASM Rising Edge Detect Enable on EN2 of state1 0: Disable 1: Enable Valid Valid reg<1342:1340> ASM_state1_dec8x1_EN1 Valid Valid reg<1343> Reserved Valid Valid reg<1346:1344> ASM_state2_dec8x1_EN1 Valid Valid reg<1347> Reserved Valid Valid reg<1350:1348> ASM_state2_dec8x1_EN0 Valid Valid reg<1351> Reserved Valid Valid reg<1354:1352> ASM_state3_dec8x1_EN0 Valid Valid reg<1355> Reserved Valid Valid reg<1358:1356> ASM_state2_dec8x1_EN2 Valid Valid reg<1359> ASM Rising Edge Detect Enable on EN2 of state2 0: Disable 1: Enable Valid Valid reg<1362:1360> ASM_state3_dec8x1_EN2 Valid Valid reg<1363> ASM Rising Edge Detect Enable on EN2 of state3 0: Disable 1: Enable Valid Valid reg<1366:1364> ASM_state3_dec8x1_EN1 Valid Valid reg<1367> Reserved Valid Valid reg<1370:1368> ASM_state4_dec8x1_EN1 Valid Valid reg<1371> Reserved Valid Valid reg<1374:1372> ASM_state4_dec8x1_EN0 Valid Valid reg<1375> Reserved Valid Valid reg<1378:1376> ASM_state5_dec8x1_EN0 Valid Valid reg<1379> Reserved Valid Valid reg<1382:1380> ASM_state4_dec8x1_EN2 Valid Valid reg<1383> ASM Rising Edge Detect Enable on EN2 of state4 0: Disable 1: Enable Valid Valid reg<1386:1384> ASM_state5_dec8x1_EN2 Valid Valid reg<1387> ASM Rising Edge Detect Enable on EN2 of state5 0: Disable 1: Enable Valid Valid reg<1390:1388> ASM_state5_dec8x1_EN1 Valid Valid reg<1391> Reserved Valid Valid reg<1394:1392> ASM_state6_dec8x1_EN1 Valid Valid reg<1395> Reserved Valid Valid reg<1398:1396> ASM_state6_dec8x1_EN0 Valid Valid reg<1399> Reserved Valid Valid reg<1402:1400> ASM_state7_dec8x1_EN0 Valid Valid reg<1403> Reserved Valid Valid reg<1406:1404> ASM_state6_dec8x1_EN2 Valid Valid reg<1407> ASM Rising Edge Detect Enable on EN2 of state6 0: Disable 1: Enable Valid Valid reg<1410:1408> ASM_state7_dec8x1_EN2 Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 175 of 193 SLG46580/82/83 Preliminary reg<1411> ASM Rising Edge Detect Enable on EN2 of state7 Valid Valid reg<1414:1412> ASM_state7_dec8x1_EN1 Valid Valid reg<1415> Reserved Valid Valid Filter / Edge Detector reg<1417:1416> Select the edge mode of Edge Detector_1 00: Rising Edge 01: Falling Edge 10: Both Edge 11: Delay Valid Valid reg<1418> Filter_1/Edge Detector_1 output Polarity Se- lect 0: Filter_1 output 1: Filter_1 output inverted Valid Valid reg<1419> Filter_1 (Typ. 50nS @VDD=3.3V) or Edge Detector_1 (Typ. 125nS @VDD=3.3V) Se- lect 0: Filter_1 1: Edge Detector_1 Valid Valid reg<1421:1420> Select the edge mode of Edge Detector_0 00: Rising Edge 01: Falling Edge 10: Both Edge 11: Delay Valid Valid reg<1422> Filter_0/Edge Detector_0 output Polarity Se- lect 0: Filter_0 output 1: Filter_0 output inverted Valid Valid reg<1423> Filter_0 (Typ. 70 ns @VDD=3.3V) or Edge Detector_0 Select (Typ. 125 ns @ VDD=3.3V) 0: Filter_0 1: Edge Detector_0 Valid Valid VREF / Bandgap reg<1424> Reserved Valid Valid reg<1426:1425> Bandgap OK for ACMP Output Delay Time Select, the start Time is "nRST_core go to High" 00, 10 with reg<1434:1432>=100 (Wide VDD range, 1.7V ~ 5.5V): Auto-delay mode, 550uS for VDD<2.7V & 100uS for 2.7V<VDD 00, 10 with reg<1434:1432>=X10: Always 100uS delay for 2.7V<VDD 00, 10 with reg<1434:1432>=XX1: Always 5 5 0 u S d e l a y f o r V D D < 2 . 7 V, 01: Always 550 us delay regardless of reg<1434:1432> & VDD, 11: Always 100us delay with 2.7V<VDD re- gardless of reg<1434:1432> Valid Valid reg<1427> Reserved Valid Valid reg<1428> Vref Op Amp Offset Chopper Enable 0: Disable 1: Enable Valid Valid reg<1429> Reserved 0: Disable 1: Enable Valid Valid reg<1430> Reserved 0: 2 MHz 1: 1 MHz Valid Valid reg<1431> Two consecut ive DFFs enable for ASM 0: Disable 1: Enable Valid Valid reg<1434:1432> CP function selection & Power divider (VDD/3, VDD/4) ON/OFF 100: CP Auto ON/OFF (Use for 1.71V<VDD<5.5V) X10: CP always OFF (Use for 2.7V<VDD), XX1: CP always ON (Use for VDD<2.7V) 0XX: Power divider off (if there is no use of VDD/3,VDD/4 @ACMP negative in) Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 176 of 193 SLG46580/82/83 Preliminary reg<1435> Reserved Valid Valid reg<1436> Force Bandgap ON 0: Auto-Mode 1: Enable (if chip is Power Down, the Band- gap will Power Down even if it is Set to 1). Valid Valid reg<1437> NVM Power Down 0: None (Or Programming Enable) 1: Power Down (Or Programming Disable) Valid Valid reg<1438> Reserved Valid Valid reg<1439> GPIO Quick Charge Enable 0: Disable 1: Enable Valid Valid Wake/Sleep reg<1440> Reserved Valid Valid reg<1441> Reserved Valid Valid reg<1442> ACMP0 Wake & Sleep function Enable 0: Disable 1: Enable Valid Valid reg<1443> ACMP1 Wake & Sleep function Enable 0: Disable 1: Enable Valid Valid reg<1444> ACMP2 Wake & Sleep function Enable 0: Disable 1: Enable Valid Valid reg<1445> ACMP3 Wake & Sleep function Enable 0: Disable 1: Enable Valid Valid reg<1446> Wake Sleep Output State When WS Oscilla- tor is Power Down if DLY/CNT0 Mode Selec- tion is "11" 0: Low 1: High Valid Valid reg<1447> Wake Sleep Ratio Control Mode Selection if DLY/CNT0 Mode Selection is "11" 0: Default Mode 1: Wake Sleep Ratio Control Mode Valid Valid LDO reg<1448> LDO1 PS_Mode_Gate (LDO1 turn-on/off is controlled by LDO1_EN matrix output) (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: LDO Mode Enable (for SLG46580) 1: Power switch Mode Enable (for SLG46580) Valid Valid reg<1449> LDO1 Start-up Ramping Slope Divide Enable (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: Disable 1: Enable (Div 8 of reg<1600>) Valid Valid reg<1450> LDO1 Over-current & Short-current Detection Enable (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: Disable (for SLG46580) 1: Enable (for SLG46580) Valid Valid reg<1451> LDO1 Discharge resistor Enable (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: No discharge resistor (for SLG46580) 1: 300 ohm discharge resistor (for SLG46580) Valid Valid reg<1452> LDO0 PS_Mode_Gate (LDO0 turn-on/off is controlled by LDO0_EN matrix output) (for SLG46580 and SLG46582) LDO PS_Mode_Gate (LDO0 turn-on/off is controlled by LDO0_EN matrix output) (for SLG46583) 0: LDO Mode Enable 1: Power switch Mode Gate Enable Valid Valid reg<1453> LDO0 Start-up Ramping Slope Divide Enable (for SLG46580 and SLG46582) LDO Start-up Ramping Slope Divide Enable (for SLG46583) 0: Disable (for SLG46580) 1: Enable (Div 8 of reg<1592>) Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 177 of 193 SLG46580/82/83 Preliminary reg<1454> LDO0 Over-current & Short-current Detection Enable (for SLG46580 and SLG46582) LDO Over-current & Short-current Detection Enable (for SLG46583) 0: Disable 1: Enable Valid Valid reg<1455> LDO0 Discharge resistor Enable (for SLG46580 and SLG46582) LDO Discharge resistor Enable (for SLG46583) 0: No discharge resistor 1: 300 Ohm discharge resistor Valid Valid reg<1456> LDO3 PS_Mode_Gate (LDO3 turn-on/off is controlled by LDO3_EN matrix output) (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: LDO Mode Enable (for SLG46580) 1: Power switch Mode Gate Enable (for SLG46580) Valid Valid reg<1457> LDO3 Start-up Ramping Slope Divide Enable (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: Disable 1: Enable (Div 8 of reg<1616>) Valid Valid reg<1458> LDO3 Over-current & Short-current Detection Enable (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: Disable (for SLG46580) 1: Enable (for SLG46580) Valid Valid reg<1459> LDO3 Discharge resistor Enable (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: No discharge resistor (for SLG46580) 1: 300 Ohm discharge resistor (for SLG46580) Valid Valid reg<1460> LDO2 PS_Mode_Gate (LDO2 turn-on/off is controlled by LDO1_EN matrix output) (for SLG46580) LDO1 PS_Mode_Gate (LDO2 turn-on/off is controlled by LDO1_EN matrix output) (for SLG46582) Reserved (for SLG46583) 0: LDO Mode Enable (for SLG46580) 1: Power switch Mode Gate Enable (for SLG46580) Valid Valid reg<1461> LDO2 Start-up Ramping Slope Divide Enable (for SLG46580) LDO1 Start-up Ramping Slope Divide Enable (for SLG46582) Reserved (for SLG46583) 0: Disable 1: Enable (Div 8 of reg<1608>) Valid Valid reg<1462> LDO2 Over-current & Short-current Detection Enable (for SLG46580) LDO1 Over-current & Short-current Detection Enable (for SLG46582) Reserved (for SLG46583) 0: Disable (for SLG46580) 1: Enable (for SLG46580) Valid Valid reg<1463> LDO2 Discharge resistor Enable (for SLG46580) LDO1 Discharge resistor Enable (for SLG46582) Reserved (for SLG46583) 0: No discharge resistor (for SLG46580) 1: 300 ohm discharge resistor (for SLG46580) Valid Valid reg<1465:1464> Reserved Reserved Valid Invalid reg<1467:1466> Reserved Valid Invalid reg<1469:1468> Reserved Reserved Valid Invalid reg<1471:1470> Reserved Reserved Valid Invalid reg<1479:1472> Reserved Reserved Valid Invalid reg<1487:1480> Reserved Reserved Valid Invalid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 178 of 193 SLG46580/82/83 Preliminary reg<1488> ACMP1 100 uA C urrent Source Enable 0: Disable 1: Enable Valid Valid reg<1489> Reserved Valid Valid reg<1490> Reserved Valid Valid reg<1491> LDO2 VOUT output connection enable to ACMP3 (for SLG46580) LDO1 VOUT output connection enable to ACMP3 (for SLG46582) Reserved (for SLG46583) 0: Default ACMP function (for SLG46580) 1: Enable LDO2 VOUT function (for SLG46580) Valid Valid reg<1492> LDO0 VOUT output connection enable to ACMP3 (for SLG46580 and SLG46582) LDO VOUT output connection enable to AC- MP3 (for SLG46583) 0: Default ACMP function 1: Enable LDO0 VOUT function Valid Valid reg<1493> TS output conn ection enable to ACMP2 0: Default ACMP function 1: Enable TS function Valid Valid reg<1494> LDO2/3 VIN connection enable to ACMP1 (for SLG46580) LDO1 VIN connection enable to ACMP1 (for SLG46582) LDO VIN connection enable to ACMP1 (for SLG46583) 0: Default ACMP function (for SLG46580 and SLG46582) 1: Enable UVLO1 function (for SLG46580 and SLG46582) 0: Default ACMP function (for SLG46583) 1: Enable UVLO function (for SLG46583) Valid Valid reg<1495> LDO0/1 VIN connection enable to ACMP0 (for SLG46580) LDO0 VIN connection enable to ACMP0 (for SLG46582) LDO VIN connection enable to ACMP0 (for SLG46583) 0: Default ACMP function (for SLG46580 and SLG46582) 1: Enable UVLO0 function (for SLG46580 and SLG46582) 0: Default ACMP function (for SLG46583) 1: Enable UVLO function (for SLG46583) Valid Valid reg<1496> Reserved Valid Valid reg<1497> Reserved Valid Valid reg<1498> Reserved Valid Valid reg<1499> Reserved Valid Valid reg<1503:1500> Reserved Valid Valid reg<1519:1504> LUT4x2_0 Output0 <15:0> Valid Valid reg<1535:1520> LUT4x2_0 Output1 <15:0> Valid Valid LUT / DLY/CNT Control Data reg<1543:1536> LUT3_6 <7:0> or DLY/CNT0 Control Data 1 - 255 (Delay Time = [Counter Control Data + 1] / Freq) Valid Valid reg<1551:1544> LUT3_7 <7:0> or DLY/CNT1 Control Data 1 - 255 (Delay Time = [Counter Control Data + 1] / Freq) Valid Valid reg<1559:1552> LUT3_8 <7:0> or DLY/CNT2 Control Data 1 - 255 (Delay Time = [Counter Control Data + 1] / Freq) Valid Valid reg<1567:1560> LUT3_9 <7:0> or DLY/CNT3 Control Data 1 - 255 (Delay Time = [Counter Control Data + 1] / Freq) Valid Valid reg<1575:1568> LUT3_10 <7:0> or DLY/CNT4 Control Data 1 - 255 (Delay Time = [Counter Control Data + 1] / Freq) Valid Valid reg<1577:1576> ReservedReserved Valid Invalid reg<1579:1578> Reserved Reserved Reserved Valid Invalid reg<1581:1580> Reserved Reserved Valid Invalid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 179 of 193 SLG46580/82/83 Preliminary reg<1583:1582> Reserved Reserved Reserved Valid Invalid reg<1584> UVLO1_HW_enable (Enable UVLO1 output Hard-Wire connection to LDO2/3) (for SLG46580) UVLO1_HW_enable (Enable UVLO1 output Hard-Wire connection to LDO1) (for SLG46582) UVLO_HW_enable1 (Enable UVLO output from ACMP1 Hard-Wire connection to LDO) (for SLG46583) 0: Disable UVLO1 HW connect (for SLG46580 and SLG46582) 1: Enable UVLO1 HW connect (for SLG46580 and SLG46582) 0: Disable UVLO HW connect (for SLG46583) 1: Enable UVLO HW connect (for SLG46583) Valid Valid reg<1585> UVLO0_HW_enable (Enable UVLO0 output Hard-Wire connection to LDO0/1) (for SLG46580) UVLO0_HW_enable (Enable UVLO0 output Hard-Wire connection to LDO0) (for SLG46582) UVLO_HW_enable0 (Enable UVLO output from ACMP0 Hard-Wire connection to LDO) (for SLG46583) 0: Disable UVLO0 HW connect (for SLG46580 and SLG46582) 1: Enable UVLO0 HW connect (for SLG46580 and SLG46582) 0: Disable UVLO HW connect (for SLG46583) 1: Enable UVLO HW connect (for SLG46583) Valid Valid reg<1588:1586> LDO0/1 VDD minimum Power Selection for LDO1 (for SLG46580) Reserved (for SLG46582 and SLG46583) 000: 2.3 V (for SLG46580) 001: 2.8 V (for SLG46580) 010: 3.0 V (for SLG46580) 011: 3.3 V (for SLG46580) 100: 3.6 V (for SLG46580) 101: 3.9 V (for SLG46580) 110: 4.3 V (for SLG46580) 111: 4.65 V (for SLG46580) Valid Valid reg<1591:1589> LDO0/1 VDD minimum Power Selection for LDO0 (for SLG46580) LDO0 VDD minimum Power Selection for LDO0 (for SLG46582) LDO VDD minimum Power Selection for LDO (for SLG46583) 000: 2.3 V 001: 2.8 V 010: 3.0 V 011: 3.3 V 100: 3.6 V 101: 3.9 V 110: 4.3 V 111: 4.65 V Valid Valid reg<1592> LDO0 Start-up Ramping Slope Selection (for SLG46580 and SLG46582) LDO Start-up Ramping Slope Selection (for SLG46583) 0: 10 V/ms 1: 20 V/ms Valid Valid reg<1594:1593> Reserved Valid Valid reg<1599:1595> LDO0 Vref Selection (for SLG46580 and for SLG46582) LDO Vref Selection (for SLG46583) 00000:0.90v, 00001:1.00v, 00010:1.05v, 00011:1.10v, 00100:1.20v, 00101:1.25v, 00110:1.35v, 00111:1.50v, 01000:1.67v, 01001:1.80v, 01010:1.90v, 01011:2.00v, 01100:2.10v, 01101:2.20v, 01110:2.30v, 01111:2.40v, 10000:2.50v, 10001:2.60v, 10010:2.70v, 10011:2.80v, 10100:2.90v, 10101:3.00v, 10110:3.10v, 10111:3.20v, 11000:3.30v, 11001:3.40v, 11010:3.50v, 11011:3.60v, 11100:3.70v, 11101:4.00v, 11110:4.30v, 11111:4.35v Valid Valid reg<1600> LDO1 Start-up Ramping Slope Selection (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: 10 V/ms (for SLG46580) 1: 20 V/ms (for SLG46580) Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 180 of 193 SLG46580/82/83 Preliminary reg<1602:1601> Reserved (for LDO1 OI selection) (for Reserved Valid Valid reg<1607:1603> LDO1 Vref Selection (for SLG46580) Reserved (for SLG46582 and SLG46583) 00000:0.90v, 00001:1.00v, 00010:1.05v, 00011:1.10v, 00100:1.20v, 00101:1.25v, 00110:1.35v, 00111:1.50v, 01000:1.67v, 01001:1.80v, 01010:1.90v, 01011:2.00v, 01100:2.10v, 01101:2.20v, 01110:2.30v, 01111:2.40v, 10000:2.50v, 10001:2.60v, 10010:2.70v, 10011:2.80v, 10100:2.90v, 10101:3.00v, 10110:3.10v, 10111:3.20v, 11000:3.30v, 11001:3.40v, 11010:3.50v, 11011:3.60v, 11100:3.70v, 11101:4.00v, 11110:4.30v, 11111:4.35v Valid Valid reg<1608> LDO2 Start-up Ramping Slope Selection (for SLG46580) LDO1 Start-up Ramping Slope Selection (for SLG46582) Reserved (for SLG46583) 0: 10 V/ms (for SLG46580) 1: 20 V/ms (for SLG46580) Valid Valid reg<1610:1609> Reserved Valid Valid reg<1615:1611> LDO2 Vref Selection (for SLG46580) LDO1 Vref Selection (for SLG46582) Reserved (for SLG46583) 00000:0.90v, 00001:1.00v, 00010:1.05v, 00011:1.10v, 00100:1.20v, 00101:1.25v, 00110:1.35v, 00111:1.50v, 01000:1.67v, 01001:1.80v, 01010:1.90v, 01011:2.00v, 01100:2.10v, 01101:2.20v, 01110:2.30v, 01111:2.40v, 10000:2.50v, 10001:2.60v, 10010:2.70v, 10011:2.80v, 10100:2.90v, 10101:3.00v, 10110:3.10v, 10111:3.20v, 11000:3.30v, 11001:3.40v, 11010:3.50v, 11011:3.60v, 11100:3.70v, 11101:4.00v, 11110:4.30v, 11111:4.35v Valid Valid reg<1616> LDO3 Start-up Ramping Slope Selection (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: 10 V/ms (for SLG46580) 1: 20 V/ms (for SLG46580) Valid Valid reg<1618:1617> Reserved (for LDO3 OI selection) (for Reserved Valid Valid reg<1623:1619> LDO3 Vref Selection (for SLG46580) Reserved (for SLG46582 and SLG46583) 00000:0.90v, 00001:1.00v, 00010:1.05v, 00011:1.10v, 00100:1.20v, 00101:1.25v, 00110:1.35v, 00111:1.50v, 01000:1.67v, 01001:1.80v, 01010:1.90v, 01011:2.00v, 01100:2.10v, 01101:2.20v, 01110:2.30v, 01111:2.40v, 10000:2.50v, 10001:2.60v, 10010:2.70v, 10011:2.80v, 10100:2.90v, 10101:3.00v, 10110:3.10v, 10111:3.20v, 11000:3.30v, 11001:3.40v, 11010:3.50v, 11011:3.60v, 11100:3.70v, 11101:4.00v, 11110:4.30v, 11111:4.35v Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 181 of 193 SLG46580/82/83 Preliminary ACMP0 reg<1628:1624> ACMP0- IN Voltage Select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD: ACMP0- /3 11001: VDD: ACMP0- /4 11010: IO6: EXT_VREF 11011: IO6: EXT_VREF /2 Valid Valid reg<1630:1629> ACMP0 Positive Input Divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X Valid Valid reg<1631> ACMP0 Low Bandwidth (MAX: 1MHz) En- a b l e 0: OFF 1:ON Valid Valid ACMP1 reg<1636:1632> ACMP1-IN Voltage Select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD: ACMP1- /3 11001: VDD: ACMP1- /4 11010: IO6: EXT_VREF 11011: IO6: EXT_VREF /2 Valid Valid reg<1638:1637> ACMP1 Positive Input Divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X Valid Valid reg<1639> ACMP1 Low Bandwidth (MAX: 1MHz) En- a b l e 0: OFF 1: ON Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 182 of 193 SLG46580/82/83 Preliminary ACMP2 reg<1644:1640> ACMP2-IN Voltage Select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD: ACMP2- /3 11001: VDD: ACMP2- /4 11010: IO6: EXT_VREF 11011: IO6: EXT_VREF /2 Valid Valid reg<1646:1645> ACMP2 Positive Input Divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X Valid Valid reg<1647> ACMP2 Low Bandwidth (MAX: 1MHz) En- a b l e 0: OFF 1: ON Valid Valid ACMP3 reg<1652:1648> ACMP3-IN Voltage Select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD: ACMP3- /3 11001: VDD: ACMP3- /4 11010: IO6: EXT_VREF 11011: IO6: EXT_VREF /2 Valid Valid reg<1654:1653> ACMP3 Positive Input Divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X Valid Valid reg<1655> ACMP3 Low Bandwidth (MAX: 1MHz) En- a b l e 0: OFF 1: ON Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 183 of 193 SLG46580/82/83 Preliminary Misc. reg<1656> TS_HW_enable (Enable Temp sensor out- put Hard-Wire connection to LDO0/1/2/3) (for SLG46580) TS_HW_enable (Enable Temp sensor out- put Hard-Wire connection to LDO0/1) (for SLG46582) TS_HW_enable (Enable Temp sensor out- put Hard-Wire connection to LDO) (for SLG46583) 0: Disable TS HW connect 1: Enable TS HW connect Valid Valid reg<1657> Switch from “Matrix OUT: LPOSC PD” to “Matrix OUT: LPOSC Force On” 0: OSC PD 1: OSC Force On (Matrix Output <60>) Valid Valid reg<1658> Switch from “Matrix OUT: OSC 25KHz/2MHz PD” to “Matrix OUT: OSC 25KHz/2MHz Force On” 0: OSC PD 1: OSC Force On (Matrix Output <59>) Valid Valid reg<1659> Reserved Valid Invalid reg<1660> Reserved Valid Invalid reg<1661> Reserved Valid Invalid reg<1662> I2C reset bit with reloading NVM into Data register 0: Keep existing condition 1: Reset execution Valid Valid reg<1663> IO Latching Enable During I2C Write Inter- face 0: Disable 1: Enable Valid Invalid reg<1671:1664> RAM 8 outputs for ASM-state0 Valid Valid reg<1679:1672> RAM 8 outputs for ASM-state1 Valid Valid reg<1687:1680> RAM 8 outputs for ASM-state2 Valid Valid reg<1695:1688> RAM 8 outputs for ASM-state3 Valid Valid reg<1703:1696> RAM 8 outputs for ASM-state4 Valid Valid reg<1711:1704> RAM 8 outputs for ASM-state5 Valid Valid reg<1719:1712> RAM 8 outputs for ASM-state6 Valid Valid reg<1727:1720> RAM 8 outputs for ASM-state7 Valid Valid reg<1735:1728> User configurable RAM / OTP Byte 0 Valid Valid reg<1743:1736> User configurable RAM / OTP Byte 1 Valid Valid reg<1751:1744> User configurable RAM / OTP Byte 2 Valid Valid reg<1759:1752> User configurable RAM / OTP Byte 3 Valid Valid reg<1767:1760> User configurable RAM / OTP Byte 4 Valid Valid reg<1775:1768> User configurable RAM / OTP Byte 5 Valid Valid reg<1783:1776> User configurable RAM / OTP Byte 6 Valid Valid reg<1791:1784> User configurable RAM / OTP Byte 7 Valid Valid reg<1792> LDO0_EN_Gate (By this bit=1, Matrix Out- put: LDO0_EN will be enabled.) (for SLG46580 and SLG46582) LDO_EN_Gate (By this bit=1, Matrix Output: LDO_EN will be enabled.) (for SLG46583) 0: Disable 1: Enable Valid Valid reg<1793> LDO0 VOUT_SEL_Gate (for SLG46580 and SLG46582) LDO VOUT_SEL_Gate (for SLG46583) 0: Default VOUT selection 1: Enable 2nd VOUT selection Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 184 of 193 SLG46580/82/83 Preliminary reg<1794> Mode1_EN_Gate (By this bit=1, Matrix Out- put: LDO MODE1_Enable for LDO0/1/2/3 will be enabled.) (for SLG46580) Mode1_EN_Gate (By this bit=1, Matrix Out- put: LDO MODE1_Enable for LDO0/1 will be enabled.) (for SLG46582) Mode1_EN_Gate (By this bit=1, Matrix Out- put: LDO MODE1_Enable for LDO will be enabled.) (for SLG46583) 0: Disable LDO_LP_MODE_EN matrix out- put (for SLG46580) 1: Enable LDO_LP_MODE_ matrix output (for SLG46580) 0: Disable (for SLG46582 and SLG46583) 1: Enable (for SLG46582 and SLG46583) Valid Valid reg<1799:1795> LDO0 2nd Vref Selection (for SLG46580 and SLG46582) LDO 2nd Vref Selection (for SLG46583) 00000:0.90v, 00001:1.00v, 00010:1.05v, 00011:1.10v, 00100:1.20v, 00101:1.25v, 00110:1.35v, 00111:1.50v, 01000:1.67v, 01001:1.80v, 01010:1.90v, 01011:2.00v, 01100:2.10v, 01101:2.20v, 01110:2.30v, 01111:2.40v, 10000:2.50v, 10001:2.60v, 10010:2.70v, 10011:2.80v, 10100:2.90v, 10101:3.00v, 10110:3.10v, 10111:3.20v, 11000:3.30v, 11001:3.40v, 11010:3.50v, 11011:3.60v, 11100:3.70v, 11101:4.00v, 11110:4.30v, 11111:4.35v Valid Valid reg<1800> LDO1_EN_Gate (By this bit=1, Matrix Out- put: LDO1_EN will be enabled.) (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: Disable (for SLG46580) 1: Enable (for SLG46580) Valid Valid reg<1801> LDO1 VOUT_SEL_Gate (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: Default VOUT selection (for SLG46580) 1: Enable 2nd VOUT selection (for SLG46580) Valid Valid reg<1802> Reserved Valid Valid reg<1807:1803> LDO1 2nd Vref Selection (for SLG46580) Reserved (for SLG46582 and SLG46583) 00000:0.90v, 00001:1.00v, 00010:1.05v, 00011:1.10v, 00100:1.20v, 00101:1.25v, 00110:1.35v, 00111:1.50v, 01000:1.67v, 01001:1.80v, 01010:1.90v, 01011:2.00v, 01100:2.10v, 01101:2.20v, 01110:2.30v, 01111:2.40v, 10000:2.50v, 10001:2.60v, 10010:2.70v, 10011:2.80v, 10100:2.90v, 10101:3.00v, 10110:3.10v, 10111:3.20v, 11000:3.30v, 11001:3.40v, 11010:3.50v, 11011:3.60v, 11100:3.70v, 11101:4.00v, 11110:4.30v, 11111:4.35v Valid Valid reg<1808> LDO2_EN_Gate (By this bit=1, Matrix Out- put: LDO2_EN will be enabled.) (for SLG46580) LDO1_EN_Gate (By this bit=1, Matrix Out- put: LDO1_EN will be enabled.) (for SLG46582) Reserved (for SLG46583) 0: Disable (for SLG46580) 1: Enable (for SLG46580) 0: Disable LDO1_EN matrix output (for SLG46582) 1: Enable LDO1_EN matrix output (for SLG46582) Valid Valid reg<1809> LDO2 VOUT_SEL_Gate (for SLG46580) LDO1 VOUT_SEL_Gate (for SLG46582) Reserved (for SLG46583) 0: Default VOUT selection 1: Enable 2nd VOUT selection Valid Valid reg<1810> Reserved Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 185 of 193 SLG46580/82/83 Preliminary reg<1815:1811> LDO2 2nd Vref Selection (for SLG46580) LDO1 2nd Vref Selection (for SLG46582) Reserved (for SLG46583) 00000:0.90v, 00001:1.00v, 00010:1.05v, 00011:1.10v, 00100:1.20v, 00101:1.25v, 00110:1.35v, 00111:1.50v, 01000:1.67v, 01001:1.80v, 01010:1.90v, 01011:2.00v, 01100:2.10v, 01101:2.20v, 01110:2.30v, 01111:2.40v, 10000:2.50v, 10001:2.60v, 10010:2.70v, 10011:2.80v, 10100:2.90v, 10101:3.00v, 10110:3.10v, 10111:3.20v, 11000:3.30v, 11001:3.40v, 11010:3.50v, 11011:3.60v, 11100:3.70v, 11101:4.00v, 11110:4.30v, 11111:4.35v Valid Valid reg<1816> LDO3_EN_Gate (By this bit=1, Matrix Out- put: LDO3_EN will be enabled.) (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: Disable (for SLG46580) 1: Enable (for SLG46580) Valid Valid reg<1817> LDO3 VOUT_SEL_Gate (for SLG46580) Reserved (for SLG46582 and SLG46583) 0: Default VOUT selection (for SLG46580) 1: Enable 2nd VOUT selection (for SLG46580) Valid Valid reg<1818> Reserved Valid Valid reg<1823:1819> LDO3 2nd Vref Selection (for SLG46580) Reserved (for SLG46582 and SLG46583) 00000:0.90v, 00001:1.00v, 00010:1.05v, 00011:1.10v, 00100:1.20v, 00101:1.25v, 00110:1.35v, 00111:1.50v, 01000:1.67v, 01001:1.80v, 01010:1.90v, 01011:2.00v, 01100:2.10v, 01101:2.20v, 01110:2.30v, 01111:2.40v, 10000:2.50v, 10001:2.60v, 10010:2.70v, 10011:2.80v, 10100:2.90v, 10101:3.00v, 10110:3.10v, 10111:3.20v, 11000:3.30v, 11001:3.40v, 11010:3.50v, 11011:3.60v, 11100:3.70v, 11101:4.00v, 11110:4.30v, 11111:4.35v Valid Valid reg<1831:1824> Reserved Valid Valid reg<1832> NVM Data Read Disable (From NVM): ID[24] for BANK0/1/2 only 0: Disable (Programmed data can be read.) 1: Enable (Programmed data can't be read.) Valid Invalid reg<1833> Reserved Reserved Valid Invalid reg<1835:1834> Reserved Reserved Valid Invalid reg<1839:1836> Reserved Reserved Valid Invalid reg<1847:1840> 8-bit Pattern ID Byte 0 (From NVM): ID[23:16] Valid Valid reg<1855:1848> Reserved Reserved Valid Invalid reg<1863:1856> Reserved Reserved Valid Invalid reg<1867:1864> I 2C Control Code Bit [3:0] Value for slave address Valid Invalid reg<1868> I 2C 1MHz operation enable 0: Up to 400 kHz 1: 1 MHz operation Valid Invalid reg<1869> Reserved Valid Invalid reg<1870> BANK0/1/2/3 I 2C-write protection bit 0: Writable 1: Non-writable Valid Invalid reg<1871> BANK0/1/2 I 2C-write protection bit 0: Writable 1: Non-writable Valid Invalid reg<1872> Reserved Invalid Invalid reg<1874:1873> Reserved Invalid Invalid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 186 of 193 SLG46580/82/83 Preliminary reg<1876:1875> Reserved Invalid Invalid reg<1879:1877> Reserved Invalid Invalid reg<1880> Reserved Invalid Invalid reg<1881> Reserved Invalid Invalid reg<1882> Reserved Invalid Invalid reg<1887:1883> Reserved Invalid Invalid reg<1891:1888> Reserved Invalid Invalid reg<1895:1892> Reserved Invalid Invalid reg<1899:1896> Reserved Invalid Invalid reg<1903:1900> Reserved Invalid Invalid reg<1904> Reserved Invalid Invalid reg<1905> Reserved Invalid Invalid reg<1907:1906> Reserved Invalid Invalid reg<1911:1908> Reserved Invalid Invalid reg<1919:1912> ASM State output <7:0> Invalid Invalid Matrix Input reg<1920> Matrix Input 0 GND Valid Invalid reg<1921> Matrix Input 1 IO0 D igital Input Valid Invalid reg<1922> Matrix Input 2 IO1 D igital Input Valid Invalid reg<1923> Matrix Input 3 IO2 D igital Input Valid Invalid reg<1924> Matrix Input 4 IO3 Digital Input Valid Invalid reg<1925> Matrix Input 5 IO4 D igital Input Valid Invalid reg<1926> Matrix Input 6 LUT2_ 0 / DFF0 Output Valid Invalid reg<1927> Matrix Input 7 LUT2_ 1 / DFF1 Output Valid Invalid reg<1928> Matrix Input 8 LUT2_ 2 / DFF2 Output Valid Invalid reg<1929> Matrix Input 9 LUT3_ 0 / DFF3 Output Valid Invalid reg<1930> Matrix Input 10 LUT3_1 / DFF4 Output Valid Invalid reg<1931> Matrix Input 11 LUT3_2 / DFF5 Output Valid Invalid reg<1932> Matrix Input 12 LUT3_3 / DFF6 Output Valid Invalid reg<1933> Matrix Input 13 LUT3_4 / DFF7 Output Valid Invalid reg<1934> Matrix Input 14 LUT3_6 / CNT_DLY0(8bit) Output Valid Inva lid reg<1935> Matrix Input 15 LUT3_7 / CNT_DLY1(8bit) Output Valid Inva lid reg<1936> Matrix Input 16 LUT3_8 / CNT_DLY2(8bit) Output Valid Inva lid reg<1937> Matrix Input 17 LUT3_9 / CNT_DLY3(8bit) Output Valid Inva lid reg<1938> Matrix Input 18 LUT3_10 / CNT_DLY4(8bit) Output Valid Inv alid reg<1939> Matrix Input 19 LUT3_11 / Pipe Delay (1st stage) Output / Ripple counter Q<0> Valid Invalid reg<1940> Matrix Input 20 LUT3_5 / DFF8 Output Valid Invalid reg<1941> Matrix Input 21 LU T4X2 Output0 Valid Invalid reg<1942> Matrix Input 22 LU T4X2 Output1 Valid Invalid reg<1943> Matrix Input 23 RTC CNT 1 second Output Valid Invalid reg<1944> Matrix Input 24 RTC DCOMP Output Valid Invalid reg<1945> Matrix Input 25 Pipe Del ay Output0 / Ripple counter Q<1> Valid Invalid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 187 of 193 SLG46580/82/83 Preliminary reg<1946> Matrix Input 26 Pipe Del ay Output1 / Ripple counter Q<2> Valid Invalid reg<1947> Matrix Input 27 Internal OSC Post-Divided by 1/2/3/4/8/12/24/64 Output (25KHz/2MHz) Valid Invalid reg<1948> Matrix Input 28 Internal OSC Post-Divided by 1/2/3/4/8/12/24/64 Output (25KHz/2MHz) Valid Invalid reg<1949> Matrix Input 29 LPOSC Output Valid Invalid reg<1950> Matrix Input 30 Filter0 / Edge Detect0 Output Valid Inva lid reg<1951> Matrix Input 31 Filter1 / Edge Detect1 Output Valid Inva lid reg<1952> Matrix Input 32 I2C_virtual_0 Input Valid Valid reg<1953> Matrix Input 33 I2C_virtual_1 Input Valid Valid reg<1954> Matrix Input 34 I2C_virtual_2 Input Valid Valid reg<1955> Matrix Input 35 I2C_virtual_3 Input Valid Valid reg<1956> Matrix Input 36 I2C_virtual_4 Input Valid Valid reg<1957> Matrix Input 37 I2C_virtual_5 Input Valid Valid reg<1958> Matrix Input 38 I2C_virtual_6 Input Valid Valid reg<1959> Matrix Input 39 I2C_virtual_7 Input Valid Valid reg<1960> Matrix Input 40 RAM_0 Ou tput for ASM-state Valid Invalid reg<1961> Matrix Input 41 RAM_1 Ou tput for ASM-state Valid Invalid reg<1962> Matrix Input 42 RAM_2 Ou tput for ASM-state Valid Invalid reg<1963> Matrix Input 43 RAM_3 Ou tput for ASM-state Valid Invalid reg<1964> Matrix Input 44 RAM_4 Ou tput for ASM-state Valid Invalid reg<1965> Matrix Input 45 RAM_5 Ou tput for ASM-state Valid Invalid reg<1966> Matrix Input 46 RAM_6 Ou tput for ASM-state Valid Invalid reg<1967> Matrix Input 47 RAM_7 Ou tput for ASM-state Valid Invalid reg<1968> Matrix Input 48 Valid Invalid reg<1969> Matrix Input 49 LDO0 FAULTB (for SLG46580 and SLG46582) LDO FAULTB (for SLG46583) Valid Invalid reg<1970> Matrix Input 50 LDO1 FAULTB (for SLG46580) GND (for SLG46582 and SLG46583) Valid Invalid reg<1971> Matrix Input 51 LDO2 FAULTB (for SLG46580) LDO1 FAULTB (for SLG46582) GND (for SLG46583) Valid Invalid reg<1972> Matrix Input 52 LDO3 FAULTB (for SLG46580) GND (for SLG46582 and SLG46583) Valid Invalid reg<1973> Matrix Input 53 IO5 Digi tal Input (GPI) Valid Invalid reg<1974> Matrix Input 54 IO6 Digital Input Valid Invalid reg<1975> Matrix Input 55 IO7 Digital Input Valid Invalid reg<1976> Matrix Input 56 IO8 Digital Input Valid Invalid reg<1977> Matrix Input 57 AC MP_0 Output Valid Invalid reg<1978> Matrix Input 58 AC MP_1 Output Valid Invalid reg<1979> Matrix Input 59 AC MP_2 Output Valid Invalid reg<1980> Matrix Input 60 AC MP_3 Output Valid Invalid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write

SLG46580/82/83_DS_062 Page 188 of 193 SLG46580/82/83 Preliminary 25.1 STQFN 20L 2x3mm 0.4P FCD Package reg<1981> Matrix Input 61 Programmable Delay with Edge Detector Output Valid Invalid reg<1982> Matrix Input 62 nRST_cor e as matrix input Valid Invalid reg<1983> Matrix Input 63 VDD Valid Invalid Reserved reg<1991:1984> Reserved Valid Invalid reg<1999:1992> Reserved Valid Invalid reg<2007:2000> Reserved Valid Invalid reg<2015:2008> Reserved Valid Valid reg<2023:2016> Reserved Valid Invalid reg<2031:2024> Valid Invalid reg<2032> Reserved Valid Valid reg<2033> Valid Valid reg<2034> Reserved Valid Valid reg<2035> Reserved Reserved Reserved Valid Invalid reg<:2039:2036> Reserved Valid Valid reg<2047:2040> Reserved Valid Valid Register Bit Address Signal Function Register Bit Definition I2C Interface I2C Read I2C Write Part Code Datecode Lot Revision – Part ID Field: identifies the specific device configuration – Date Code Field: Coded date of manufacture – Lot Code: Designates Lot # – Assembly Site/COO: Specifies Assembly Site/Country of Origin – Revision Code: Device Revision XXXXX DD LLL C RR COO

SLG46580/82/83_DS_062 Page 189 of 193 SLG46580/82/83 Preliminary

26.0 Package Drawing and Dimensions

26.1 STQFN 20L 2x3mm 0.4P FCD Package JEDEC MO-220, Variation WECE IC Net Weight: TBD g

SLG46580/82/83_DS_062 Page 190 of 193 SLG46580/82/83 Preliminary

27.0 Tape and Reel Specifications

27.1 Carrier Tape Drawing and Dimensions

# of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm]per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 20L 2x3 mm 0.4P FCD 20 2 x 3 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W STQFN 20L 2x3 mm 0.4P FCD Refer to EIA-481 specification

SLG46580/82/83_DS_062 Page 191 of 193 SLG46580/82/83 Preliminary

28.0 Recommended Land Pattern

28.1 STQFN 20L 2x3mm 0.4P FCD Package Note 1: Pins 11 and 13 must be shorted externally, Pins 14 and 16 must be shorted externally for SLG46582. Note 2: Pins 12 and 15 must be shorted externally, Pins 11, 13, 14 and 16 must be shorted externally for SLG46583.

29.0 Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow prof ile based on package volume of 3.30 mm 3 (nominal). More information can be found at www.jedec.org.

SLG46580/82/83_DS_062 Page 192 of 193 SLG46580/82/83 Preliminary

30.0 Revision History

11/17/2017 0.62 Updated ACMP Positive Input Range General Review Updated Section Analog Comparator Updated Appendix A Updated Sections Low Dropout Regulators 11/7/2017 0.61 Updated Sections Low Dropout Regulators Updated front page Package Drawing Updated Section Analog Temperature Sensor Updated Electrical Spec Relocated tables Typical Delay Estimated for Each Macrocell, Programmable Delay Expected Delays and Widths (typical), Typical Pulse Width Performance 10/13/2017 0.60 Added Typical Application circuit in LDO section Updated Electrical Spec Updated I2C Specifications Added OSC Power On delay 9/7/2017 0.59 Updated Section Combination Function Macrocells Updated Electrical Spec 8/9/2017 0.58 Added exte rnal reset description 7/24/2017 0.57 Updated Or dering Information 7/20/2017 0.56 Updated Electrical Spec 7/19/2017 0.55 Change d LDO node naming 7/18/2017 0.54 Updated according to KDC 7/12/2017 0.53 Updated LDO Information 7/6/2017 0.52 Updated tables LDO HP MODE Electrical Specifications and Updated Absolute Maximum Conditions 7/3/2017 0.51 Updated Electrical Characteristics Updated Analog Temperature Sensor Fixed typos Updated LDO Current Consumption 6/7/2017 0.50 Fixed quality of Initial Polarity Operations diagrams Preliminary release

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