SLG46400

SLG46400 DIALOG

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 95

Technical content

Features

• Logic & Mixed Signal Circuits
• Highly Versatile Macro Cells
• Read Back Protection (Read Lock)
• 1.8V (±5%) to 5V (±10%) Supply
• Operating Temperature Range: -40°C to 85°C
• RoHS Compliant / Halogen-Free
• Pb-Free TDFN-12 2.5mm x 2.5mm Package

Applications

• Personal Computers and Servers
• PC Peripherals
• Consumer Electronics
• Data Communications Equipment
• Handheld and Portable Electronics Pin Configuration GPIO GPIO GPIO GPIO GPIO GPIO 4 9 GPI VDD 1 Thermal Pad connected to GNDTDFN-12 (Top View) GPIO GPIO 5

6 GND

Ext_Vref_in Int_Vref_out

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1.0 Overview

The SLG46400 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macro cells of the SLG46400. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The macro cells in the device include the following:

• 8-Bit Successive Approximation Register Analog to Digital Converter (SAR ADC)
• Power-On Reset Device (POR)
• Voltage Reference (V REF)
• RC Oscillator (RC OSC)
• 4 Counter/Delay Generators (CNT/DLY)
• 4 D Flip-Flop/Latches (DFF)
• 3 Digital Comparators (DCMP) or Pulse Width Modulator (PWM)
• 2 Analog Comparators (ACMP)
• 11 Combinatorial Look-Up Tables (LUT)
• Slave SPI
• Configurable I/O Pins (Open Drain, Push-Pull, Schmitt Trigger Input, Low Voltage Digital Input and Analog I/O)
• Delay (20ns/40ns/60ns/80ns)
• Pipe Delay The specific functions that can be designed using the SLG46400 include:
• Power-On-Rese t Generators
• Signal Delay Elements
• One-Shot Detection
• Voltage Level Detectors
• Voltage Level-Shift Circuits
• Battery Charge Controller
• LED Lighting Control
• Fan Controller
• Optical Encoder
• Level Shifters
• Hall Effect Driver
• Signal De-Glitches The PWM and ADC macro cells also support more complex control circuits such as fan speed controllers, stepper motor control- lers and interface to a wide variety of sensor devices. Traditi onally these devices were designed from combinations of low complexity logic and discrete devices requiring costly board space while having complex testing strategies. Silego’s SLG46400 allows the functionality of these circuits to be fully tested before being mounted onto a PCB – greatly simplifying the system design and testing procedures.

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2.0 Pin Description

2.1 Functional Pin Description

2.2 Programming Pin Description

Pin # Pin Name Function 1 VDD 1.8V to 5V Supply

2 GPI General Input

3 GPIO General IO or Analog Comparator 0 Input

4 GPIO General IO or Analog Comparator 1 Input

5 GPIO General IO or External Clock of OSC, ADC, and S2P

6G P I O General IO or Serial Output Data of ADC and Serial Input/Output Data of S2P 7G N D G N D

8 GPIO General IO or Positive Input of ADC

9 GPIO General IO or Negative Input of ADC

10 GPIO General IO or V

11 GPIO General IO or V REF Input

12 GPIO General IO or Single-ended Mode ADC Input Selection

Pin # Pin Name Programming Description 1V D D V D D

2 GPI VPP

8 GPIO Program Mode Control

10 GPIO NVM Read Mode Output Data

11 GPIO NVM Write Mode Input Data

12 GPIO NVM Clock

3.0 User Programmability

code (.gp2 file) is forwarded to Silego to integrate into a production process. Figure 1. Steps to create a custom Silego GreenPAK device

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4.0 Ordering Information

SLG46400VTR TDFN-12 - Tape and Reel (3k units)

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5.0 Electrical Specifications

5.1 Absolute Maximum Conditions

5.2 Electrical Characteristics (1.8V ±5% VDD) Parameter Min. Max. Unit VHIGH to GND -0.3 7 V Voltage at Input Pin -0.3 7 V Current at Input Pin -1.0 1.0 mA Storage Temperature Range -65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 6000 -- V ESD Protection (Charged Device Model) 1300 -- V Moisture Sensitivity Level 1 Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 1.71 1.8 1.89 V IQ Quiescent Current Static Inputs and Outputs -- -- 1 μA TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.5 7.75 V VAIR Analog Input Voltage Range ADC VREF 0- - 1 . 0 V ACMP Negative Input 0 -- 1.0 V VIH HIGH-Level Input Voltage Logic Input 1.1 -- -- V Logic Input with Schmitt Trigger 1.35 -- -- V LOW-Level Logic Input 1.1 -- -- V V IL LOW-Level Input Voltage Logic Input -- -- 0.65 V Logic Input with Schmitt Trigger -- -- 0.45 V LOW-Level Logic Input -- -- 0.50 V I IH HIGH-Level Input Current Logic Input Pins; V IN=1.8V -1.0 -- 1.0 μA IIL LOW-Level Input Current Logic Input Pins; V IN=0V -1.0 -- 1.0 μA VOH HIGH-Level Output Voltage Push-Pull, IOH = 100μA, 1X Drive 1.66 -- -- V Push-Pull, IOH = 700μA, 1X Drive 1.21 -- -- V Push-Pull, IOH = 1mA, 2X Drive 1.42 -- -- V Push-Pull, IOH = 100μA, 2X Drive 1.68 -- -- V Push-Pull, IOH = 700μA, 2X Drive 1.53 -- -- V VOL LOW-Level Output Voltage Push-Pull, IOL= 100μA, 1X Drive -- -- 0.040 V Push-Pull, IOL = 700μA, 1X Drive -- -- 0.415 V Push-Pull, IOL = 1mA, 2X Drive -- -- 0.245 V Push-Pull, IOL = 100μA, 2X Drive -- -- 0.020 V Push-Pull, IOL = 700μA, 2X Drive -- -- 0.155 V Open Drain, IOL = 5mA, 1X Drive -- -- 0.340 V Open Drain, IOL = 5mA, 2X Drive -- -- 0.138 V

000-0046400-109 Page 6 of 89 SLG46400 1. If startup time lower than 7 ms is required, please contact Silego regarding a potential custom mixed-signal IC with a reduced startup time for your design. IOL LOW-Level Output Current Push-Pull, VOL = 0.15V, 1X Drive 0.34 -- -- mA Push-Pull, VOL = 0.15V, 2X Drive 0.68 -- -- mA Open Drain, VOL = 0.15V, 1X Drive 2.72 -- -- mA Open Drain, VOL = 0.15V, 2X Drive 5.44 -- -- mA TSU Startup Time After VDD reaches 1.4-1.6V level -- 7 1 -- ms Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046400-109 Page 7 of 89 SLG46400 5.3 Electrical Characteristics (3.3V ±10% VDD) 1. If startup time lower than 7 ms is required, please contact Silego regarding a potential custom mixed-signal IC with a reduced startup time for your design. Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3.0 3.3 3.6 V IQ Quiescent Current Static Inputs and Outputs -- -- 1 μA TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.5 7.75 V VAIR Analog Input Voltage Range ADC 0 -- 1.0 V ACMP 0 -- 1.5 V VIH HIGH-Level Input Voltage Logic Input 1.8 -- -- V Logic Input with Schmitt Trigger 2.3 -- -- V LOW-Level Logic Input 1.5 -- -- V V IL LOW-Level Input Voltage Logic Input -- -- 1.10 V Logic Input with Schmitt Trigger -- -- 0.92 V LOW-Level Logic Input -- -- 0.66 V I IH HIGH-Level Input Current Logic Input Pins; V IN=3.3V -1.0 -- 1.0 μA IIL LOW-Level Input Current Logic Input Pins; V IN=0V -1.0 -- 1.0 μA VOH HIGH-Level Output Voltage Push-Pull, IOH = 3mA, 1X Drive 2.1 -- -- V Push-Pull, IOH = 3mA, 2X Drive 2.6 -- -- V VOL LOW-Level Output Voltage Push-Pull, IOL = 3mA, 1X Drive -- -- 0.81 V Push-Pull, IOL = 3mA, 2X Drive -- -- 0.32 V Open Drain, IOL = 20mA, 1X Drive -- -- 0.605 V Open Drain, IOL = 20mA, 2X Drive -- -- 0.252 V IOL LOW-Level Output Current Push-Pull, VOL = 0.4V, 1X Drive 1.836 -- -- mA Push-Pull, VOL = 0.4V, 2X Drive 3.672 -- -- mA Open Drain, VOL = 0.4V, 1X Drive 14.688 -- -- mA Open Drain, VOL = 0.4V, 2X Drive 29.376 -- -- mA TSU Startup Time After VDD reaches 1.4-1.6V level -- 7 1 -- ms

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5.4 Electrical Characteristics (5V ±10% VDD)

1. If startup time lower than 7 ms is required, please contact Silego regarding a potential custom mixed-signal IC with a reduced startup time for your design. Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 4.5 5 5.5 V IQ Quiescent Current Static Inputs and Outputs -- -- 1 μA TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.5 7.75 V VAIR Analog Input Voltage Range ADC 0 -- 1.0 V ACMP 0 -- 1.5 V VIH HIGH-Level Input Voltage Logic Input 2.6 -- -- V Logic Input with Schmitt Trigger 3.2 -- -- V LOW-Level Logic Input 1.7 -- -- V V IL LOW-Level Input Voltage Logic Input -- -- 1.7 V Logic Input with Schmitt Trigger -- -- 1.3 V LOW-Level Logic Input -- -- 0.77 V I IH HIGH-Level Input Current Logic Input Pins; V IN=5V -1.0 -- 1.0 μA IIL LOW-Level Input Current Logic Input Pins; V IN=0V -1.0 -- 1.0 μA VOH HIGH-Level Output Voltage Push-Pull, IOH = 5mA, 1X Drive 3.6 -- -- V Push-Pull, IOH = 8mA, 1X Drive 2.9 -- -- V Push-Pull, IOH = 5mA, 2X Drive 4.1 -- -- V Push-Pull, IOH = 8mA, 2X Drive 3.8 -- -- V VOL LOW-Level Output Voltage Push-Pull, IOL = 5mA, 1X Drive -- -- 0.85 V Push-Pull, IOL = 8mA, 1X Drive -- -- 1.20 V Push-Pull, IOL = 5mA, 2X Drive -- -- 0.36 V Push-Pull, IOL = 8mA, 2X Drive -- -- 0.63 V Open Drain, IOL = 20mA, 1X Drive -- -- 0.36 V Open Drain, IOL = 20mA, 2X Drive -- -- 0.17 V IOL LOW-Level Output Current Push-Pull, VOL = 0.4V, 1X Drive 2.745 -- -- mA Push-Pull, VOL = 0.4V, 2X Drive 5.490 -- -- mA Open Drain, VOL = 0.4V, 1X Drive 21.960 -- -- mA Open Drain, VOL = 0.4V, 2X Drive 43.920 -- -- mA TSU Startup Time After VDD reaches 1.4-1.6V level -- 7 1 -- ms

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6.0 Summary of Macro Cell Function

6.1 I/O Pins (10 total)

• Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
• Open Drain
• P u s h P u l l
• Analog I/O
• 50K/100K/300K pull-up/pull-down resistors

6.2 Connection Matrix

• Digital matrix for circuit connections based on user design

6.3 Analog to Digital Converter

• 8-bit, 10kHz, Successive Ap proximation Register ADC
• DNL < ±1LSB, INL < ±1LSB
• V IN Range: 0 ~ 1V
• Common Mode Voltage Range: V PP/2 ~ VDD/2
• 3-bit Programmable Gain Amplifier with gain values of (1, 2, 4, 8,16X in differential mode and 0.5, 1, 2, 4, 8X in single-ended mode)
• SPI output format

6.4 Analog Comparators (2 total)

• 0mV/12mV/50mV/150mV Hysteresis

6.5 Voltage Reference Out

• Provides an external voltage based on either ACMP0 reference or V DD/3

6.6 Digital Comparators or PWM (3 total)

• Three 8-bit 10MHz PWMs or Digital Comparators

6.7 Delays/Counters (4 total)

• Delay Time Range: 1-16384 clock cycles (clock cycle based on RC Oscillator or External Clock Input)
• Three 14-bit delays/counte rs: Range 1-16384 clock cycles
• One 8-bit delay/counter: Range 1-255 clock cycles
• Two counters can function as FSM counters

6.8 Programmable Delay

• 20ns/40ns/60ns/80ns

6.9 Pipe Delay Output

• 1 p i p e
• 2/4/8/12 pipes
• 3/5/7/11 pipes

6.10 RC Oscillator

• 16 frequencies ranging from 27kHz – 10MHz

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6.11 Slave SPI/S2P

• Supports Slave SPI to control DCMP/PWM/FSM counter
• ADC SPI Output

6.12 Combinatorial Logic LUTs (11 total)

• Used to create either standard or custom digital logic cells
• Four 2-bit Lookup Tables
• Six 3-bit Lookup Tables
• One 4-bit Lookup Table

6.13 Digital Storage Elements (4 total)

• Four D Flip-Flops or Latches

6.14 Power On Reset

• V DD >1.6V

7.0 I/O Pins

serve as a programmable function for the one time Non-Volatile Memory to configure interconnect logic.

• PIN 2: Input Pin only
• PIN 3: GPIO or Input for Analog Comparator 0
• PIN 4: GPIO or Input for Analog Comparator 1
• PIN 5: GPIO or External Clock Input for ADC, RC OSC and S2P
• PIN 6: GPIO or ADC Serial Output Data, S2P input/output data (reg<712:711>)
• PIN 8: GPIO or ADC IN+
• PIN 9: GPIO or ADC IN-
• PIN 10: GPIO or V REF Output
• PIN 11: GPIO or V REF Input
• PIN 12: GPIO or Single-Ended mode ADC channel selection Programming Mode Pin Definition is as follows:
• PIN 2: Voltage for Programming Power (7.5V needed)
• PIN 3: Program Reset
• PIN 8: Program Mode Control
• PIN 9: Die ID
• PIN 10: NVM Read Mode Output Data
• PIN 11: NVM Write Mode Input Data
• PIN 12: NVM Clock Of the ten user defined I/O Pins in the SLG46400, nine pins (PINs 3, 4, 5, 6, 8, 9, 10, 11, and 12) can be used for either input or output and one pin (PIN 2) is defined as input only.

7.1 Input Modes

inputted into the SLG46400, based on the configuration of the input pin which is defined by the user. Figure 2. I/O Pads Layout

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7.2 Output Modes

PINs 3, 4, 5, 6, 8, 9, 10, 11 and 12 can be configured as ei ther an open drain output or push -pull output (with Output Enable). Additionally PIN 10 can be also be configured as an analog output in the SLG46400 device. The OE functionality for each of the output pins is controlled by the connection matrix except for PINs 3, 8, and 9. Those pins are controlled by the following registers: reg<685> for PIN3 reg<547> for PIN8 reg<556> for PIN9

7.2.1 Open Drain Output

The Open Drain Output setting has a 1X current ratio. The open drain output signal from the SLG46400 design will decide the port’s output state (Hi-Z or ground). If the signal = 1, output will be Hi-Z (high impedance) If the signal = 0, output will be connected to ground PINs 6 and 12 have a 2X current sinking option where the current value depends on VDD.

7.2.2 Push Pull with Output Enable

The Push Pull with Output Enable setting has either a 1X or 2x current ratio and the Output Enable signal will make the output Hi-Z All output pins have Push Pull 2X current sinking option where the current value depends on VDD. With 1X option these currents will be one half the value of the 2X value.

7.2.3 Analog Input and Open Drain Output

PINs 3, 4, 8, 9, and 11, can be configured as Analog Inputs/Open Drain Outputs on this device. Using this configuration will make the pin bi-directional, but the output will be Open Drain. This means that a logic LOW state on the pin will cause both the output and the input to go LOW.

7.2.4 Analog Output

Analog output functionality is only available on PIN 10 and is configured via the VREF cell Analog Output = internal signal value

7.2.5 Digital Bi-Directional Input / Output Pin by Configuring Settings

PIN 4, PIN 5, PIN 6, PIN 10, PIN 11, and PIN 12 can be configured as a Bi-Directional Pins by configuring the Analog Input and Open Drain Output settings in the GreenPAK II Designer tool. This is done by going to the PIN’s propertly menu in the GreenPAK II Designer software and changing the Mode Setting to “Analog In/Out and Open Drain”.

7.2.6 Creating a Digital Bi-Directional Input / Output Pin using an OE Signal

The PINs can also be configured as Digital Bi-Directional Input / Output Pins using an external Output Enable signal with the following steps:

000-0046400-109 Page 13 of 89 SLG46400 1. Configure the I/O Pins as one of the following: a. Digital Input with Schmitt Trigger b. Digital Input without Schmitt Trigger c. Low Voltage Digital Input 2. Use a control signal for the Output Enable on the I/O Pin 3. The I/O Pin will function as Push Pull 1x current by setting the OE signal of the pin to HIGH.

7.3 Pull Up/Down Resistors

All 10 I/O Pins have the option of a 50k/ 100k/300k pull up/down resistor. Resistors can be used with any of the input or output pin configurations previously defined.

7.4 I/O Pins Register Settings

7.4.1 PIN 2 Register Settings

7.4.2 PIN 3 Register Settings

Table 1. PIN 2 Register Settings Table 2. PIN 3 Register Settings

7.4.3 PIN 4 Register Settings

7.4.4 PIN 5 Register Settings

Table 3. PIN 4 Register Settings Table 4. PIN 5 Register Settings

7.4.5 PIN 6 Register Settings

7.4.6 PIN 8 Register Settings

Table 5. PIN 6 Register Settings Table 6. PIN 8 Register Settings

7.4.7 PIN 9 Register Settings

7.4.8 PIN 10 Register Settings

Table 7. PIN 9 Register Settings Table 8. PIN 10 Register Settings

7.4.9 PIN 11 Register Settings

7.4.10 PIN 12 Register Settings

Table 9. PIN 11 Register Settings Table 10. PIN 12 Register Settings

8.0 Connection Matrix

fully custom circuit will be created. For a complete list of the SLG46400’s register table, see Appendix A.

8.1 Connection Matrix Register Settings

Table 11. Connection Matrix Register Settings

000000 Ground

000001 LUT2_0 Output

000010 LUT2_1 Output

000011 LUT2_2 Output

000100 LUT2_3 Output

000101 LUT3_0 Output

000110 LUT3_1 Output

000111 LUT3_2 Output

001000 LUT3_3 Output

001001 LUT3_4 Output

001010 LUT3_5 Output

001011 LUT4 Output

001100 DFF0/LATCH0 Output

001101 DFF1/LATCH1 Output

001110 DFF2/LATCH2 Output

001111 DFF3/LATCH3 Output

010000 PIN2 Digital Output

010001 PIN3 Digital Output

010010 PIN4 Digital Output

010011 PIN5 Digital Output

010100 PIN6 Digital Output

010101 PIN8 Digital Output

010110 PIN9 Digital Output

010111 PIN10 Digital Output

011000 PIN11 Digital Output

011001 PIN12 Digital Output

011010 RC Oscillator Output

011011 RC Oscillator Divided By 4 Output

011100 RC Oscillator Divided By 12 Output

011101 DLY0/CNT0 Output

011110 DLY1/CNT1 Output

011111 DLY2/CNT2 Output

100000 DLY3/CNT3 Output

100001 Edge Detect Output

100010 Analog Comparator0 Output

100011 Analog Comparator1 Output

100100 ADC Output

100101 Digital Comparator0 Equal Output

100110 Digital Comparator1 Equal Output

100111 Digital Comparator2 Equal Output

101000 PWM/DCMP0 OUT- Output

101001 PWM/DCMP0 OUT+Output

101010 PWM/DCMP1 OUT- Output

101011 PWM/DCMP1 OUT+Output

101100 PWM/DCMP2 OUT- Output

101101 PWM/DCMP2 OUT+Output

101110 Reserved

101111 Programmable Delay Output

110000 Pipe Delay OUT0

110001 Pipe Delay OUT1

110010 Power Detector Output (PWR DETECT)

110100 DFF0 Negative Output (nQ)

110101 DFF1 Negative Output (nQ)

110110 DFF2 Negative Output (nQ)

110111 DFF3 Negative Output (nQ)

111000 Ground

111001 Ground

111010 Ground

111011 Ground

111100 Ground

111101 Ground

111110 Power On Reset (OUT)

111111 VDD

9.0 Analog-to-Digital Converter (ADC)

• CH SELECTOR: Single-Ended Mode ADC Selection and Analog Input Mux Control Signal (PIN 12)
• IN+: Single-Ended Mode Input and Differential Mode Positive Input (PIN8)
• IN-: Differential Mode Negative Input (PIN 9)
• EXT. VREF: ADC External Voltage Reference Input (PIN 11)
• EXT. CLK: ADC External Clock Input (PIN 5)
• SHARED PD: ADC Power Down Signal Outputs:
• Ext_refout: ADC External Volt age Reference Output (PIN 10)
• PGA_Out: Output of the PGA to ACMP0
• SER DATA: ADC serial output (PIN 6)
• PAR DATA: 8-bit ADC parallel data to either the PWM or DCMP0
• ADC Interrupt Output (INT. OUT)

9.1 ADC Functional Diagram

Figure 3. ADC Functional Diagram

9.2 ADC Operation Modes

• Single-Ended ADC operation using IN+ from PIN 8, when ADC_sel (reg <742>) is “0”
• Differential ADC operation using IN+ from PIN 8 and IN- from PIN 9, when ADC_sel (reg <742>) is “1”
• Pseudo-Differential ADC operation using IN + from PIN 8 and IN- from PIN 9, when ADC_sel (reg <742>) and ADC_pseudodiff_en (reg <738>) bits are both set to “1”

9.3 ADC 3-bit Programmable Gain Amplifier

For Pseudo-Differential mode, the PGA gain can only be 1X.

9.4 ADC 2-Channel Selection

the selection is controlled by PIN 12.

• When PIN 12 is set to “0”, the ADC will sample PIN 9
• When PIN 12 is set to “1”, the ADC will sample PIN 8 When ADC_channel_sel (reg <714>) is set to “0”, the PGA of the ADC will sample PIN 8 on the IN+ input.

9.5 ADC Input Voltage Definition

Figure 4. ADC 2-Channel Selection

9.6 ADC Reference Voltage

• Bandgap voltage (V BG) of 1V or 0.778V from Internal Source
• 1x or 2x External User Defined Voltage Source (PIN 11)
• Power Divider of (0.25 or 0.5) * V DD

9.7 ADC Power Down Select Mode

ADC and the PGA to power down mode. The SLG46400 also has a slow/fast power on mode feat ure controlled by reg<715>. When reg<715> = 0, the ADC is in slow power on mode and the entire analog block is controlled by connection matrix output 3. 20μs; the next power cycle the ADC power on (ADC only) time is <1ns.

9.8 ADC Clock Source

• The RC Oscillator is used when the ADC_clk_sel is “0”
• An external clock from PIN 5 is used when the ADC_clk_sel is “1” The ADC requires 16 clock cycles to sample the analog voltage and output the sampled data. When the internal RC Oscillator is used for providing timing to the ADC, a total of 1024 clo ck cycles are needed since the CLK4ADC signal is also divided by 64.

Figure 5. ADC Reference Voltage Table 12. ADC Reference Voltage.

10 Power Divider

11 N/A N/A

Figure 6. ADC Clock Source

When an external clock is used on PIN5, the ADC will only need 16 clock cycles, as it bypasses the divide by 64 logic.

9.9 ADC Outputs

clock cycles when activated, while the PAR DATA produces an 8-bit data string over 16 clock cycles.

9.9.1 ADC Serial Output

external device within the larger system design.

9.9.2 ADC Parallel Output

9.10 ADC Interrupt Output Timing Diagram

Figure 7. ADC Interrupt Output Timing Diagram

9.11 ADC Register Settings

Table 13. ADC Register Settings

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10.0 Analog Comparator (ACMP)

There are two Analog Comparator (ACMP) macro cells in the SLG46400. In order for the ACMP cells to be used in a GreenPAK design the power up signals (PWR UP) need to be active. These signals should be HIGH to turn on the ACMP and LOW to turn it off and each ACMP can be powered seperately. When ACMP is powered down, output is low. Each of the two ACMP cells has a negative input signal that is either created from an internal reference voltage (VREF) or provided by way of the external sources.

10.1 ACMP0 Input Modes

ACMP0’s positive input (IN+) can be connected to PIN3, PI N4, ADC/PGA OUT or IN by setting reg <735> and by the ACMP0_PGA_en signal, reg<739>. The negative input (IN-) of the ACMP0 cell can come from the internal VREF macro cell which will generate a 50mV to 1.5V signal (only when V DD > 3.0V), a 30mV to 1.0V signal, or fr om an external voltage source that is placed on PIN 11. Selection is made using a 4-bit value from NVM (reg<725:722>) and the VREF band select (reg<736>).

10.2 ACMP0 Functional Diagram

10.3 ACMP1 Functional Diagram

Figure 8. ACMP0 Functional Diagram Figure 9. ACMP1 Functional Diagram

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10.4 ACMP1 Input Modes

ACMP1’s positive input (IN+) comes from PIN 4 with selection gain of 1X or 0.5X (two 50k Ω resistor divider). The ACMP1_0.5gain_en signal (reg<747>) is used as a control signal into a MUX which has the 1X and 0.5X signals as inputs. The negative input (IN-) of the ACMP1 cell can come from the DAC or the internal VREF logic cell (selected by reg <745>) which will generate a 50mV to 1.5V signal (only when V DD > 3.0V), a 30mV to 1.0V signal, or fr om a external voltage source that is placed on PIN 11 (but not more than V AIR parameter for correct ACMP operation, see Section 5.0 Electrical Specifications) . Selection is made using a 4-bit value from NVM, reg<730:727> and the VREF band select (reg<736>). Reg <746> selects either the FSM1 or ADC as the source of the DAC. The maximum ACMP output delay is 5μs based on a minimum input difference of 2mV. The ACMP output is undefined for 100μs after power up. When the power supply changes its value from higher to lower or vice versa (detect value is around 2.7V), then a special internal block (power regulator) starts up/down and influences VREF. It means that ACMP with internal VREF has output glitches if overvoltage is less than 50mV.

10.5 ACMP Output Modes

When IN+ has a greater voltage than IN-, the ACMP’s output will be “1”. Otherwise, that output will be a “0” signal. The ACMP of the SLG46400 has an offset voltage of ± 5mV.

10.6 ACMP 1uA Input Current Option

Both ACMP’s can source 1μA on their respected inputs. This feature is controlled by the following signals: ACMP0_l1u_en, reg<721> for ACMP0 ACMP1_l1u_en, reg<726> for ACMP1 When either of these signals are equal to “1” the input will source a 1μA current.

10.7 ACMP Low Bandwidth

Both ACMP’s have a low bandwidth enable feature; this is controlled by the following signals: ACMP0_low_bw, reg<811> for ACMP0 ACMP1_low_bw, reg<812> for ACMP1 When either of these signals are equal to “1” and the input frequency is more than 200kHz, the output retains its last value.

10.8 ACMP Frequency Bode Plot

Figure 10. ACMP Frequency Bode Plot

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10.9 ACMP Hysteresis

Both ACMP’s have a hysteresis feature, where either the addition or subtraction of 12, 50, or 150 mV to the IN- signal will change the ACMP’s output value. The amount of hysteresis is controlled as shown below: ACMP0_hy_en, reg<732:731> when set to “01” will turn on the 12mV hysteresis,

• Output from “0” becomes “1” when IN+ ≥ IN- + 0.006V
• Output from “1” becomes “0” when IN+ ≤ IN- - 0.006V ACMP0_hy_en, reg<732:731> when set to “10” will turn on the 50mV hysteresis,
• Output from “0” becomes “1” when IN+ ≥ IN- + 0.025V
• Output from “1” becomes “0” when IN+ ≤ IN- - 0.025V ACMP0_hy_en, reg<732:731> when set to “11” will turn on the 150mV hysteresis,
• Output from “0” becomes “1” when IN+ ≥ IN- + 0.075V
• Output from “1” becomes “0” when IN+ ≤ IN- - 0.075V ACMP1_hy_en, reg<734:733> when set to “01” will turn on the 12mV hysteresis,
• Output from “0” becomes “1” when IN+ ≥ IN- + 0.006V
• Output from “1” becomes “0” when IN+ ≤ IN- - 0.006V ACMP1_hy_en, reg<734:733> when set to “10” will turn on the 50mV hysteresis,
• Output from “0” becomes “1” when IN+ ≥ IN- + 0.025V
• Output from “1” becomes “0” when IN+ ≤ IN- - 0.025V ACMP1_hy_en, reg<734:733> when set to “11” will turn on the 150mV hysteresis,
• Output from “0” becomes “1” when IN+ ≥ IN- + 0.075V
• Output from “1” becomes “0” when IN+ ≤ IN- - 0.075V

10.10 ACMP0 & ACMP1 Register Settings

10.10.1 ACMP0 Register Settings

Table 14. ACMP0 Register Settings

10.10.2 ACMP1 Register Settings

Table 15. ACMP1 Register Settings

11.0 Voltage Reference Out (VREF Out)

The VREF macro cell supplies an accurate reference voltage for the SLG46400.

11.1 VREF Output

the SLG46400, the VREF output enable signal (reg<741>) must be turned on. impedance becomes 1kΩ. With the op amp buffer switched out, the PIN 10 output voltage reference’s impedance is 100kΩ.

11.2 VREF Sources

11.3 VREF Functional Diagram

Figure 11. VREF Functional Diagram

11.4 VREF Register Settings

Refer to reg <725:722> for possible VREF configurations. Table 16. VREF Register Settings

000-0046400-109 Page 35 of 89 SLG46400

12.0 Digital Comparator (DCMP) / Pulse Width Modulator (PWM)

The SLG46400 has three 8-bit digital comparator / pulse width modulator logic cells. Each of these three logic cells can be either a digital comparator (DCMP) or a pulse width modulator (PWM) independently of how the other two logic cells are defined. Both the DCMP and PWM logic can operate at up to a frequency of 10MHz. The input power for the three logic cells is controlled independently by reg<760> for DCMP0/PWM0, reg<761> for DCMP1/PWM1 and reg<762> for DCMP2/PWM2. PWM power down control is configured by reg <815:814> which is also shared with the ADC and OSC

12.1 DCMP Input Modes

The three DCMP logic cells have a positive (IN+) and a negative (IN-) input that are compared within the logic cell. The inp signal (connected to the IN+ input) takes the value from a 4:1 mux selection between the following signals:

• 8-bit signal from the ADC Parallel Output
• 8-bit signal from the S2P logic cell output (S2P< 15:8> for DCMP0 and DCMP1 or S2P<7:0> for DCMP2)
• 8-bit signal from the FSM0<7:0>
• 8-bit user defined signal value. The inn signal (connected to the IN- input) takes the value from an 8-bit user defined value for the DCMP operation.

12.2 DCMP Output Modes

The two 8-bit data inputs from IN+ and IN- are compared within the DCMP logic cells to produce the output and a match signal.

• I f inp > inn, both OUT+ and OUT signals are equal to “1”, and EQ signal is equal to “0”
• I f inp < inn, both OUT+ and OUT signals are equal to “0”, and EQ signal is equal to “0”
• I f inp = inn, both OUT+ and OUT signals are equal to “0”, and EQ signal is equal to “1” Both the OUT+ and EQ signals are triggered by the rising or falling edge of the CKOSC signal (defined by bit reg <759>).

12.3 PWM Input Modes

IN+ for the PWM is an 8-bit data string that can be selected from one of four sources;

• 8-bit signal from the ADC Parallel Output
• 8-bit signal from the S2P logic cell output (S2P< 15:8> for DCMP0 and DCMP1 or S2P<7:0> for DCMP2)
• 8-bit signal from the FSM0<7:0>
• 8-bit user defined signal value. IN-’s 8-bit data string for all PWMs is sourced from an 8-bit signal from CNT/DLY1.

12.4 PWM Output Modes

signal (EQ) will go high. The outputs (OUT- and OUT+) are non-overlapping.

• PWM output duty cycle ranges from 0% to 99.61% and is determined by: Output Duty Cycle = IN+/256
• (IN+ = 0: output duty cycle = 0/256 = 0%; IN+ = 255: output duty cycle = 255/256 = 99.61%)
• Output signals are triggered by the rising or falling edge of the CKOSC signal (defined by bit reg <759>). When reg<758/818/819> = “1”
• PWM output duty cycle ranges from 0.39% to 100% and is determined by Output Duty Cycle = (IN+ + 1)/256
• (IN+ = 0: output duty cycle = 1/256 = 0.39%; IN+ = 255: output duty cycle = 256/256 = 100%)
• Output signals are triggered by the rising or falling edge of the CKOSC signal (defined by bit reg <759>). When IN+ = IN- then EQ = “1”

12.5 DCMP0/PWM0 Functional Diagram

Figure 12. DCMP0/PWM0 Functional Diagram

12.6 DCMP1/PWM1 Functional Diagram

12.7 DCMP2/PWM2 Functional Diagram

Figure 13. DCMP1/PWM1 Functional Diagram Figure 14. DCMP2/PWM2 Functional Diagram

12.8 PWM Dead Band Control

64ns, increasing by 8ns intervals.

12.9 PWM Dead Band Control Timing Diagram

12.10 DCMP/PWM Power Down Control

• When reg<760> = “0” DCMP0/PWM0 is powered down, when “1” logic cell is ON
• When reg<761> = “0” DCMP1/PWM1 is powered down, when “1” logic cell is ON
• When reg<762> = “0” DCMP2/PWM2 is powered down, when “1” logic cell is ON

12.11 DCMP/PWM Clock Invert Control

control the three logic cells clock inversion. Figure 15. PWM Dead Band Control Timing Diagram

12.12 DCMP/PWM Register Settings

Table 17. DCMP/PWM Register Settings

000-0046400-109 Page 40 of 89 SLG46400

13.0 Counters/Delay Generators (CNT/DLY)

There are four configurable counters/delay generators in the SLG46400. Th ree of these four logic ce lls can be either a 14-bit counter (CNT) or a delay generator (DLY) and one can be a 8-bit counter or delay generator independently of how the other three logic cells are defined.

13.1 Counter Functionality

CNT0, CNT1 and CNT2 each have a 14-bit input data source, while CNT3 has a 8-bit input data source. CNT2 and CNT3’s inputs can be sourced from the NVM, the ADC, or the S2P, while CNT0 and CNT1’s inputs can be sourced from the connection matrix. The clock can be sourced from either the internal RC Oscillator (with data divider for CNT1) or from another connection matrix output. The counters output their data to either the PWM or to the S2P. The supported counter functions include (FSM only): count UP , count DOWN, KEEP, and LOAD DATA (taken from ADC, S2P or Counter Data). The four counters can also function as frequency dividers, FSM (CNT2 and CNT3), or PWM ramp (CNT1), while captured data is outputted to S2P. In counter mode, it is in DOWN mode. the count UP/DOWN, KEEP , and LOAD signals in CNT2 and CNT3 must be tied to ground and the RC OSC should be forced ON if the clock is sourced from the internal RC OSC for the counter to work. For proper counter functionality, the force signals (CNT0_ force reg<588>, CNT1_force reg<610>, CNT2_force reg<633>, CNT3_force reg<655>) should be configured as “1” (Force Power On) for any block configured as counter. Example: for CNT3 to use the CNT/DLY block in Counter mode the following settings should be applied:

• CNT/DLY3 Output Source Select ( output_src_sel) set to Counter Mode (reg <656> = “1”)
• CNT3 Enable ( CNT3_force) set to Force Power On (reg <655> = “1”)
• Reset Source ( rst_src_sel) should be set to Edge Detect mode (reg<654> = “1”)
• Edge Select can be set to Both, Falling, or Rising (reg <669:668>)
• Additionally, make sure that RC Osc is in operating mode. The RC Osc may need to be set to Force On as well. Since CNT1 and CNT2 can be used for a PWM ramp function, the PWM power down signal will control the force power to those macro cells.

13.2 CNT2 and CNT3 Reset Source Select

When reg <632> = “1“ (for CNT2) or reg <654> = “1“ (for CNT3), the reset signal for CNT2 or CNT3 is sourced from the falling and/or rising edge active signal from the connection matrix and onl y applies when used for counter function. When used in the counter function and reg <632> / reg <654> = “0“ then the reset signal is sourced from the POR. However when the counter cells are used for a delay function, reg <632> / reg <654> must be set to 0.

13.3 Counters Functional Diagram

Figure 16. Counters Functional Diagram

13.4 Counter Timing

have a value of greater than ‘1’. same for CNT3, except the timing would be based on 8-bits of data rather than 14-bits. Figure 17. Counter Behavior

13.5 CNT0/DLY0 and CNT1/DLY1 Register Settings

Table 18. CNT0/DLY0 and CNT1/DLY1 Register Settings

13.6 CNT2/DLY2 and CNT3/DLY3 Register Settings

Table 19. CNT2/DLY2 and CNT3/DLY3 Register Settings

13.7 CNT2 as a Finite State Machine (FSM0)

CNT2 can be used as a 14-bit Finite State Machine, which has features for UP/DOWN/KEEP control and loading data select.

• When UP/DOWN = “1“: CNT2 is in up-counting mode, after POR or reset, the Q value will count from 0 to 16383, then the N is loaded (d <13:0>) and the Q value count from loaded data N to 16383. When Q is equal to 16383, OUT generates a single clock cycle pulse as shown in Figure (FSM Behavior).
• When UP/DOWN = “0“: CNT2 is in down-counting mode, the Q va lue will count from the loaded data value of N (based on reg<651:638> + 1) to 0. When Q is equal to 0, OUT generates a single clock cycle pulse as shown in Figure (FSM Behavior).
• When KEEP = “1“: Q will stay at its current value.
• When DLY IN has a transition (edge mode is dependent on reg<653:652>), a narrow pulse signal will be generated which will reset the CNT2 state to “0“.
• For FSM operation, the Reset Source ( rst_src_sel) should be set to Edge Detect in Counter Mode and user will be able to select rising, falling, or both edge (if resetting is needed), or tie reset input to ground (if resetting is not needed).
• LOAD function is synchronous to Counter’s clock signal. Fo r LOAD event to happen there should be a rising edge on the clock input of the FSM and LOAD node should be HIGH.

13.8 FSM0 (CNT2) Functional Diagram

Figure 18. FSM0 (CNT2) Functional Diagram Figure 19. FSM0 Behavior

13.9 CNT3 as a Finite State Machine (FSM1)

CNT3 can be used as a 8-bit Finite State Machine, which has features for UP/DOWN/KEEP control and loading data select.

• When UP/DOWN = “1“: CNT3 is in up-counting mode, after POR or reset, the Q value will count from 0 to 255, then the N is loaded (d <13:0>) and the Q value count from loaded data N to 255. When Q is equal to 255, OUT generates a single clock cycle pulse as shown in Figure (FSM Behavior).
• When UP/DOWN = ”0”: CNT3 is in down-counting mode, the Q va lue will count from the loaded data value of N (based on reg<667:660> + 1) to ”0”. When Q is equal to 0, OUT generates a single clock cycle pulse as shown in Figure (FSM Behavior).
• When KEEP = ”1”: Q will stay at its current value.
• When DLY IN has a transition (edge mode is dependent on reg<669:668>), a narrow pulse signal will be generated which will reset the CNT3 state to “0”.
• For FSM operation, the Reset Source ( rst_src_sel) should be set to Edge Detect in Counter Mode and user will be able to select rising, falling, or both edge (if resetting is needed), or tie reset input to ground (if resetting is not needed).
• LOAD function is synchronous to Counter’s clock signal. Fo r LOAD event to happen there should be a rising edge on the clock input of the FSM and LOAD node should be HIGH.

13.10 FSM1 (CNT3) Functional Diagram

Figure 20. FSM1 (CNT3) Functional Diagram Figure 21. FSM1 Behavior

13.11 FSM Register Settings

13.12 Delay Cell Functionality

from a rising edge transition, a falling edge transition, or a transition in either direction. Table 20. FSM Register Settings Figure 22. Delay Cells - Long Pulse, Rising Edge Figure 23. Delay Cells - Long Pulse, Falling Edge Figure 24. Delay Cells - Short Pulse, Rising Edge

13.13 Delay Cells Functional Diagram

13.14 Delay Timing

Oscillator which has a /4, /8, and /12 function. Note: In order for these equations above to be valid the pulse width must be larger than the total rising and falling edge delay times. Figure 27. Delay Cells Functional Diagram

14.0 Programmable Delay (PDLY)

in series where the output of each delay cell goes to the next delay cell and to a 4-input mux that is controlled by reg<537:536>.

14.1 Programmable Delay Functional Diagram

14.3 Programmable Delay Register Settings

Figure 28. Programmable Delay Functional Diagram Table 21. VDD vs. Typical Time Delay per 1 Cell. Table 22. Programmable Delay Register Settings

000-0046400-109 Page 51 of 89 SLG46400

15.0 Pipe Delay (PD)

The SLG46400 has a pipe delay logic cell available that can generate up to three individual delays concurrently:

• a single delay stage on 1 PIPE OUT
• 3, 5, 7, or 11 stages of delay on OUT0
• 2, 4, 8, 12 stages of delay on OUT1 The pipe delay cell is built from 12 D Flip-F lop logic cells that provide the three del ay options. The DFF cells are tied in se ries where the output (Q) of each delay cell goes to the next DFF cell. There are delay output points for each set of the OUT0 and OUT1 outputs to a 4-input mux that is controlled by reg <810:809> for OUT0 and reg <821:820> for OUT1. The 4-input mux is used to control the selection of the amount of delay. The overall time of the delay is based on the clock used in the SLG46400 design. Each DFF cell has a time delay of the inverse of the clock time (either external clock or the RC Oscillator within the SLG46400). The sum of the number of DFF cells used will be the total time delay of the Pipe Delay logic cell.

15.1 Pipe Delay Functional Diagram

15.2 Pipe Delay Register Settings

Figure 29. Pipe Delay Functional Diagram Table 23. Pipe Delay Register Settings

16.0 Clock Management

cells. It has a frequency range of 27kHz – 10MHz which can be adjusted through the RCO_freq_cont registers <586:583>.

16.1 Clock Management Functional Diagram

16.2 RC OSC Power Down Control

to turn on the RC OSC. This signal has the highest priority and if the RC OSC is off, no other blocks of registers will be available.

16.3 RC OSC Dividers Control

16.4 Ring Oscillator and External Clock from PIN 5

reg<587> and reg<670> should be set to ‘1’. connection to matrix is not possible (CNT/DLY/FSM blocks and matrix will be fed from the internal RC Oscillator without dividers). Figure 30. Clock Management Functional Diagram

16.5 RC OSC Frequency Selection

16.6 RC OSC Register Settings

Table 24. RC OSC Typical Frequency Selection Table 25. RC OSC Register Settings

17.0 Slave SPI - Serial to Parallel / Parallel to Serial Converter (S2P)

signal comes from PIN 5 and the nCSB (Enable Control Signal) comes from the Connection Matrix Out. S2P uses edge detection from the DLY3 signal for capturing the input data.

17.1 S2P Functional Diagram

17.2 Serial to Parallel Operation

the LSB <7:0> can be used by the PWM/DCMP2, FSM0, and FSM1 logic cells.

17.3 Serial to Parallel Timing Diagram

17.4 Parallel to Serial Operation

output the 8-bit serial data out (MISO) signal. Figure 31. S2P Functional Diagram Figure 32. Serial to Parallel Timing Diagram

17.5 Parallel to Serial Timing Diagram

17.6 S2P Notes

• S2P serial to parallel mode or S2P parallel to serial out
• S2P parallel to serial mode or ADC serial output data on PIN 6
• S2P parallel to serial mode or DLY3 logic cell

17.7 S2P Register Settings

Figure 33. Parallel to Serial Timing Diagram Table 26. S2P Register Settings

18.0 Combinatorial Logic

logic devices (AND, NAND, OR, NOR, XOR, XNOR). The four 2-bit LUTs within the SLG46400 each take in two input signals from the connection matrix and produce a single output. LUT 2.0 inputs are shared with input and reset of the Pipe Delay logic cell. Figure 34. 2-bit LUTs Table 27. 2-bit LUT0 Truth Table. Table 28. 2-bit LUT1 Truth Table. Table 29. 2-bit LUT2 Truth Table. Table 30. 2-bit LUT3 Truth Table.

created within each of the four 2-bit LUT logic cells. Table 31. 2-bit LUT0/LUT1/LUT2/LUT3 Standard Digital Functions.

The six 3-bit LUTs within the SLG46400 each take in three input signals from the connection matrix and produce a single output. Figure 35. 3-bit LUTs Table 32. 3-bit LUT0 Truth Table. Table 33. 3-bit LUT1 Truth Table.

Table 34. 3-bit LUT2 Truth Table. Table 35. 3-bit LUT3 Truth Table. Table 36. 3-bit LUT4 Truth Table. Table 37. 3-bit LUT5 Truth Table.

created within each of the six3-bit LUT logic cells. Table 38. 3-bit LUT0/LUT1/LUT2/LUT3/LUT4/LUT5 Standard Digital Functions.

created within the 4-bit LUT logic cell. Figure 36. 4-bit LUT Table 39. 4-bit LUT0 Truth Table. Table 40. 4-bit LUT0 Standard Digital Functions.

19.0 Digital Storage Elements (DFFs/LATCHes)

outputs for the three DFF/LATCHes are configured from the connection matrix. DFF/LATCH 1, matrix out18 will control the Reset and Set functions (Active Low) that are controlled from reg<533>.

19.1 DFF/LATCH Functional Diagram

Figure 37. DFF/LATCH Functional Diagram

19.2 DFF/LATCH Selection

a Latch within the design. Those control bits are shown in the table below.

19.3 DFF/LATCH Register Settings

Table 41. DFF/LATCH Register Settings

20.0 Power On Reset (POR)

data out is 500μs. For POR to work properly, the max power up ramp time for VDD=1.8V is 34ms; for VDD=5V, it is 100ms. signals such as delay cells, ADC, or PWM, the oscillator will need a maximum of 5μs to become stable. Figure 38. Power on Reset Timing Diagram Figure 39. Stable Oscillator wait time

20.1 POR Register Settings Description

• When set to ‘010’: Auto power detect function is on (both auto detection and the regulator for ADC and ACMP are on)
• When set to ‘101’: VDD bypass to ADC (when VDD < 2.7V, no power consumption is used by either the ADC or ACMP logic cells)
• When set to ‘001’: Regulator always on (when VDD > 2.7V, there is no auto power detection, but regulator has power for the ADC & ACMP logic cells). If the ADC or ACMP are not in use; reg <750:748> should be set to ‘000’ and the ADC/ACMP logic cells should be set to power down mode. If the ADC or ACMP are in use:
• i f V DD is fixed and ≤ 2.7V, reg <750:748> should be set to ‘101’.
• I f V DD varies from 1.8V to 5.0V, reg <750:748> should be set to ‘010’
• i f V DD varies from 2.6V to 5.0V, reg <750:748> should be set to ‘010’ or ‘001’.

20.2 POR Register Settings

Table 42. POR Register Settings

21.0 Application Examples

21.1 System Reset

within the SLG46400 requires the use of an input buffer, an open drain LED output driver, a de-glitch filter, and a one-shot circuit. In this example the SLG46400 replaces up to four off-the-shelf components.

21.2 Combinatorial Logic

used in the final PCB design.

21.3 Example: Bi-Directional Pin using an OE Signal

signal for the Output Enable control signal. The input to PIN 2 is controlled from an external signal, which is then used to control the Output Enable on PIN 3.

• When the signal on PIN 2 = “0”, then PIN 3 will act as a Digital Input. In this example, the signal from PIN 3 is going to the logic cell (LUT2.1 in this case).

Figure 40. Example: System Reset Figure 41. Example: Combinatorial Logic

• When the signal on PIN 2 = “1”, then PIN 4 will act as a Push Pull Output with 1x current drive. In this example, a signal from CNT1/DLY1 will be sent from the SLG46400 to the external board.

Figure 42. PIN 4 as a Bi-Directional Pin with PIN 2 as the OE Control

000-0046400-109 Page 69 of 89 SLG46400

22.0 Development Tools

22.1 Software & Hardware

22.1.1 GreenPAK 2 Designer™

At the core of the GreenPAK 2 development software suite is GreenPAK 2 Designer, graphical schematic design tool used to create circuit designs within the GreenPAK 2 IC. GreenPAK 2 Designer requires no programming language or complier. GreenPAK 2 Designer Software is available free of charge at http://www.silego.com/.

22.1.2 GreenPAK 2 Programmer

GreenPAK 2 Programmer is flexible enough and is used on the bench in development and also suitable for factory programming. GreenPAK 2 Programmer operates directly from GreenPAK 2 Designer.

22.1.3 Minimum System Requirements

• CPU: 800MHz
• RAM: 128MB
• Graphics RAM: 32MB
• Free Hard Disk Space: 50MB Both of Silego’s GreenPAK 2 Designer and Programmer software is supported in the following operating systems:
• 32-bit Microsoft Windows XP / Vista / 7
• 64-bit Microsoft Windows XP / Vista / 7
• Apple Mac OS X Windows is a registered trademark of Microsoft Corporation in the United States and other countries. Mac OS is a trademark of Apple Inc., registered in the U.S. and other countries.

22.2 Development Kits

The GreenPAK 2 Development kit is sold directly at the Silego Online Store. Please visit at http://store.silego.com/ The GreenPAK 2 Development kit is for prototyping and development with GreenPAK 2 Designer. The kit contains a USB Programming stick, USB extension cable and 50 SLG46400 samples. Everything needed for a circuit designer to start prototyping designs with the GreenPAK 2 IC.

22.3 Project Examples

Additional GreenPAK 2 examples designs are available on the Silego website free of charge. These designs can be downloaded and reviewed in the GreenPAK 2 designer as a quick and efficient way to become familiar with the project development. These examples can be found at http://support.silego.com/

000-0046400-109 Page 70 of 89 SLG46400

23.0 Package Top Marking System Definition

– Part ID Field: identifies the specific device configuration – Date Code Field: Coded date of manufacture – Lot Code: Designates Lot # – Assembly Site/COO: Specifies Assembly Site/Country of Origin – Revision Code: Device Revision XXXXX DD LLL C RR COO

000-0046400-109 Page 71 of 89 SLG46400

24.0 Package Drawing and Dimensions

24.1 12 Lead TDFN Package JEDEC MO-252, Variation 2525E

000-0046400-109 Page 72 of 89 SLG46400

24.2 Tape and Reel Specifications

24.3 Carrier Tape Drawing and Dimensions

# of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm]per Reel per Box Pockets Length [mm] Pockets Length [mm] TDFN 12L Green 12 2.5 x 2.5 x 0.75 3,000 3,000 178 / 60 42 168 42 168 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index hole to Pocket center Tape Width A0 B0 K0 P0 P1 D0 E F W TDFN 12L W EP0 Y Y Section Y-Y CL F Refer to EIA-481 specification

000-0046400-109 Page 73 of 89 SLG46400

25.0 Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 4.6875 mm 3 (nominal). More information can be found at www.jedec.org.

000-0046400-109 Page 74 of 89 SLG46400

26.0 Appendix - SLG46400 Register Definition

Bit Address Register Definition reg<5:0> Clock of Pipe Delay reg<11:6> Reset or set of DFF0 reg<17:12> Reset or set of DFF1 reg<23:18> Power down for ADC/PWM/RC OSC (reg<815:814> select power down block) reg<29:24> CNT2 external clock reg<35:30> CNT3 external clock reg<41:36> 20ns/40ns/60ns/80ns Delay input reg<47:42> nCSB for SPI reg<53:48> PWM/DCMP0 ip3 and PWM/DCMP1 in1 input mux select bit0 reg<59:54> PWM/DCMP0 ip3 and PWM/DCMP1 in1 input mux select bit1 reg<65:60> PWR UP (power up) for ACMP0 reg<71:66> PWR UP (power up) for ACMP0 reg<77:72> KEEP for FSM0 reg<83:78> LOAD for FSM0 reg<89:84> UP/DOWN for FSM0 reg<95:90> KEEP for FSM1 reg<101:96> LOADfor FSM1 reg<107:102> UP/DOWN for FSM1 reg<113:108> Input for DLY0 or CNT0 external clock reg<119:114> Input for DLY1 or CNT1 external clock reg<125:120> Input for DLY2 reg<131:126> Input for DLY3 reg<137:132> PIN3 Digital Output Source reg<143:138> PIN4 Digital Output Source reg<149:144> PIN5 Digital Output Source reg<155:150> PIN6 Digital Output Source (reg<712:711>=00) reg<161:156> PIN8 Digital Output Source reg<167:162> PIN9 Digital Output Source reg<173:168> PIN10 Digital Output Source reg<179:174> PIN11 Digital Output Source reg<185:180> PIN12 Digital Output Source reg<191:186> Output Enable of PIN4 reg<197:192> Output Enable of PIN5 reg<203:198> Output Enable of PIN6 reg<209:204> Output Enable of PIN10 reg<215:210> Output Enable of PIN11 reg<221:216> Output Enable of PIN12 reg<227:222> Data Input of DFF0 reg<233:228> Clock Input of DFF0 reg<239:234> Data Input of DFF1 reg<245:240> Clock Input of DFF1 reg<251:246> Data Input of DFF2

000-0046400-109 Page 75 of 89 SLG46400 reg<257:252> Clock Input of DFF2 reg<263:258> Data Input of DFF3 reg<269:264> Clock Input of DFF3 reg<275:270> IN0 of LUT2_0 /Input of Pipe Delay reg<281:276> IN1 of LUT2_0 /resetb of Pipe Delay reg<287:282> IN0 of LUT2_1 reg<293:288> IN1 of LUT2_1 reg<299:294> IN0 of LUT2_2 reg<305:300> IN1 of LUT2_2 reg<311:306> IN0 of LUT2_3 reg<317:312> IN1 of LUT2_3 reg<323:318> IN0 of LUT3_0 reg<329:324> IN1 of LUT3_0 reg<335:330> IN2 of LUT3_0 reg<341:336> IN0 of LUT3_1 reg<347:342> IN1 of LUT3_1 reg<353:348> IN2 of LUT3_1 reg<359:354> IN0 of LUT3_2 reg<365:360> IN1 of LUT3_2 reg<371:366> IN2 of LUT3_2 reg<377:372> IN0 of LUT3_3 reg<383:378> IN1 of LUT3_3 reg<389:384> IN2 of LUT3_3 reg<395:390> IN0 of LUT3_4 reg<401:396> IN1 of LUT3_4 reg<407:402> IN2 of LUT3_4 reg<413:408> IN0 of LUT3_5 reg<419:414> IN1 of LUT3_5 reg<425:420> IN2 of LUT3_5 reg<431:426> IN0 of LUT4_0 reg<437:432> IN1 of LUT4_0 reg<443:438> IN2 of LUT4_0 reg<449:444> IN3 of LUT4_0 reg<453:450> LUT2_0 data reg<457:>454 LUT2_1 data reg<461:458> LUT2_2 data reg<465:462> LUT2_3 data reg<473:466> LUT3_0 data reg<481:474> LUT3_1 data reg<489:482> LUT3_2 data reg<497:490> LUT3_3 data reg<505:498> LUT3_4 data reg<513:506> LUT3_5 data Bit Address Register Definition

000-0046400-109 Page 76 of 89 SLG46400 reg<529:514> LUT4 data reg<530> DFF0 or Latch select 0: DFF function 1: Latch function reg<531> DFF0 nRST/nSET select 0: nRST from matrix out1 1: nSET from matrix out1 reg<532> DFF1 or Latch select 0: DFF function 1: Latch function reg<533> DFF1 nRST/nSET select 0: nRST from matrix out18 1: nSET from matrix out18 reg<534> DFF2 or Latch select 0: DFF function 1: Latch function reg<535> DFF3 or Latch select 0: DFF function 1: Latch function reg<537:536> Delay value select 00: 20ns 01: 40ns 10: 60ns 11: 80ns reg<538> Reserved reg<540:539> PIN8 initial state control 00: floating 01: ground 10: power 11: input reg<543:541> PIN8 mode control 000: digital in mode with Schmitt trigger 001: digital in mode without Schmitt trigger 010: low voltage digital in mode without Schmitt trigger 011: analog IO mode 100: push pull current x2 101: open drain mode 110: analog IO & open drain mode 111: push pull mode reg<545:544> PIN8 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<546> PIN8 pull up/down resistor 0: pull down resistor 1: pull up resistor reg<547> PIN8 push pull output Enable 0: Disable 1: Enable reg<549:548> PIN9 Initial State Control 00: floating 01: ground 10: power 11: input Bit Address Register Definition

000-0046400-109 Page 77 of 89 SLG46400 reg<552:550> PIN9 mode control 000: Digital in mode with Schmitt trigger 001: Digital in mode without Schmitt trigger 010: Low voltage digital in mode without Schmitt trigger 011: Analog IO mode 100: Push pull current x2 101: Open drain mode 110: Analog IO & open drain mode 111: Push pull mode reg<554:553> PIN9 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<555> PIN9 pull up/down resistor 0: Pull down resistor 1: Pull up resistor reg<556> PIN9 push pull output Enable 0: Disable 1: Enable reg<558:557> PIN10 initial state control 00: Floating 01: Ground 10: Power 11: Input reg<561:559> PIN10 mode control 000: Digital in mode with Schmitt trigger 001: Digital in mode without Schmitt trigger 010: Low voltage digital in mode without Schmitt trigger 011: Analog IO mode 100: Push pull current x2 101: Open drain mode 110: Analog IO & open drain mode 111: Push pull mode reg<563:562> PIN10 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<564> PIN10 pull up/down resistor 0: Pull down resistor 1: Pull up resistor reg<566:565> PIN11 initial state control 00: Floating 01: Ground 10: Power 11: Input reg<569:567> PIN11 mode control 000: Digital in mode with Schmitt trigger 001: Digital in mode without Schmitt trigger 010: Low voltage digital in mode without Schmitt trigger 011: Analog IO mode 100: Push pull current x2 101: Open drain mode 110: Analog IO & open drain mode 111: Push pull mode Bit Address Register Definition

000-0046400-109 Page 78 of 89 SLG46400 reg<571:570> PIN11 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<572> PIN11 pull up/down resistor 0: Pull down resistor 1: Pull up resistor reg<574:573> PIN11 initial state control 00: Floating 01: Ground 10: Power 11: Input reg<577:575> PIN12 mode control 000: Digital in mode with Schmitt trigger 001: Digital in mode without Schmitt trigger 010: Low voltage digital in mode without Schmitt trigger 011: Reserved 100: Push pull current x2 101: Open drain mode 110: Reserved 111: Push pull mode reg<579:578> PIN12 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<580> PIN12 pull up/down resistor selection 0: Pull down resistor 1: Pull up resistor reg<581> PIN12 open drain double current 0: Normal current 1: Double current reg<582> Force RC Oscillator on 0: Auto Power On (Power on as needed) 1: Force Power On (Power always on) reg<586:583> RC Oscillator frequency control 0000: 28.66k 0001: 55.2k 0010: 78.84k 0011: 122.1k 0100: 141.58k 0101: 210.78k 0110: 225.06k 0111: 31‘.24k 1000: 487.02k 1010: 666.11k 1011: 765.72k 1100: 2.25M 1101: 2.93M 1110: 6.67M 1111: 8.28M reg<587> External Clock Source Select 0: Internal Oscillator Clock 1: External Clock Bit Address Register Definition

000-0046400-109 Page 79 of 89 SLG46400 reg<588> CNT0 Enable 0: Disable 1: Enable reg<589> CNT/DLY0 Output Source Select 0: Delay Output 1: Counter Output reg<592:590> CNT/DLY0 Clock Source Select 000: Internal RC OSC Clock 001: CLOCK/4 010: CLOCK/12 011: CNT1 Overflow Output 1X0: CLOCK/8 1X1: External Clock (reg<609> = 1) reg<606:593> CNT0 Control Data/DLY0 Time Control 1-16384: (delay time = (counter control data + 1) / freq) reg<608:607> DLY0 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges reg<609> DLY0 Input Function Select 0: For Delay Input signal 1: For CNT0 External Clock reg<610> CNT1 Enable 0: Disable 1: Enable reg<611> CNT/DLY1 Output Source Select 0: Delay Output 1: Counter Output reg<614:612> CNT/DLY1 Clock Source Select 000: Internal RC OSC Clock 001: CLOCK/4 010: CLOCK/12 011: CNT1 Overflow Output 1X0: CLOCK/8 1X1: External Clock (reg<631> = 1) reg<628:615> CNT1 Control Data/DLY1 Time Control 1-16384: (delay time = (counter control data + 1) / freq) reg<630:629> DLY1 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges reg<631> DLY1 Input Function Select 0: For Delay input signal 1: For CNT0 external clock reg<632> CNT/DLY2 Reset Source Select 0: From delay cell 1: From edge detect reg<633> CNT2 Enable 0: Disable 1: Enable reg<634> CNT/DLY2 Output Source Select 0: Delay Output 1: Counter Output Bit Address Register Definition

000-0046400-109 Page 80 of 89 SLG46400 reg<637:635> CNT/DLY2 Clock Source Select 000: Internal RC OSC Clock 001: CLOCK/4 010: CLOCK/12 011: CNT1 overflow output 1X0: CLOCK/8 1X1: External clock reg<651:638> CNT2 Control Data/DLY2 Time Control 1-16384: (delay time = (counter control data + 1) / freq) reg<653:652> DLY2 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges reg<654> CNT/DLY3 Reset Source Select 0: From Delay Cell 1: From Edge Detect reg<655> CNT3 Enable 0: Disable 1: Enable reg<656> CNT/DLY3 Output Source Select 0: Delay Output 1: Counter Output reg<659:657> CNT/DLY3 Clock Source Select 000: Internal RC OSC Clock 001: CLOCK/4 010: CLOCK/12 011: CNT1 Overflow Output 1X0: CLOCK/8 1X1: External Clock reg<667:660> CNT3 Control Data/DLY3 Time Control 1-255: (delay time = (counter control data + 1) / freq) reg<669:668> DLY3 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges reg<670> Ring Oscillator Enable 0: Disable 1: Enable (PWM/DCMP external clock source is selected from this ring osc) reg<671> Reserved reg<673:672> PIN2 Mode Control 00: Digital In Mode with Schmitt Trigger 01: Digital In Mode without Schmitt Trigger 10: Low Voltage Digital Input 11: Analog In reg<675:674> PIN2 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<676> PIN2 pull up/down resistor 0: Pull down resistor 1: Pull up resistor Bit Address Register Definition

000-0046400-109 Page 81 of 89 SLG46400 reg<678:677> PIN3 initial state control 00: Floating 01: Ground 10: Power 11: Input reg<681:679> PIN3 mode control 000: Digital in mode with Schmitt trigger 001: Digital in mode without Schmitt trigger 010: Low voltage digital in mode without Schmitt trigger 011: Analog IO mode 100: Push pull current x2 101: Open drain mode 110: Analog IO & open drain mode 111: Push pull mode reg<683:682> PIN3 pull up/down resistor value selection. 00: Floating 01: 50K 10: 100K 11: 300K reg<684> PIN3 pull up/down resistor 0: Pull Down Resistor 1: Pull Up Resistor reg<685> PIN3 push pull output Enable 0: Push Pull Output Disable 1: Push Pull Output Enable reg<687:686> PIN4 initial state control 00: Floating 01: Ground 10: Power 11: Input reg<690:688> PIN4 mode control 000: Digital in mode with Schmitt trigger 001: Digital in mode without Schmitt trigger 010: Low voltage digital in mode without Schmitt trigger 011: Analog IO mode 100: Push pull current x2 101: Open drain mode 110: Analog IO & open drain mode 111: Push pull mode reg<692:691> PIN4 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<693> PIN4 pull up/down resistor 0: Pull down resistor 1: Pull up resistor reg<695:694> PIN5 initial state control 00: Floating 01: Ground 10: Power 11: Input Bit Address Register Definition

000-0046400-109 Page 82 of 89 SLG46400 reg<698:696> PIN5 mode control 000: Digital in mode with Schmitt trigger 001: Digital in mode without Schmitt trigger 010: Low voltage digital in mode without Schmitt trigger 011: Reserved 100: Push pull current x2 101: Open drain mode 110: Reserved 111: Push pull mode reg<700:699> PIN5 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<701> PIN5 pull up/down resistor 0: Pull down resistor 1: Pull up resistor reg<703:702> PIN6 initial state control 00: Floating 01: Ground 10: Power 11: Input reg<706:704> PIN6 mode control 000: Digital in mode with Schmitt trigger 001: Digital in mode without Schmitt trigger 010: ;ow voltage digital in mode without Schmitt trigger 011: Reserved 100: Push pull current x2 101: Open drain mode 110: Reserved 111: Push pull mode reg<708:707> PIN6 pull up/down resistor value selection 00: Floating 01: 50K 10: 100K 11: 300K reg<709> PIN6 pull up/down resistor 0: Pull down resistor 1: Pull up resistor reg<710> PIN6 open drain double 0: Normal current 1: Double current reg<712:711> PIN6 digital output source selection 0x: From Connection Matrix (out25) 10: From S2P (MISO) 11: From ADC Serial Output reg<713> ADC Input Gain Range 0: 0 ~ 1V 1: 0 ~ 0.78V reg<714> ADC Mux Channel Selection 0: MUX Disabled, ADC will sample PIN 8 for IN+ 1: MUX Enabled, ADC will sample either PIN 8 or 9 for IN+ reg<715> ADC power down mode select 0: ADC slow power on mode 1: ADC fast power on mode Bit Address Register Definition

000-0046400-109 Page 83 of 89 SLG46400 reg<718:716> ADC PGA Gain Control 000: Single-ended (0.5X gain) or differential (N/A) 001: Single-ended (1X gain) or differential (1x gain) 010: Single-ended (2X gain) or differential (2X gain) 011: Single-ended (4X gain) or differential (4X gain) 100: Single-ended (8X gain) or differential (8X gain) 101: Single-ended (N/A) or differential (16X gain) reg<720:719> ADC VREF source select (depends on reg <713>) 00: Bandgap voltage VBG (1V or 0.778) 01: 1x or 2x external voltage source 11: None reg<721> ACMP0 1uA input current option 0: Disable 1: Enable reg<725:722> ACMP0 IN- voltage select (when reg<736> = 0) 0000: 50mV 0001: 100mV 0010: 150mV 0011: 200mV 0100: 250mV 0101: 300mV 0110: 400mV 0111: 500mV 1000: 600mV 1001: 700mV 1010: 800mV 1011: 900mV 1100: 1100mV 1101: 1300mV 1110: 1500mV 1111: External (PIN 11) reg<725:722> ACMP0 IN- voltage select (when reg<736> = 1) 0000: 30mV 0001: 70mV 0010: 100mV 0011: 130mV 0100: 170mV 0101: 200mV 0110: 270mV 0111: 330mV 1000: 400mV 1001: 470mV 1010: 530mV 1011: 600mV 1100: 730mV 1101: 870mV 1110: 1000mV 1111: External (PIN 11) reg<726> ACMP1 1μA input current option 0: Disable 1: Enable reg<730:727> ACMP1 IN- voltage select (when reg<736> = 0) 0000: 50mV 0001: 100mV 0010: 150mV 0011: 200mV 0100: 250mV 0101: 300mV 0110: 400mV 0111: 500mV 1000: 600mV 1001: 700mV 1010: 800mV 1011: 900mV 1100: 1100mV 1101: 1300mV 1110: 1500mV 1111: External (PIN 11) reg<730:727> ACMP1 IN- voltage select (when reg<736> = 1) 0000: 30mV 0001: 70mV 0010: 100mV 0011: 130mV 0100: 170mV 0101: 200mV 0110: 270mV 0111: 330mV 1000: 400mV 1001: 470mV 1010: 530mV 1011: 600mV 1100: 730mV 1101: 870mV 1110: 1000mV 1111: External (PIN 11) reg<732:731> ACMP0 hysteresis Enable 00: Disabled (0mV) 01: Enabled (12mV) 10: Enabled (50mV) 11: Enabled (150mV) reg<734:733> ACMP1 hysteresis Enable 00: Disabled (0mV) 01: Enabled (12mV) 10: Enabled (50mV) 11: Enabled (150mV) reg<736> ACMP VREF band select 0: 50mV to 1.5V range 1: 30mV to 1V range reg<737> ADC clock selection 0: Internal RC Oscillator 1: External clock from PIN 5 Bit Address Register Definition

000-0046400-109 Page 84 of 89 SLG46400 reg<738> ADC pseudo diff input Enable under ADC diff mode 0: Disabled 1: Enabled reg<739>, reg<735> ACMP0 IN+ source selection 00: ACMP0 IN+ input from PIN3 01: ACMP0 IN+ input from PIN4 (PIN3 analog_io_en should be disabled) 10: ACMP0 IN+ input from PGA OUT 11: ACMP0 IN+ input from PGA IN reg<740> VREF Output Active Buffer Control 0: Enabled 1: Disabled reg<741> VREF Output Enable 0: ACMP0 = VREF Input 1: Enabled reg<742> ADC Input Mode Select 0: Single-end operation using PIN 8 1: Differential mode using PINS 8 & 9 reg<743> VREF Output Source Select 0: ACMP0 reference voltage 1: VDD/3 reg<744> Force bandgap on 0: Disabled 1: Enable reg<745> ACMP1 negative input source select 0: from VREF 1: from DAC output reg<746> DAC input data select 0: ADC normal work 1: DAC data comes from FSM reg<747> ACMP1 positive input divided by 2 resistor(100K) 0: Disabled (IP input from PIN 4) 1: Enabled (IP input from ADC - PGA Out) reg<748> POR Auto Power Detection Control 0: Enable 1: Disable reg<749> POR Power Divider Power On (only required when using power divider output for external source) 0: Disable 1: Enable reg<750> POR VDD bypass to ADC (only required when VDD <=2.7V) 0: Disable 1: Enable reg<752:751> FSM0 Input Data Select x0: From NVM (connection matrix) 01: From S2P 11: From ADC reg<754:753> FSM1 Input Data Select x0: From NVM (connection matrix) 01: From S2P 11: From ADC reg<757:755> PWM deadband Select 000:8ns 001:16ns 010:24ns 011:32ns 100:40ns 101:48ns 110:56ns 111:64ns Bit Address Register Definition

000-0046400-109 Page 85 of 89 SLG46400 reg<758> PWM0 Mode Select 0: Down to 0% 1: Up to 100% reg<759> PWM/DCMP Clock Invert 0: Disable 1: Enable reg<760> PWM0/DCMP0 Power Down Control 0: Power down 1: Power on reg<761> PWM1/DCMP1 Power Down Control 0: Power down 1: Power on reg<762> PWM2/DCMP2 Power Down Control 0: Power down 1: Power on reg<764:763> PWM0/DCMP0 Positive Input Source Select 00: From ADC 01: From S2P 10: From FSM0 11: 8-bit user defined (selected through matrix) reg<766:765> PWM1/DCMP1 Positive Input Source Select 00: From ADC 01: From S2P 10: From FSM0 11: 8-bit user defined (selected through matrix) reg<768:767> PWM2/DCMP2 Positive Input Source Select 00: From ADC 01: From S2P 10: From FSM0 11: 8-bit user defined (selected through matrix) reg<769> PWM0/DCMP0 Negative Input Source Select 0: From CNT1 ramp (for PWM) 1: 8-bit user defined (selected through matrix) reg<770> PWM1/DCMP1 Negative Input Source Select 0: From CNT1 ramp (for PWM) 1: 8-bit user defined (selected through matrix) reg<771> PWM2/DCMP2 Negative Input Source Select 0: From CNT1 ramp (for PWM) 1: 8-bit user defined (selected through matrix) reg<779:772> PWM/DCMP NVM data pwm_reg0 reg<787:780> PWM/DCMP NVM data pwm_reg1 reg<795:788> PWM/DCMP NVM data pwm_reg2 reg<803:796> PWM/DCMP NVM data pwm_reg3 reg<804> S2P or P2S Mode Select 0: Serial in parallel output to chip internal 1: Parallel in from chip serial out reg<805> SPI clock /Osc external clock Enable 0: Disable 1: Enable reg<806> Bypass the PIN2 0: PIN2 edge active 1: PIN2 high active Bit Address Register Definition

000-0046400-109 Page 86 of 89 SLG46400 reg<807> PIN2 edge detect mode 0: Rising edge 1: Falling edge reg<808> PIN2 reset Enable 0: Disable 1: Enable reg<810:809> Pipe number select from connection matrix out <48> 00: 3 pipes 01: 5 pipes 10: 7 pipes 11: 11 pipes reg<811> ACMP0 Low Bandwidth Enable 0: Disable 1: Enable reg<812> ACMP1 Low Bandwidth Enable 0: Disable 1: Enable reg<813> ADC power down control register when reg<815:814>=”01”. ADC power power is controlled by reg<813>, otherwise, ADC power down is controlled by connection matrix out<3>. When reg <814> = “1”: 0: ADC power on 1: ADC power down <815:814> ADC/PWM/OSC power down source selection 00: ADC power down from matrix out <3>, PWM power down from register 01: PWM power down from matrix out <3>, ADC power down from reg <813> 10: ADC & PWM power down from matrix out <3> 11: OSC power down from matrix out <3>, PWM & ADC power down from register reg<816> Oscillator Dividers control 0:Oscillator Dividers Enabled 1: Oscillator Dividers Diasbled reg<817> DFF0/LATCH0 output polarity control 0: Do not invert output polarity 1: Invert output polarity reg<818> PWM1 Mode Select 0: Down to 0% 1: Up to 100% reg<819> PWM2 Mode Select 0: Down to 0% 1: Up to 100% reg<821:820> Pipe number select from connection matrix out <49> 00: 2 pipes 01: 4 pipes 10: 8 pipes 11: 12 pipes reg<829:822> 8-bit pattern id reg<830> NVM data read Disable 0: Disable 1: Enable reg<831> NVM power down 0: None 1: Power Down Bit Address Register Definition

000-0046400-109 Page 87 of 89 SLG46400

27.0 Revision History

6/3/2015 1.09 Fixed package name Tape and Reel Spec 10/8/2014 1.08 Fixed typo in Tape and Reel Spec 8/6/2014 1.07 Fixed ESD information 11/21/2013 1.06 Added ESD Ratings and MSL to Absolute Maximum Conditions 9/24/2013 1.05 Updated conditions for VAIR in Electriical Characteristics for clarity. Updated Section 13 to clarify Counter functionality. 7/16/2013 1.04 Fixed Typo in Section 15.1 Diagram 06/04/2013 1.03 Updated 3bit LUT and 4bit LUT Standard Digital Functions tables 02/05/2013 1.02 SLG46400 Rev. B: Updated ADC Functional Diagram (Figure 3) Updated ACMP0 IN+ source selection information and ACMP0 Functional Diagram (Sec- tion 10.1 and Figure 8) Updated ACMP0 Register Settings (reg<735> and reg<739>) Corrected FSM0 and FSM1 UP/DOWN operation descriptions (Sections 13.7 and 13.9, Figures 19 and 21) Added Frequency Dividers Control function description (Section 16.3) Updated RC OSC Register Settings Updated RC OSC Typical Frequency Selection, Table 24 Updated Register Definition (RC OSC Frequency Control, reg<586:583>) Updated Register Definition (ACMP0 IN+ Source Selection, reg<739, 735>) Updated Register Definition (RC OSC Dividers Control, reg<816>) 11/19/2012 1.01 Updated Electrical Characteristics Table (VIL values) Fixed typo in Section 10.9 (less than or equal sign) 9/19/2012 1.0 Fixed typo in Section 10.9 Description 7/27/2012 0.92 Fixed typo in Electrical Characteristics table Updated Section 12.2 for clarification 7/16/2012 0.91 Editorial changes for clarification and typo fixes throughout Renamed Signal names to match GreenPAK Designer Software Moved Bi-Directional Pin example to Section 21.0 6/27/2012 0.9 Updated Electrical Characteristics Table Corrected Section 9.4 regarding 2-Channel Selection (Pin 12 instead of Pin 2) Updated Section10.0 to clarify ACMP power down operation and fixed ACMP hysteresis values in Sections 6.4, 10.9, and 10.10.1 Updated Section 12.10 regarding poiwer down control Renamed Section 16.0 RC Oscillator to Clock Management and clarified operation and updated block diagram. Updated Section 13.12 to include short pulse delay time diagrams. Removed Application Example regarding time delay Updated register map 6/8/2012 0.85 Updated Section 13.4 Added note regarding minimum value of the register setting for the CNT/DLY cells 3/20/2012 0.84 Editorial changes for clarification and typo fixes throughout 1/27/2012 0.83 Editorial changes for clarification and typo fixes throughout Updated Section 9.9 ADC Outputs Updated Section 13.1 Counter Functionality Updated Section 13.7 and 13.9 regarding FSM Operation Updated Recommended Soldering Profile information 12/5/2011 0.82 Added Recommended Soldering Profile information 11/3/2011 0.81 Added Bi-Directional Pin Information 9/19/2011 0.8 Production release 9/18/2011 0.53 General updates

000-0046400-109 Page 88 of 89 SLG46400 10/20/2010 0.1 Preliminary datasheet Date Version Change

000-0046400-109 Page 89 of 89 SLG46400

28.0 Silego Website & Support

28.1 Silego Technology Website

Silego Technology provides online support via our website at http://www.silego.com/.This web site is used as a means to make files and information easily available to customers. For more information regarding Silego GreenPAK and other Silego Green products, please visit: http://greenpak.silego.com/ http://greenfet.silego.com/ http://greenpak2.silego.com/ http://greenfet2.silego.com/ http://greenclk.silego.com/ Products are also available for purchase directly from Silego at the Silego Online Store at http://store.silego.com/.

28.2 Silego Technical Support

Datasheets and errata, application notes and example designs, user guides, and hardware support documents and the latest software releases are available at the Silego website or can be requested directly at info@silego.com. For specific GreenPAK design or applications questions and support please send email requests to GreenPAK@silego.com Users of Silego products can receive assistance through several channels:

28.2.1 Contact Your Local Sales Representative

Customers can contact their local sales representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. More information regarding your lo cal representative is available at the Silego website or send a request to info@silego.com

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Silego can be contacted directly via e-mail at info@silego.com or user submission form, located at the following weblink: http://support.silego.com/

28.3 Other Information

The latest Silego Technology press releases, listing of seminars and events, listings of world wide Silego Technology offices and representatives are all available at http://www.silego.com/ THIS PRODUCT HAS BEEN DESIGNED AND QUALIF IED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. SILEGO TECHNOLO GY DOES NOT ASSUME ANY LIABILI TY ARISING OUT OF SUCH APPLI - CATIONS OR USES OF ITS PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE.