SLG46170V

2 manufacturer specifications

Personal Computers and Servers

Manufacturer variants: 2

Selected specification: Dialog Semiconductor

Documents: 2

Request Quote Download Datasheet Read online HTML view

Compare manufacturer specifications More from Dialog Semiconductor Browse S parts

Manufacturer Specifications

Compare SLG46170V variants.

Select a manufacturer to view its specifications, local PDF, and searchable HTML text.

2 manufacturers / 2 documents

Manufacturer	Series	Package	Documents	Available	Select specification
Dialog Semiconductor	-	-	1	PDF HTML	Viewing
Renesas Technology Corp	-	-	1	PDF HTML	View spec

Online Datasheet

Read the Dialog Semiconductor document online.

DATASHEET SEARCH SITE

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 87

Technical content

Features

Logic & Mixed Signal Circuits
Highly Versatile Macrocells
Read Back Protection (Read Lock)
1.8V (±5%) to 5V (±10%) Supply
Operating Temperature Range: -40°C to 85°C
RoHS Compliant / Halogen-Free
14-pin STQFN: 2 x 2.2 x 0.55 mm, 0.4 mm pitch

Applications

Personal Computers and Servers
PC Peripherals
Consumer Electronics
Data Communications Equipment
Handheld and Portable Electronics Pin Configuration GND GPIO GPIO GPIO GPIO 11GPI VDD 1 14-pin STQFN (Top View) GPIO GPIO 14 13 GPIO GPIO GPIO GPIO GPIO 5 Pin4 GPIO Programmable Delay RC Oscillator Pin 5 GPIO Pin 1 VDD Pin 2 GPI Pin 3 GPIO Pin 14 GPIO Pin 13 GPIO FILTER_0 FILTER_1 Additional Logic Functions Look Up Tables (LUTs) Counters/Delay Generators CNT0 CNT1 2-bit LUT2_1 3-bit LUT3_3 2-bit LUT2_2 3-bit LUT3_0 3-bit LUT3_2 3-bit LUT3_1 3-bit LUT3_5 3-bit LUT3_7 3-bit LUT3_6 Combination Function Macrocells 2-bit LUT2_0 or DFF4 3-bit LUT3_8 or Pipe Delay CNT2 CNT3 CNT4 CNT5 CNT6 CNT7 D Flip Flops (DFF) / Latches DFF0 DFF1 DFF2 DFF3 DFF5 DFF6 2-bit LUT2_5 2-bit LUT2_4 3-bit LUT3_4 3-bit LUT3_3 4-bit LUT4_0 3-bit LUT3_9 Pin 6 GPIO Pin 7 GPIO Pin 9 GND Pin 8 GPIO Pin 12 GPIO Pin 11 GPIO Pin 10 GPIO

000-0046170-103 Page 1 of 86 SLG46170

1.0 Overview

The SLG46170 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macrocells of the SLG46170. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The macrocells in the device include the following:

Fifteen Combinatorial Look Up Tables (LUTs)
Five 2-bit LUTs
Nine 3-bit LUTs
One 4-bit LUT
Two Combination Function Macrocells
One Selectable FF/Latch or 2-bit LUT
One Selectable Pipe Delay or 3-bit LUT
Pipe Delay – 16 stage / 3 output
Eight Counter / Delay Generators (CNT/DLY)
One 14-bit delay/counter
One 14-bit delay/counter with external clock/reset
Four 8-bit delays/counters
Two 8-bit delays/counters with external clock/reset
Six D Flip-Flop / Latches (DFF)
Pipe Delay – 16 sta ge/3 output (Part of Combination Function Macrocell)
Programmable Delay
Additional Logic Functions – 2 Deglitch Filters
RC Oscillator (RC OSC)

000-0046170-103 Page 2 of 86 SLG46170

2.0 Pin Description

2.1 Functional and Programming Pin Description

Pin # Pin Name Function Programming Function

1 VDD Power Supply Power Supply

2 GPI General Purpose Input V PP (Programming Voltage)

3 GPIO General Purpose I/O N/A

4 GPIO General Purpose I/O N/A

5 GPIO General Purpose I/O N/A

6 GPIO General Purpose I/O N/A

7 GPIO General Purpose I/O N/A

8 GPIO General Purpose I/O N/A

9 GND Ground Ground

10 GPIO General Purpose I/ O Programming Mode Control

11 GPIO General Purpose I/O Programming ID Pin

12 GPIO General Purpose I/O Programming SDIO Pin

13 GPIO General Purpose I/O Programming SRDWB Pin

14 GPIO General Purpose I/O or External Clock Programming SCL Pin

3.0 User Programmability

long as it remains powered and can be re-written as needed to facilitate rapid design changes. Once the design is finalized, the design file can be forwarded to Silego to integrate into the production process. Figure 1. Steps to create a custom Silego GreenPAK device

000-0046170-103 Page 4 of 86 SLG46170

4.0 Ordering Information

SLG46170VTR 14-pin STQFN - Tape and Reel (3k units)

000-0046170-103 Page 5 of 86 SLG46170

5.0 Electrical Specifications

5.1 Absolute Maximum Conditions

5.2 Electrical Characteristics (1.8 V ±5% VDD) Parameter Min. Max. Unit Supply voltage on VDD relative to GND -0.5 7 V DC Input voltage G ND - 0.5 VDD + 0.5 V Maximum Average or DC Current (Through pin) Push-Pull 1x -- 8 mA Push-Pull 2x -- 10 OD 1x -- 8 OD 2x -- 12 OD 4x -- 25 Current at Input Pin -1.0 1.0 mA Storage Temperature Range -65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1300 -- V Moisture Sensitivity Level 1 Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 1.71 1.80 1.89 V TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VIH HIGH-Level Input Voltage Logic Input 1.100 -- -- V Logic Input with Schmitt Trigger 1.270 -- -- V Low-Level Logic Input 0.980 -- -- V VIL LOW-Level Input Voltage Logic Input -- -- 0.690 V Logic Input with Schmitt Trigger -- -- 0.440 V Low-Level Logic Input -- -- 0.520 V ILKG Input Leakage (Absolute Value) -- 1 1000 nA VOH HIGH-Level Output Voltage Push-Pull 1X, Open Drain PMOS 1X, IOH = 100 A 1.690 1.789 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 100 A 1.700 1.794 -- V VOL LOW-Level Output Voltage Push-Pull 1X, IOL= 100 A -- 0.008 0.030 V Push-Pull 2X, IOL= 100 A -- 0.004 0.010 V Open Drain NMOS 1X, IOL= 100 A -- 0.005 0.020 V Open Drain NMOS 2X, IOL= 100 A -- 0.003 0.010 V Open Drain NMOS 4X, IOL= 100 A -- 0.003 0.004 V

000-0046170-103 Page 6 of 86 SLG46170 IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, VOH = VDD - 0.2 1.066 1.703 -- mA Push-Pull 1X, Open Drain PMOS 1X, VOH = VDD - 0.2 2.216 3.406 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, VOL = 0.15 V 0.917 1.689 -- mA Push-Pull 2X, VOL = 0.15 V 1.834 3.378 -- mA Open Drain NMOS 1X, VOL = 0.15 V 1.375 2.534 -- mA Open Drain NMOS 2X, VOL = 0.15 V 2.750 5.068 -- mA Open Drain NMOS 4X Drive, VOL = 0.15 V 5.500 10.136 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) TSU Startup Time from VDD rising past 1.35 V -- 0.3 -- ms PONTHR Power On Threshold V DD Level Required to Start Up the Chip 1.096 1.353 1.528 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 0.759 0.933 1.125 V Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11, 12, 13 and 14 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046170-103 Page 7 of 86 SLG46170 5.3 Electrical Characteristics (3.3V ±10% VDD) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3.0 3.3 3.6 V TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VIH HIGH-Level Input Voltage Logic Input 1.780 -- -- V Logic Input with Schmitt Trigger 2.130 -- -- V Low-Level Logic Input 1.130 -- -- V VIL LOW-Level Input Voltage Logic Input -- -- 1.210 V Logic Input with Schmitt Trigger -- -- 0.950 V Low-Level Logic Input -- -- 0.690 V ILKG Input Leakage (Absolute Value) -- 1 1000 nA VOH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, IOH = 3 mA 2.735 3.120 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 3 mA 2.870 3.210 -- V VOL LOW-Level Output Voltage Push-Pull 1X, IOL= 3 mA -- 0.130 0.228 V Push-Pull 2X, IOL= 3 mA -- 0.060 0.108 V Open Drain NMOS 1X, IOL= 3 mA -- 0.080 0.147 V Open Drain NMOS 2X, IOL= 3 mA -- 0.040 0.080 V Open Drain NMOS 4X, IOL= 3 mA -- 0.027 0.034 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, VOH = 2.4 V 6.045 12.080 -- mA Push-Pull 2X, Open Drain PMOS 2X, VOH = 2.4 V 11.522 24.160 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, VOL = 0.4 V 4.875 8.244 -- mA Push-Pull 2X, VOL = 0.4 V 9.750 16.488 -- mA Open Drain NMOS 1X, VOL = 0.4 V 7.313 12.370 -- mA Open Drain NMOS 2X, VOL = 0.4 V 14.541 24.740 -- mA Open Drain NMOS 4X Drive, VOL = 0.4 V 25.801 49.480 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) TSU Startup Time from VDD rising past 1.35 V -- 0.3 -- ms

000-0046170-103 Page 8 of 86 SLG46170 PONTHR Power On Threshold V DD Level Required to Start Up the Chip 1.096 1.353 1.528 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 0.759 0.933 1.125 V Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11, 12, 13 and 14 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046170-103 Page 9 of 86 SLG46170

5.4 Electrical Characteristics (5 V ±10% VDD)

Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VIH HIGH-Level Input Voltage Logic Input 2.640 -- -- V Logic Input with Schmitt Trigger 3.160 -- -- V Low-Level Logic Input 1.230 -- -- V VIL LOW-Level Input Voltage Logic Input -- -- 1.840 V Logic Input with Schmitt Trigger -- -- 1.510 V Low-Level Logic Input -- -- 0.780 V ILGK Input leakage (Absolute Value) -- 1 1000 nA VOH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, IOH = 5 mA 4.190 4.780 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 5 mA 4.320 4.890 -- V VOL LOW-Level Output Voltage Push-Pull 1X, IOL= 5 mA -- 0.157 0.270 V Push-Pull 2X, IOL= 5 mA -- 0.076 0.130 V Open Drain NMOS 1X, IOL= 5 mA -- 0.102 0.180 V Open Drain NMOS 2X, IOL= 5 mA -- 0.051 0.110 V Open Drain NMOS 4X, IOL= 5 mA -- 0.035 0.045 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, VOH = 2.4 V 22.080 34.040 -- mA Push-Pull 2X, Open Drain PMOS 2X, VOH = 2.4 V 41.690 68.080 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, VOL = 0.4 V 7.215 11.580 -- mA Push-Pull 2X, VOL = 0.4 V 13.831 23.160 -- mA Open Drain NMOS 1X, VOL = 0.4 V 10.820 17.380 -- mA Open Drain NMOS 2X, VOL = 0.4 V 17.343 34.760 -- mA Open Drain NMOS 4X Drive, VOL = 0.4 V 30.964 69.520 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) TSU Startup Time from VDD rising past 1.35 V -- 0.3 -- ms

000-0046170-103 Page 10 of 86 SLG46170 PONTHR Power On Threshold V DD Level Required to Start Up the Chip 1.096 1.353 1.528 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 0.759 0.933 1.125 V Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11, 12, 13 and 14 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

5.5 IDD Estimator

5.6 Timing Estimator

5.7 Typical Counter/Delay Offset Measurements

Table 1. Typical Current estimated for each macrocell. Table 2. Typical Delay estimated for each macrocell. Table 3. Typical Counter/Delay Offset Measurements.

5.8 Expected Delays and Widths

5.9 Typical Pulse Width Performance

Table 4. Expected Delays and Widths for Programmable Delay (typical). Table 5. Typical Pulse Width Performance.

5.10 OSC Specifications

Table 6. 25 kHz RC OSC frequency limits at T = 25 °C Table 7. 25 kHz RC OSC frequency error (error calculated relative to nominal value) at T = 25 °C

5.10.2 OSC Power On delay

Table 8. 2 MHz RC OSC frequency limits at T = 25 °C Table 9. 2 MHz RC OSC frequency error (error calculated relative to nominal value) at T = 25 °C Table 10. Oscillators Power On delay at T=(-40..+85) °C, DLY/CNT Counter data = 100; RC OSC power setting: "Auto

000-0046170-103 Page 16 of 86 SLG46170

6.0 Summary of Macrocell Function

6.1 I/O Pins

Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
Open Drain Outputs
Push Pull Outputs
10 k /100 k/1 Mpull-up/pull-down resistors
40 mA Open Drain 4X Drive output

6.2 Connection Matrix

Digital matrix for circuit co nnections based on user design

6.3 Combinational Logic Look Up Tables (LUTs – 15 total)

Five 2-bit Lookup Tables
Nine 3-bit Lookup Tables
One 4-bit Lookup Tables

6.4 Combination Function Macrocell (2 total)

One Selectable FF/Latch or 2-bit LUT
One Selectable Pipe Delay or 3-bit LUT

6.5 Delays/Counters (8 total)

Two 14-bit delay/counter s: Range 1-16384 clock cycles
Four 8-bit delays/counters : Range 1-255 clock cycles
Two 8-bit delays/coun ters with external clock/reset: Range 1-255 clock cycles

6.6 Digital Storage Elements (6 total)

Six D Flip-Flops or Latches

6.7 Pipe Delay (Part of Combination Function Macrocell)

16 stage / 3 output
One 1 stage fixed output
Two 1-16 stage se lectable outputs.

6.8 Programmable Delay

150 ns/300 ns/450 ns /600 ns @ 3.3 V
Includes Edge Detection function

6.9 Additional Logic Functions (2 total)

Two Deglitch filter macrocells

6.10 RC Oscillator

25 kHz and 2 MHz s electable frequency
First stage divider (4): OSC /1, OSC/2, OSC/4, and OSC/8
Second stage divider (5): OSC/1, OSC/4, selectable (OSC/8, OSC /12, OSC/24, or OSC/64), OSC/3, and additional OSC/3 (from selectable output)

000-0046170-103 Page 17 of 86 SLG46170

7.0 I/O Pins

The SLG46170 has a total of 12 mu lti-function I/O pins which ca n function as either a user defined Input or Output, as well as serving as a special function (s uch as outputting the voltage r eference), or serving as a signal for programming of the on-chi p Non Volatile Memory (NVM). Normal Mode pin definitions are as follows:

Pin 2: general purpose input
Pin 3: general purpo se input or output
Pin 4: general purpo se input or output
Pin 5: general purpo se input or output
Pin 6: general purpo se input or output
Pin 7: general purpo se input or output
Pin 8: general purpo se input or output
Pin 10: general purpose input or output
Pin 11: general purpose input or output
Pin 12: general purpose input or output
Pin 13: general purpose input or output
Pin 14: general purpose input or output or external clock Programming Mode pin definitions are as follows;
Pin 1: Vdd power supply
Pin 2: Vpp programming voltage
Pin 9: ground
Pin 10: programming mode control
Pin 11: progr amming ID pin
Pin 12: programming SDIO pin
Pin 13: programming SRDWB pin
Pin 14: programming SCL pin Of the 12 user defined I/O pins on the SLG46170, all but one of the pins (Pin 2) can serve as both digital input and digital output. Pin 2 can only serve as a digital input pin.

7.1 Input Modes

Each I/O pin can be configured as a digital input pin with/with out buffered Schmitt Trigger, or can also be configured as a lo w voltage digital input.

7.2 Output Modes

Pins 3, 4, 5, 6, 7, 8, 10, 11, 12, 13 and 14 can all be configured as digital output pins.

7.3 Pull Up/Down Resistors

All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors are 10 k, 100 k and 1 M. In the case of Pin 2, the resistors are fixed to a pull-down configuration. In the case of all other I/O pins, the internal resistors can be configured as either pull-up or pull-downs.

7.4 I/O Register Settings

7.4.1 PIN 2 Register Settings

Table 11. PIN 2 Register Settings

7.4.2 PIN 3 Register Settings

7.4.3 PIN 4 Register Settings

Table 12. PIN 3 Register Settings Table 13. PIN 4 Register Settings

7.4.4 PIN 5 Register Settings

7.4.5 PIN 6 Register Settings

Table 14. PIN 5 Register Settings Table 15. PIN 6 Register Settings

7.4.6 PIN 7 Register Settings

Table 16. PIN 7 Register Settings

7.4.7 PIN 8 Register Settings

7.4.8 PIN 10 Register Settings

Table 17. PIN 8 Register Settings Table 18. PIN 10 Register Settings

7.4.9 PIN 11 Register Settings

7.4.10 PIN 12 Register Settings

Table 19. PIN 11 Register Settings Table 20. PIN 12 Register Settings

7.4.11 PIN 13 Register Settings

7.4.12 PIN 14 Register Settings

Table 21. PIN 13 Register Settings Table 22. PIN 14 Register Settings

7.5 GPI IO Structure

7.5.1 GPI IO Structure (for Pin 2)

Figure 2. PIN 2 GPI IO Structure Diagram

7.6 Register OE IO Structure

7.6.1 Register OE IO Structure (for Pins 3, 4, 5, 6, 7, 10, 11, 12, 13, 14)

Figure 3. Register OE IO Structure Diagram

7.7 Register OE IO Structure with 4X Drive

7.7.1 Register OE IO Structure with 4X Drive (for Pin 8)

Figure 4. Register OE IO with 4X Drive Structure Diagram

8.0 Connection Matrix

8.1 Matrix Input Table

Table 23. Matrix Input Table

0 G N D 000000

2 R e s e r v e d 000010

7 R e s e r v e d 000111

18 DFF/LATCH_0 Q output w ith nRST or nSET 0 1 0 0 1 0

19 DFF/LATCH_0 nQ output with nRST or nSET 0 1 0 0 1 1

20 DFF/LATCH_1 output wit h nRST or nSET 0 1 0 1 0 0

21 DFF/LATCH_2 output wit h nRST or nSET 0 1 0 1 0 1

22 DFF/LATCH_3 output wit h nRST or nSET 0 1 0 1 1 0

23 DFF/LATCH_5 output 0 1 0 1 1 1

24 DFF/LATCH_6 output 0 1 1 0 0 0

25 LUT4_0 output 0 1 1 0 0 1

26 LUT3_0 output 0 1 1 0 1 0

27 LUT3_1 output 0 1 1 0 1 1

28 LUT3_2 output 0 1 1 1 0 0

29 LUT3_3 output 0 1 1 1 0 1

30 LUT3_4 output 0 1 1 1 1 0

31 LUT3_5 output 0 1 1 1 1 1

32 LUT3_6 output 1 0 0 0 0 0

33 LUT3_7 output 1 0 0 0 0 1

34 LUT3_8 output (1st stage pipe 1 delay output) 1 0 0 0 1 0

35 LUT3_9 output 1 0 0 0 1 1

36 LUT2_0 output (DFF/ LATCH_4 output) 1 0 0 1 0 0

37 LUT2_1 output 1 0 0 1 0 1

38 LUT2_2 output 1 0 0 1 1 0

39 LUT2_3 output 1 0 0 1 1 1

40 LUT2_4 output 1 0 1 0 0 0

41 LUT2_5 output 1 0 1 0 0 1

44 Edge detect output 1 0 1 1 0 0

45 Programmable delay with edge detector 1 0 1 1 0 1

50 R e s e r v e d 110010

51 R e s e r v e d 110011

52 R e s e r v e d 110100

53 R e s e r v e d 110101

62 Reset_core (POR) a s m a t r i x i n p u t 111110

8.2 Matrix Output Table

Table 24. Matrix Output Table

9.0 Combinatorial Logic

please see Section 10.0 Combination Function Macrocells. logic devices (AND, NAND, OR, NOR, XOR, XNOR). Figure 6. 2-bit LUTs

created within each of the four 2-bit LUT logic cells. Table 30. 2-bit LUT Standard Digital Functions Table 25. 2-bit LUT1 Truth Table. Table 26. 2-bit LUT2 Truth Table. Table 27. 2-bit LUT3 Truth Table. Table 28. 2-bit LUT4 Truth Table. Table 29. 2-bit LUT5 Truth Table.

Figure 7. 3-bit LUTs

Table 31. 3-bit LUT0 Truth Table. Table 32. 3-bit LUT1 Truth Table. Table 33. 3-bit LUT2 Truth Table. Table 34. 3-bit LUT3 Truth Table. Table 35. 3-bit LUT4 Truth Table. Table 36. 3-bit LUT5 Truth Table. Table 37. 3-bit LUT6 Truth Table. Table 38. 3-bit LUT7 Truth Table.

created within each of the six3-bit LUT logic cells. Table 40. 3-bit LUT Standard Digital Functions. Table 39. 3-bit LUT9 Truth Table.

created within the 4-bit LUT logic cell. Figure 8. 2-bit LUTs Table 41. 4-bit LUT0 Truth Table. Table 42. 4-bit LUT Standard Digital Functions.

10.0 Combination Function Macrocells

One macrocell that can serve as either 2-bit LUT or as D Flip Flop
One macrocell that can serve as either 3-bit LUT or as Pipe Delay Inputs/Outputs for the two combination function macrocells are configured from the connection matrix with specific logic functions being defined by the state of NVM bits. When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user def ined function, including the f ollowing standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR, Inverter, Buffer and MUX for 3-bit and 4-bit LUTs). 10.1 2-Bit LUT or D Flip Flop Macrocells There is one macrocell that can serve as either a 2-bit LUT or as a D Flip Flop. When used to implement LUT function, the 2-bit LUT takes in two input signals from the connection matrix and p roduce a single output, which goes back into the connection matrix. When used to implement D Flip Flop function, the two input signals from the connection matrix go to the data (D) and clock (clk) inputs for the Flip Flop, with the output going back to the connection matrix. 10.1.1 2-Bit LUT or D Flip Flop Macrocells Used as 2-Bit LUTs

Figure 9. 2-bit LUT0 or DFF4 Table 43. 2-bit LUT0 Truth Table.

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay. single output, which goes back into the connection matrix. by reg <664:661> for OUT0 and reg <668:665> for OUT1. The 4-input mux is used to control the selection of the amount of delay. be the total time delay of the Pipe Delay logic cell. Table 44. DFF4 Register Settings

Figure 10. 3-bit LUT8 or Pipe Delay

16 Flip-FlopsIN

Table 46. Pipe Delay Register Settings Table 45. 3-bit LUT8 Truth Table.

11.0 Digital Storage Elements (DFFs/Latches)

additional input from the matrix that can serve as a nSet or nReset function to the macrocell. Section 10.1 2-Bit LUT or D Flip Flop Macrocells for the description of this Combination Function macrocell. Figure 11. DFF/Latch0

11.1 Initial Polarity Operations

Figure 17. DFF Polarity Operations

12.0 Counters/Delay Generators (CNT/DLY)

previous (N-1) CNT/DLY macrocell, to implement longer count / delay circuits. Figure 18. CNT/DLY0

Figure 25. CNT/DLY7

12.1 CNT/DLY Timing Diagrams

Figure 26. Delay Mode Timing Figure 27. Counter Mode Timing

12.2 CNT/DLY0 Register Settings

12.3 CNT/DLY1 Register Settings

12.4 CNT/DLY2 Register Settings

Table 47. CNT/DLY0 Register Settings Table 48. CNT/DLY1 Register Settings Table 49. CNT/DLY2 Register Settings

12.5 CNT/DLY3 Register Settings

12.6 CNT/DLY4 Register Settings

Table 50. CNT/DLY3 Register Settings Table 51. CNT/DLY4 Register Settings

12.7 CNT/DLY5 Register Settings

12.8 CNT/DLY6 Register Settings

Table 52. CNT/DLY5 Register Settings Table 53. CNT/DLY6 Register Settings

12.9 CNT/DLY7 Register Settings

Table 54. CNT/DLY7 Register Settings

000-0046170-103 Page 59 of 86 SLG46170

13.0 Pipe Delay (PD)

The SLG46170 has a pipe delay logic cell that is shared with the 3-bit LUT8 in one of the Combination Function macrocells. The user can select one of these functions to use in a design, but not both. Please see Section 10.2 3-Bit LUT or Pipe Delay Macrocell for the description of this Combination Function macrocell.

14.0 Programmable Delay / Edge Detector

period. See the timing diagrams below for further information. Note: The input signal must be longer than the delay, otherwise it will be filtered out.

14.1 Programmable Delay Timing Diagram - Edge Detector Output

Figure 28. Programmable Delay Figure 29. Edge Detector Output

Note: For delays and widths refer to Table 4.

14.2 Programmable Delay Timing Diagram - Glitch Filtering For Edge Detector Output

Figure 30. Delayed Edge Detector Output Figure 31. Glitch Filtering for Edge Detector Output

14.3 Programmable Delay Register Settings

Table 55. Programmable Delay Register Settings

15.0 Additional Logic Functions

The SLG46170 has two additional logic functions that serve as deglitch filters.

15.1 Deglitch Filter

Figure 32. Deglitch Filter

000-0046170-103 Page 64 of 86 SLG46170

16.0 RC Oscillator (RC Osc)

16.1 RC Oscillator Overview

The SLG46170 has two internal RC oscillators, one that runs at 25 kHz and one that runs at 2 MHz. The user can select one of these fundamental frequencies for the RC OSC Macrocell, or the fundamental frequency can also come from an external clock input (PIN 14). There are two divider stages that allow the user flexibility for introducing clock signals on various Connection Matrix Input lines. The first stage divider allows the selection of /1, /2, /4 or /8 divide down frequency from the fundamental. The second stage divider has an input of one frequency from the first stage divider, and outputs five different frequencies on Connection Matrix Input lines <45>, <46>, <47>, <48>, and <49>. See Figure 33 below for details of the frequencies for each of these five Connection Matrix Inputs. If PWR DOWN input of oscillator is LOW, the oscillator will be turned on. If PWR DOWN input of oscillator is HIGH the oscillator will be turned off. The PWR DOWN signal has the highest priority. The user can select two OSC POWER MODEs (reg<707>):

I f AUTO POWER ON <0> is selected, the OSC will run when the SLG46170 is powered on.
I f FORCE POWER ON <1> is selected, the OSC will run only when any macrocell that uses OSC is powered on. OSC can be turned on by:
Register control (force power on)
Delay mode, when delay requires OSC
C N T

16.2 RC OSC Block Diagram

Figure 33. RC OSC Block Diagram

16.3 Oscillator Power On delay

Note 1: OSC power mode: "Auto Power On”. Note 2: ‘OSC enable’ signal appears when any macrocell that uses OSC is powered on. Figure 34. Oscillator Startup Diagram Figure 35. RC Oscillator Maximum Power On Delay vs. VDD at room temperature

2 MHz

16.4 Oscillator Accuracy

Note: OSC power setting: Force Power On; Clock to matrix input - enable; Bandgap: turn on by register - enable. Note: For more information see section 5.10 OSC Specifications. Figure 36. RC Oscillator Frequency vs. Temperature, RC OSC0=2 MHz Figure 37. RC Oscillator Frequency vs. Temperature, RC OSC0=25 kHz

17.0 Power On Reset (POR)

17.1 POR Overview

17.2 POR Timing Diagram

Figure 38. POR Timing Diagram

000-0046170-103 Page 69 of 86 SLG46170

18.0 Appendix A - SLG46170 Register Definition

Address Signal Function Register Bit Definition reg<5:0> Reserved reg<11:6> Matrix Out PIN3 Digital Output Source reg<17:12> Matrix Out PIN4 Digital Output Source reg<23:18> Matrix Out PIN5 Digital Output Source reg<29:24> Matrix Out PIN6 Digital Output Source reg<35:30> Reserved reg<41:36> Matrix Out PIN7 Digital Output Source reg<47:42> Matrix Out PIN8 Dig ital Output Source (4X Drive) reg<53:48> Matrix Out Input for del ay0 or Counter0 external clock reg<59:54> Matrix Out Input for d elay1 or counter1 reset input reg<65:60> Matrix Out Input for Counter1 external clock or delay1 external clock reg<71:66> Matrix Out Input for d elay2 or counter2 reset input reg<77:72> Matrix Out Input for Counter2 external clock or delay2 external clock reg<83:78> Matrix Out Input for d elay3 or counter3 reset input reg<89:84> Matrix Out Input for Counter3 external clock or delay3 external clock reg<95:90> Matrix Out Input for del ay4 or Counter4 external clock reg<101:96> Matrix Out Input for delay5 or Counter5 external cloc k reg<107:102> Matrix Out Input for d elay6 or Counter6 external clock reg<113:108> Matrix Out Input for d elay7 or Counter7 external clock reg<119:114> Matrix Out Clock Input of DFF0 reg<125:120> Matrix Out Data Input of DFF0 reg<131:126> Matrix Out nRST (nSET) of DFF0 reg<137:132> Matrix Out Clock Input of DFF1 reg<143:138> Matrix Out Data Input of DFF1 reg<149:144> Matrix Out nRST (nSET) of DFF1 reg<155:150> Matrix Out Clock Input of DFF2 reg<161:156> Matrix Out Data Input of DFF2 reg<167:162> Matrix Out nRST (nSET) of DFF2 reg<173:168> Matrix Out Clock Input of DFF3 reg<179:174> Matrix Out Data Input of DFF3 reg<185:180> Matrix Out nRST (nSET) of DFF3 reg<191:186> Matrix Out Clock Input of DFF5 reg<197:192> Matrix Out Data Input of DFF5 reg<203:198> Matrix Out Clock Input of DFF6 reg<209:204> Matrix Out Data Input of DFF6 reg<215:210> Matrix Out In0 of LUT4_0 reg<221:216> Matrix Out In1 of LUT4_0 reg<227:222> Matrix Out In2 of LUT4_0

000-0046170-103 Page 70 of 86 SLG46170 reg<233:228> Matrix Out In3 of LUT4_0 reg<239:234> Matrix Out In0 of LUT3_0 reg<245:240> Matrix Out In1 of LUT3_0 reg<251:246> Matrix Out In2 of LUT3_0 reg<257:252> Matrix Out In0 of LUT3_1 reg<263:258> Matrix Out In1 of LUT3_1 reg<269:264> Matrix Out In2 of LUT3_1 reg<275:270> Matrix Out In0 of LUT3_2 reg<281:276> Matrix Out In1 of LUT3_2 reg<287:282> Matrix Out In2 of LUT3_2 reg<293:288> Matrix Out In0 of LUT3_3 reg<299:294> Matrix Out In1 of LUT3_3 reg<305:300> Matrix Out In2 of LUT3_3 reg<311:306> Matrix Out In0 of LUT3_4 reg<317:312> Matrix Out In1 of LUT3_4 reg<323:318> Matrix Out In2 of LUT3_4 reg<329:324> Matrix Out In0 of LUT3_5 reg<335:330> Matrix Out In1 of LUT3_5 reg<341:336> Matrix Out In2 of LUT3_5 reg<347:342> Matrix Out In0 of LUT3_6 reg<353:348> Matrix Out In1 of LUT3_6 reg<359:354> Matrix Out In2 of LUT3_6 reg<365:360> Matrix Out In0 of LUT3_7 reg<371:366> Matrix Out In1 of LUT3_7 reg<377:372> Matrix Out In2 of LUT3_7 reg<383:378> Matrix Out In0 of L UT3_8 or Input of Pipe delay reg<389:384> Matrix Out In1 of L UT3_8 or nRST of Pipe delay reg<395:390> Matrix Out In2 of L UT3_8 or Clock of Pipe delay reg<401:396> Matrix Out In0 of LUT3_9 reg<407:402> Matrix Out In1 of LUT3_9 reg<413:408> Matrix Out In2 of LUT3_9 reg<419:414> Matrix Out In0 of L UT2_0 or Clock Input of DFF4 reg<425:420> Matrix Out In1 of L UT2_0 or Data Input of DFF4 reg<431:426> Matrix Out In0 of LUT2_1 reg<437:432> Matrix Out In1 of LUT2_1 reg<443:438> Matrix Out In0 of LUT2_2 reg<449:444> Matrix Out In1 of LUT2_2 reg<455:450> Matrix Out In0 of LUT2_3 reg<461:456> Matrix Out In1 of LUT2_3 reg<467:462> Matrix Out In0 of LUT2_4 reg<473:468> Matrix Out In1 of LUT2_4 reg<479:474> Matrix Out In0 of LUT2_5 reg<485:480> Matrix Out In1 of LUT2_5 Register Bit Address Signal Function Register Bit Definition

000-0046170-103 Page 71 of 86 SLG46170 reg<491:486> Matrix Out Input for programmable delay & edge detec tor reg<497:492> Matrix Out Power down for osc reg<503:498> Reserved reg<509:504> Reserved reg<515:510> Reserved reg<521:516> Reserved reg<527:522> Matrix Out Pin10 Digital Output Source reg<533:528> Matrix Out Pin11 Digital Output Source reg<539:534> Matrix Out Pin12 Digital Output Source reg<545:540> Matrix Out Pin13 Digital Output Source reg<551:546> Matrix Out Pin14 Digital Output Source reg<557:552> Matrix Out Input of filter_0 reg<563:558> Matrix Out Input of filter_1 reg<569:564> Matrix Out Reserved reg<571:570> Reserved reg<575:572> LUT2_0 data or reg<572> DFF4 or Latch select 0: DFF function 1: Latch function reg<573> DFF4 output select 0: Q output 1: nQ output reg<574> DFF4 initial polarity select 0: Low 1: High reg<579:576> LUT2_1 data reg<583:580> LUT2_2 data reg<587:584> LUT2_3 data reg<591:588> LUT2_4 data reg<595:592> LUT2_5 data reg<596> LUT2_0 or DFF4 select 0: LUT2_0 1: DFF4 reg<604:597> LUT3_0 data reg<612:605> LUT3_1 data reg<620:613> LUT3_2 data reg<628:621> LUT3_3 data reg<636:629> LUT3_4 data reg<644:637> LUT3_5 data reg<652:645> LUT3_6 data reg<660:653> LUT3_7 data reg<668:661> LUT3_8 data or pipe number select reg<664: 661>: OUT0 select reg<668: 665>: OUT1 select reg<676:669> LUT3_9 data Register Bit Address Signal Function Register Bit Definition

000-0046170-103 Page 72 of 86 SLG46170 reg<692:677> LUT4_0 data reg<693> DFF0 or Latch Select 0: DFF function 1: Latch function reg<694> DFF0 nRST/nSET select 0: nRST from matrix out 1: nSET from matrix out reg<695> DFF0 Initial polarity select 0: Low 1: High reg<696> DFF1 or Latch Select 0: DFF function 1: Latch function reg<697> DFF1 output select (Q or nQ) 0: Q output 1: nQ output reg<698> DFF1 nRST/nSET select 1: nSET from matrix out 0: nRST from matrix out reg<699> DFF1 Initial polarity select 0: Low 1: High reg<700> DFF2 or Latch Select 0: DFF function 1: Latch function reg<701> DFF2 output select (Q or nQ) 0: Q output 1: nQ output reg<702> DFF2 nRST/nSET select 1: nSET from matrix out 0: nRST from matrix out reg<703> DFF2 Initial polarity select 0: Low 1: High reg<704> DFF3 or Latch Select 0: DFF function 1: Latch function reg<705> DFF3 output select (Q or nQ) 0: Q output 1: nQ output reg<706> DFF3 nRST/nSET select 1: nSET from matrix out 0: nRST from matrix out reg<707> DFF3 Initial polarity select 0: Low 1: High reg<708> DFF5 or Latch Select 0: DFF function 1: Latch function reg<709> DFF5 output select (Q or nQ) 0: Q output 1: nQ output reg<710> DFF5 Initial polarity select 0: Low 1: High reg<711> DFF6 or Latch Select 0: DFF function 1: Latch function reg<712> DFF6 output select (Q or nQ) 0: Q output 1: nQ output reg<713> DFF6 Initial polarity select 0: Low 1: High reg<714> Counter/Delay0 mode select 0: Delay Mode 1: Counter Mode Register Bit Address Signal Function Register Bit Definition

000-0046170-103 Page 73 of 86 SLG46170 reg<717:715> Counter/delay0 Clock Source Select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter 7 Overflow reg<731:718> Counter0 Control Data /Delay0 Time Control 1-16384: ( delay time = (counter control data +2) /freq) reg<733:732> Delay0 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges reg<734> Counter/Delay1 mode select 0: Delay Mode 1: Counter Mode reg<737:735> Counter/delay 1 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter 0 Overflow reg<751:738> Counter1 Control Data /Delay1 Time Control 1-16384: ( delay time = (counter control data +2) /freq) reg<753:752> Delay1 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for delay & counter reset) 01: Delay on falling edge only (for delay & counter reset) 10: Delay on rising edge only (for delay & counter reset) 11: No delay on either falling or rising edges / high level reset for counter mode reg<754> Counter/Del ay2 Mode selection 0: Delay Mode 1: Counter Mode reg<757:755> Counter/delay 2 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter 1 Overflow reg<765:758> Counter2 Control Data /Delay2 Time Control 1-256: (de lay time = (counter control data +2) /freq) reg<767:766> Delay2 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for delay & counter reset) 01: Delay on falling edge only (for delay & counter re- set) 10: Delay on rising edge only (for delay & counter re- set) 11: No delay on either falling or rising edges / high level reset for counter mode reg<768> Counter/Del ay3 Mode selection 0: Delay Mode 1: Counter Mode Register Bit Address Signal Function Register Bit Definition

000-0046170-103 Page 74 of 86 SLG46170 reg<771:769> Counter/delay 3 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter 2 Overflow reg<779:772> Counter3 Control Data /Delay3 Time Control 1-256: (de lay time = (counter control data +2) /freq) reg<781:780> Delay3 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for delay & counter reset) 01: Delay on falling edge only (for delay & counter reset) 10: Delay on rising edge only (for delay & counter reset) 11: No delay on either falling or rising edges / high level reset for counter mode reg<782> Counter/Delay4 Mode Selection 0: Delay Mode 1: Counter Mode reg<785:783> Counter/delay 4 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter 3 Overflow reg<793:786> Counter4 Control Data /Delay4 Time Control 1-256: (de lay time = (counter control data +2) /freq) reg<795:794> Delay4 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges reg<796> Counter/Delay5 Mode Selection 0: Delay Mode 1: Counter Mode reg<799:797> Counter/delay5 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter 4 Overflow reg<807:800> Counter5 Control Data /Delay5 Time Control 1-256: (de lay time = (counter control data +2) /freq) reg<809:808> Delay5 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges reg<810> Counter/Delay6 Mode Selection 0: Delay Mode 1: Counter Mode Register Bit Address Signal Function Register Bit Definition

000-0046170-103 Page 75 of 86 SLG46170 reg<813:811> Counter/delay6 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter 5 Overflow reg<821:814> Counter6 Control Data /Delay6 Time Control 1-256: (de lay time = (counter control data +2) /freq) reg<823:822> Delay6 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges reg<824> Counter/Delay7 Mode Selection 0: Delay Mode 1: Counter Mode reg<827:825> Counter/Delay7 Mode Selection (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter 6 Overflow reg<841:828> Counter7 Control Data /Delay7 Time Control 1-16384:(d elay time = (counter control data +2)/freq reg<843:842> Delay7 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges <845:844> PIN2 mode control 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved <847:846> PIN2 pull down resistor value selection 00: floating 01: 10 K 10: 100 K 11: 1 M <850:848> Reserved <852:851> Reserved <853> Reserved <854> Reserved <857:855> PIN3 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved <859:889> PIN3 pull up/down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M <860> PIN3 pull up/dow n resistor select 0: pull down resistor enable 1: pull up resistor enable Register Bit Address Signal Function Register Bit Definition

000-0046170-103 Page 76 of 86 SLG46170 <861> PIN3 driver strength selection 0: 1X 1: 2X <864:862> PIN4 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved <866:865> PIN4 pull up/down resistor value selection 00: floating 01: 10 K 10: 100 K 11: 1 M <867> PIN4 pull up/dow n resistor select 0: pull down resistor enable 1: pull up resistor enable <868> PIN4 driver strength selection 0: 1X 1: 2X <871:869> PIN5 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved <873:872> PIN5 pull up/down resistor value selection 00: floating 01: 10 K 10: 100 K 11: 1 M <874> PIN5 pull up/dow n resistor select 0: pull down resistor enable 1: pull up resistor enable <875> PIN5 driver strength selection 0: 1X 1: 2X <878:876> PIN6 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved <880:879> PIN6 pull up/down resistor value selection 00: floating 01: 10 K 10: 100 K 11: 1 M <881> PIN6 pull up/dow n resistor select 0: pull down resistor enable 1: pull up resistor enable <882> PIN6 driver strength selection 0: 1X 1: 2X <885:883> Reserved <887:886> Reserved <888> Reserved Register Bit Address Signal Function Register Bit Definition

000-0046170-103 Page 77 of 86 SLG46170 <889> Reserved <892:890> PIN7 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved <894:893> PIN7 pull up/down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M <895> PIN7 pull up/dow n resistor select 0: pull down resistor enable 1: pull up resistor enable <896> PIN7 driver strength selection 0: 1X 1: 2X <899:897> PIN8 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved <901:900> PIN8 pull up/down resistor value selection 00: floating 01: 10 K 10: 100 K 11: 1 M <902> PIN8 pull up/dow n resistor select 0: pull down resistor enable 1: pull up resistor enable <903> PIN8 driver strength selection 0: 1X 1: 2X <904> PIN8 4X Drive (4X, NMO S open drain) selection 0: 4X Drive off 1: 4X Drive on (if <899: 897> = 101) <907:905> Reserved <909:908> Reserved <910> Reserved <911> Reserved <912> Reserved <915:913> Reserved <917:916> Reserved <918> Reserved <919> Reserved <922:920> Reserved <924:923> Reserved <925> Reserved Register Bit Address Signal Function Register Bit Definition

000-0046170-103 Page 78 of 86 SLG46170 <926> Reserved <929:927> Reserved <931:930> Reserved <932> Reserved <933> Reserved <936:934> PIN10 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved <938:937> PIN10 pull up/down resistor value selection 00: floating 01: 10 K 10: 100 K 11: 1 M <939> PIN10 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable <940> PIN10 driver strength selection 0: 1X 1: 2X <943:941> PIN11 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved <945:944> PIN11 pull up/down r esistor value selection 00: floating 01: 10 K 10: 100 K 11: 1 M <946> PIN11 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable <947> PIN11 driver strength selection 0: 1X 1: 2X <950:948> PIN12 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved <952:951> PIN12 pull up/down resistor value selection 00: floating 01: 10 K 10: 100 K 11: 1 M <953> PIN12 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable Register Bit Address Signal Function Register Bit Definition

000-0046170-103 Page 79 of 86 SLG46170 <954> PIN12 driver strength selection 0: 1X 1: 2X <957:955> PIN13 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved <959:558> PIN13 pull up/down resistor value selection 00: floating 01: 10 K 10: 100 K 11: 1 M <960> PIN13 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable <961> PIN13 driver strength selection 0: 1X 1: 2X <964:962> PIN14 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved <966:965> PIN14 pull up/down resistor value selection 00: floating 01: 10 K 10: 100 K 11: 1 M <967> PIN14 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable <968> PIN14 driver strength selection 0: 1X 1: 2X reg<969> Force RC oscillator on 0: Auto Power on 1: Force Power on reg<970> RC Oscillator frequency control 0: 25 K 1: 2 M reg<971> Reserved reg<973:972> Internal Oscillator frequency divider control 00: OSC/8 01: OSC/12 10: OSC/24 11: OSC/64 reg<974> External Clock Source Select 0: Internal Oscillator 1: External Clock from Pin20 reg<976:975> Osc clock pre-divider 00: Div1 01: Div2 10: Div4 11: Div8 reg<977> LUT3_8 or pipe delay output select 0: Lut3_8 1: 1 pipe delay output reg<978> Pipe delay OUT1 polarity select bit 0: non-inverted 1: inverted Register Bit Address Signal Function Register Bit Definition

000-0046170-103 Page 80 of 86 SLG46170 reg<979> NVM dat a read disable 0: Disable (program data can be read) 1: Enable (Program data cannot be read) reg<980> NVM power down 0: None (or programming enable) 1: Power Down (or programming disable) reg<981> GPIO quick charge enable 0: Disable 1: Enable reg<983: 982> Reserved reg<991:984> Reserved reg<999:992> 8-bit Pattern ID reg<1001:1000> Delay value select for programmable delay & edge de- tector (VDD 3.3V, typ) 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns reg<1003:1002> Select the edge mode of programmable delay & edge detector 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay reg<1004> Select edge de tector output mode 0: edge detector output 1: delayed edge detector output reg<1005> Select polar ity of filter_0 output 0: non-inverted 1: inverted reg<1006> Select polar ity of filter_1 output 0: non-inverted 1: inverted reg<1007> Reserved reg<1013:1008 > Reserved reg<1014> Reserved reg<1015> Reserved reg<1023:1016> Reserved Register Bit Address Signal Function Register Bit Definition

000-0046170-103 Page 81 of 86 SLG46170

19.0 Package Top Marking System Definition

000-0046170-103 Page 82 of 86 SLG46170

20.0 Package Drawing and Dimensions

STQFN 14L 2 x 2.2mm 0.4P COL Package JEDEC MO-220, Variation WECE

000-0046170-103 Page 83 of 86 SLG46170

21.0 Tape and Reel Specifications

21.1 Carrier Tape Drawing and Dimensions

# of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm]per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 14L 2x2.2 mm 0.4P COL 14 2 x 2.2 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W STQFN 14L 2x2.2 mm 0.4P COL Refer to EIA-481 specification

000-0046170-103 Page 84 of 86 SLG46170

22.0 Recommended Landing Pattern

23.0 Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow prof ile based on package volume of 2.42 mm 3 (nominal). More information can be found at www.jedec.org.

000-0046170-103 Page 85 of 86 SLG46170

24.0 Revision History

10/10/2017 1.03 Updated Electrical Spec Fixed typos 7/5/2017 1.02 Fixed typos Updated Silego Website & Support Updated Section Programmable Delay / Edge Detector Updated Electrical Spec 10/20/2016 1.01 Removed references to GPAK families 9/28/2016 1.00 Prod uction Release

000-0046170-103 Page 86 of 86 SLG46170 Silego Website & Support Silego Technology Website Silego Technology provides online support via our website at http://www.silego.com/.This website is used as a means to make files and information easily available to customers. For more information regarding Silego Green products, please visit our website. Our Green product lines feature: GreenPAK: Programmable Mixed Signal Matrix products GreenFET1 / GreenFET3 / HFET1: MOSFET Drivers and ultra-small, low RDSon Load Switches GreenCLK1 / GreenCLK2 / GreenCLK3: Crystal replacement technology Products are also available for purchase directly from Silego at the Silego Online Store at http://www.silego.com /buy/. Silego Technical Support Datasheets and errata, application notes and example designs, u ser guides, and hardware support documents and the latest software releases are available at the Silego website or can be requested directly at info@silego.com. For specific GreenPAK design or applications questions and support please send e-mail requests to GreenPAK@silego.com Users of Silego products can receive assistance through several channels: Contact Your Local Sales Representative Customers can contact their local sales representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. More information regarding your lo cal representative is available at the Silego website or send a request to info@silego.com Contact Silego Directly Silego can be contacted directly via e-mail at info@silego.com or user submission form, located at the following URL: http://support.silego.com/ Other Information The latest Silego Technology press releases, listing of seminars and events, listings of world wide Silego Technology offices and representatives are all available at http://www.silego.com/ THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. SILEGO TECHNOLOGY DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICA- TIONS OR USES OF ITS PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTI

Selected Specification

Dialog Semiconductor SLG46170V overview.

Change manufacturer

Summary

Personal Computers and Servers

Description

Personal Computers and Servers

Source title SLG46170V Datasheet(PDF) - Dialog Semiconductor

Related Parts

More parts from the same family.

Browse manufacturer