SLG46140

2 manufacturer specifications

GreenPAK Programmable Mixed-signal Matrix

Manufacturer variants: 2

Selected specification: Dialog Semiconductor

Documents: 2

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Online Datasheet

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Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 170

Technical content

Features

Logic & Mixed Signal Circuits
Highly Versatile Macrocells
1.8V (±5%) to 5V (±10%) Supply
Operating Temperatur e Range: -40°C to 85°C
RoHS Compliant / Halogen-Free
Pb-Free: 1.6 x 2.0 x 0.55 mm, 0.4 mm pitch Pin Configuration

Applications

The extensive list of integrated components included in the SLG 46140 can be used to implement these and many other functions, often in combination.

Ambient Light Detect
Battery Charge Control
Fan Control
Hall Effect Drive
LED Control
Level Shift
One-Shot Detect
Optical Encode
Over Voltage Protect
Port Detection
Power Sequencing
Sensor Interface
Signal De-Glitch
Signal Delay
System Reset
Thermal Management
Voltage Level Detect GPIO GPIO GPIO GPIO GPIO 11GPI VDD 1 14-pin STQFN (Top View) GND GPIO 14 13 GPIO GPIO GPIO GPIO GPIO 5

000-0046140-109 Page 1 of 169 SLG46140 Block Diagram 3-bit LUT3_7 or CNT3 Vref Programmable Delay RC Oscillator Pin 1 VDD Pin 2 GPI Pin 3 GPIO Pin 4 GPIO Pin 14 GPIO Pin 13 GPIO Pin 6 GPIO Pin 7 GPIO Pin 10 GPIO Pin 9 GPIO Pin 12 GPIO Pin 11 GPIO ACMP0 ACMP1 FILTER_0 Additional Logic Functions Look Up Tables (LUTs) Counters/Delay Generators CNT0 CNT1 2-bit LUT2_0 3-bit LUT3_0 2-bit LUT2_1 2-bit LUT2_3 Combination Function Macrocells 2-bit LUT2_4 or DFF0 2-bit LUT2_5 or DFF1 3-bit LUT3_6 or Pipe Delay 3bit LUT3_5 or DFF3 3-bit LUT3_4 or DFF2 Pin 8 GND Pin 5 GPIO DFF/Latches DFF4 DFF5 2-bit LUT2_2 3-bit LUT3_3 3-bit LUT3_2 3-bit LUT3_1 4-bit LUT4_1 or CNT2 4bit LUT4_0 or PGEN Digital Comparators/PWMs DCMP0 DCMP1 DCMP2 POR PWR DET DAC1 Ring Oscillator LF Oscillator DAC0 8-bit SAR ADCPGA SPI

000-0046140-109 Page 2 of 169 SLG46140

1.0 Overview

In addition to the integrated analog and digital components, the SLG46140 comprises an internal connection matrix and one-time programmable NVM. By programming the NVM, using the easy-to-use GreenPAK development tools, the designer configures the connection matrix, I/O Pins, and integrated components of the SLG46140. The SLG46140 includes the following analog and digital resources:

8-bit Successive Approximation Register Analog-to-Digital Conv erter (SAR ADC)
ADC 3-bit Programmable Gain Amplifier (PGA)
Two Digital-to-Analog Converters (DAC)
Two Analog Comparators (ACMP)
Voltage Reference (VREF)
Eight Combinatorial Lookup Tables (LUTs)
Four 2-bit LUTs
Four 3-bit LUTs
Nine Combination Function Macrocells
One 14-bit Delay/Counter (Wake-Sleep Control)
Two Selectable DFF/Latch or 2-bit LUTs
Two Selectable DFF/Latch or 3-bit LUTs
One Selectable 16-Stage / 3-Output Pipe Delay or 3-bit LUT
One 8-bit Delay/Counter/Finite State Machine
One 14-bit Delay/Counter/Finite State Machine
One Selectable Pattern Generator or 4-bit LUT
Three Digital Comparators/Pulse Width Modulators (DCMPs /PWMs) w/ Selectable Deadband
Three Counters/Delays (CNT/DLY)
One 14-bit Delay/Counter/Finite State Machine
One 14-bit Delay/Counter
One 8-bit Delay/Counter
Two D Flip-flops/Latches
Programmable Delay w/ Edge Detection
Three Internal Oscillators
Low-Frequency
R i n g
RC 25 kHz and 2 MHz
Power-On-Reset (POR)
Slave SPI
One Bandgap

000-0046140-109 Page 3 of 169 SLG46140

2.0 Pin Description

2.1 Functional Pin Description

Pin # Pin Name Function

1 VDD Power Supply

2 GPI General Purpose Input

3 GPIO General Purpose I/O or ADC Vref_IO

4 GPIO General Purpose I/O or Analog Comparator 0 (-) / PGA_OUT

5 GPIO General Purpose I/O or Analog Comparator 1 (-)

6 GPIO General Purpose I/O or PGA(+)

7 GPIO General Purpose I/O or PGA(-)

9 GPIO General Purpose I/O or ACMP1(+)

10 GPIO General Purpose I/O or ACMP0(+)

11 GPIO General Purpose I/O or AIN MUX

12 GPIO General Purpose I/O

13 GPIO General Purpose I/O

14 GPIO General Purpose I/O

3.0 User Programmability

code (.gpx file) is forwarded to Silego to integrate into a production process. Figure 1. Steps to create a custom Silego GreenPAK device

000-0046140-109 Page 5 of 169 SLG46140

4.0 Ordering Information

SLG46140VTR 14-pin STQFN - Tape and Reel (3k units)

000-0046140-109 Page 6 of 169 SLG46140

5.0 Electrical Specifications

5.1 Absolute Maximum Conditions

5.2 Electrical Characteristics (1.8V ±5% VDD) Parameter Min. Max. Unit Supply voltage on VDD relative to GND -0.5 7 V DC Input voltage GND - 0.5 VDD + 0.5 V Maximum Average or DC Current (Through pin) Push-Pull 1x -- 12 mA Push-Pull 2x -- 21 Push-Pull 4x -- 43 OD 1x -- 18 OD 2x -- 45 OD 4x -- 72 Current at Input Pin -1.0 1.0 mA Storage Temperature Range -65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 500 -- V Moisture Sensitivity Level 1 Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 1.71 1.80 1.89 V IQ Quiescent Current Static Inputs and Outputs, all macrocells disabled -- 0.08 -- A TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VACMP ACMP Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.1 V VIH HIGH-Level Input Voltage Logic Input 1.100 -- V DD V Logic Input with Schmitt Trigger 1.270 -- V DD V Low-Level Logic Input 0.980 -- V DD V VIL LOW-Level Input Voltage Logic Input 0 -- 0.690 V Logic Input with Schmitt Trigger 0 -- 0.440 V Low-Level Logic Input 0 -- 0.520 V VHYS Schmitt Trigger Hysteresis Voltage Logic Input with Schmitt Trigger 0.273 0.413 0.553 V

000-0046140-109 Page 7 of 169 SLG46140 ILKG (Absolute Value) ACMP Input Leakage Vin = 0 V -- 0.39 2.39 nA Vin = VDD -- 0.26 1.29 nA PGA Input Leakage Vin = 0 V -- 0.04 0.18 nA Vin = VDD -- 0.12 0.65 nA Logic Input without Schmitt Trigger (Floating) Leakage Vin = 0 V -- 0.04 0.34 nA Vin = VDD -- 1.55 71.77 nA Logic Input with Schmitt Trigger (Floating) Leakage Vin = 0 V -- 0.04 0.39 nA Vin = VDD -- 1.55 72.26 nA Low-Level Logic Input (Floating) Leakage Vin = 0 V -- 0.04 0.33 nA Vin = VDD -- 1.55 72.39 nA VOH HIGH-Level Output Voltage Push-Pull 1X, Open Drain PMOS 1X, IOH = 100 A 1.670 1.788 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 100 A 1.679 1.792 -- V Push-Pull 4X, Open Drain PMOS 4X, IOH = 100 A 1.700 1.798 -- V VOL LOW-Level Output Voltage Push-Pull 1X, IOL= 100 A -- 0.010 0.020 V Push-Pull 2X, IOL= 100 A -- 0.007 0.010 V Push-Pull 4X, IOL= 100 A -- 0.004 0.009 V Open Drain NMOS 1X, IOL= 100 A -- 0.007 0.010 V Open Drain NMOS 2X, IOL= 100 A -- 0.002 0.010 V Open Drain NMOS 4X, IOL= 100 A -- 0.001 0.004 V IOH HIGH-Level Output Pulse Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, VOH = VDD - 0.2 1.053 1.690 -- mA Push-Pull 2X, Open Drain PMOS 2X, VOH = VDD - 0.2 2.069 3.390 -- mA Push-Pull 4X, Open Drain PMOS 4X, VOH = VDD - 0.2 4.007 7.070 -- mA IOL LOW-Level Output Pulse Current (see Note 1) Push-Pull 1X, VOL = 0.15 V 0.760 1.420 -- mA Push-Pull 2X, VOL = 0.15 V 1.520 2.840 -- mA Push-Pull 4X, VOL = 0.15 V 4.430 6.122 -- mA Open Drain NMOS 1X, VOL = 0.15 V 1.530 2.840 -- mA Open Drain NMOS 2X, VOL = 0.15 V 3.060 5.680 -- mA Open Drain NMOS 4X, VOL = 0.15 V 10.504 14.987 -- mA Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046140-109 Page 8 of 169 SLG46140 IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T VO Maximal Voltage Applied to any PIN in High- Impedance State VDD V TSU Startup Time (see Note 3) from VDD rising past PON THR 0.671 1.179 4.999 ms PONTHR Power On Threshold VDD Level Required to Start Up the Chip 0.961 1.310 1.657 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 0.875 1.109 1.287 V RPUP Pull Up Resistance 1 M Pull Up 896.67 1075.81 1337.85 kΩ 100 k Pull Up 93.13 111.06 132.78 kΩ 10 k Pull Up 11.10 12.95 15.30 kΩ R PDWN Pull Down Resistance 1 M Pull Down 660.68 1074.06 1287.58 kΩ 100 k Pull Down 93.29 111.06 132.78 kΩ 10 k Pull Down 10.90 12.75 15.51 kΩ Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6 and 7 are connected to one side, pins 9,10, 11, 12, 13 and 14 to another. Note 3: VDD ramp rising speed must be less than 0.6 V/µs after power on. Violating this specification may cause chip to restart. Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046140-109 Page 9 of 169 SLG46140 5.3 Electrical Characteristics (3.3V ±10% VDD) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3.0 3.3 3.6 V IQ Quiescent Current Static Inputs and Outputs (when all macrocells that require internal RC OSC or bandgap are inactive) -- 0.16 -- A TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VACMP ACMP Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 1.780 -- V DD V Logic Input with Schmitt Trigger 2.130 -- V DD V Low-Level Logic Input 1.130 -- V DD V VIL LOW-Level Input Voltage Logic Input 0 -- 1.210 V Logic Input with Schmitt Trigger 0 -- 0.950 V Low-Level Logic Input 0 -- 0.690 V VHYS Schmitt Trigger Hysteresis Voltage Logic Input with Schmitt Trigger 0.346 0.486 0.625 V ILKG (Absolute Value) ACMP Input Leakage Vin = 0 V -- 0.42 2.49 nA Vin = VDD -- 0.30 1.48 nA PGA Input Leakage Vin = 0 V -- 0.05 0.21 nA Vin = VDD -- 0.13 0.73 nA Logic Input without Schmitt Trigger (Floating) Leakage Vin = 0 V -- 0.05 0.39 nA Vin = VDD -- 1.47 67.45 nA Logic Input with Schmitt Trigger (Floating) Leakage Vin = 0 V -- 0.05 0.40 nA Vin = VDD -- 1.47 67.80 nA Low-Level Logic Input (Floating) Leakage Vin = 0 V -- 0.05 0.39 nA Vin = VDD -- 1.47 67.84 nA VOH HIGH-Level Output Voltage Push-Pull 1X, Open Drain PMOS 1X, IOH = 3 mA 2.722 3.102 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 3 mA 2.861 3.201 -- V Push-Pull 4X, Open Drain PMOS 4X, IOH = 3 mA 2.927 3.248 -- V

000-0046140-109 Page 10 of 169 SLG46140 VOL LOW-Level Output Voltage Push-Pull 1X, IOL= 3 mA -- 0.151 0.280 V Push-Pull 2X, IOL= 3 mA -- 0.079 0.130 V Push-Pull 4X, IOL= 3 mA -- 0.055 0.104 V Open Drain NMOS 1X, IOL= 3 mA -- 0.070 0.130 V Open Drain NMOS 2X, IOL= 3 mA -- 0.040 0.070 V Open Drain NMOS 4X, IOL= 3 mA -- 0.018 0.023 V IOH HIGH-Level Output Pulse Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, VOH = 2.4 V 5.770 11.151 -- mA Push-Pull 2X, Open Drain PMOS 2X, VOH = 2.4 V 11.278 21.750 -- mA Push-Pull 4X, Open Drain PMOS 4X, VOH = 2.4 V 21.458 40.903 -- mA IOL LOW-Level Output Pulse Current (see Note 1) Push-Pull 1X, VOL = 0.4 V 4.060 6.920 -- mA Push-Pull 2X, VOL = 0.4 V 8.130 13.840 -- mA Push-Pull 4X, VOL = 0.4 V 19.628 28.240 -- mA Open Drain NMOS 1X, VOL = 0.4 V 8.130 13.850 -- mA Open Drain NMOS 2X, VOL = 0.4 V 16.260 23.700 -- mA Open Drain NMOS 4X, VOL = 0.4 V 45.976 66.769 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T VO Maximal Voltage Applied to any PIN in High- Impedance State VDD V TSU Startup Time (see Note 3) from VDD rising past PON THR 0.504 0.927 3.092 ms PONTHR Power On Threshold VDD Level Required to Start Up the Chip 0.962 1.312 1.658 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 0.876 1.109 1.287 V RPUP Pull Up Resistance 1 M Pull Up 888.18 1075.30 1316.50 kΩ 100 k Pull Up 92.15 110.40 132.16 kΩ 10 k Pull Up 9.83 11.99 14.49 kΩ Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046140-109 Page 11 of 169 SLG46140 RPDWN Pull Down Resistance 1 M Pull Down 662.60 1074.47 1285.21 kΩ 100 k Pull Down 92.42 110.60 132.48 kΩ 10 k Pull Down 10.00 11.88 14.25 kΩ Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6 and 7 are connected to one side, pins 9,10, 11, 12, 13 and 14 to another. Note 3: VDD ramp rising speed must be less than 0.6 V/µs after power on. Violating this specification may cause chip to restart. Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046140-109 Page 12 of 169 SLG46140

5.4 Electrical Characteristics (5V ±10% VDD)

Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V IQ Quiescent Current Static Inputs and Outputs (when all macrocells that require internal RC OSC or bandgap are inactive) -- 0.25 -- A TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VACMP ACMP Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 2.901 -- V DD V Logic Input with Schmitt Trigger 3.254 -- V DD V Low-Level Logic Input 1.209 -- V DD V VIL LOW-Level Input Voltage Logic Input 0 -- 1.840 V Logic Input with Schmitt Trigger 0 -- 1.510 V Low-Level Logic Input 0 -- 0.780 V VHYS Schmitt Trigger Hysteresis Voltage Logic Input with Schmitt Trigger 0.443 0.618 0.792 V ILKG (Absolute Value) ACMP Input Leakage Vin = 0 V -- 0.70 3.30 nA Vin = VDD -- 0.38 1.84 nA PGA Input Leakage Vin = 0 V -- 0.25 1.05 nA Vin = VDD -- 0.17 0.91 nA Logic Input without Schmitt Trigger (Floating) Leakage Vin = 0 V -- 0.29 1.40 nA Vin = VDD -- 1.46 64.99 nA Logic Input with Schmitt Trigger (Floating) Leakage Vin = 0 V -- 0.29 1.40 nA Vin = VDD -- 1.45 65.16 nA Low-Level Logic Input (Floating) Leakage Vin = 0 V -- 0.29 1.40 nA Vin = VDD -- 1.45 66.16 nA VOH HIGH-Level Output Voltage Push-Pull 1X, Open Drain PMOS 1X, IOH = 5 mA 4.168 4.759 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 5 mA 4.330 4.878 -- V Push-Pull 4X, Open Drain PMOS 4X, IOH = 5 mA 4.405 4.932 -- V

000-0046140-109 Page 13 of 169 SLG46140 VOL LOW-Level Output Voltage Push-Pull 1X, IOL= 5 mA -- 0.193 0.330 V Push-Pull 2X, IOL= 5 mA -- 0.101 0.160 V Push-Pull 4X, IOL= 5 mA -- 0.071 0.135 V Open Drain NMOS 1X, IOL= 5 mA -- 0.090 0.160 V Open Drain NMOS 2X, IOL= 5 mA -- 0.050 0.080 V Open Drain NMOS 4X, IOL= 5 mA -- 0.021 0.030 V IOH HIGH-Level Output Pulse Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, VOH = 2.4 V 20.716 30.759 -- mA Push-Pull 2X, Open Drain PMOS 2X, VOH = 2.4 V 40.059 59.691 -- mA Push-Pull 4X, Open Drain PMOS 4X, VOH = 2.4 V 76.137 112.724 -- mA IOL LOW-Level Output Pulse Current (see Note 1) Push-Pull 1X, VOL = 0.4 V 6.010 9.730 -- mA Push-Pull 2X, VOL = 0.4 V 12.020 19.460 -- mA Push-Pull 4X, VOL = 0.4 V 26.150 37.191 -- mA Open Drain NMOS 1X, VOL = 0.4 V 12.030 19.460 -- mA Open Drain NMOS 2X, VOL = 0.4 V 24.060 38.920 -- mA Open Drain NMOS 4X, VOL = 0.4 V 60.071 86.737 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T VO Maximal Voltage Applied to any PIN in High- Impedance State VDD V TSU Startup Time (see Note 3) from VDD rising past PON THR 0.462 0.848 2.693 ms PONTHR Power On Threshold VDD Level Required to Start Up the Chip 0.963 1.314 1.659 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 0.877 1.109 1.288 V RPUP Pull Up Resistance 1 M Pull Up 884.96 1074.96 1306.99 kΩ 100 k Pull Up 91.90 110.17 131.96 kΩ 10 k Pull Up 8.98 11.64 14.55 kΩ Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046140-109 Page 14 of 169 SLG46140 RPDWN Pull Down Resistance 1 M Pull Down 667.10 1074.89 1287.81 kΩ 100 k Pull Down 92.03 110.34 132.21 kΩ 10 k Pull Down 9.45 11.55 14.05 kΩ Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6 and 7 are connected to one side, pins 9,10, 11, 12, 13 and 14 to another. Note 3: VDD ramp rising speed must be less than 0.6 V/µs after power on. Violating this specification may cause chip to restart. Symbol Parameter Condition/Note Min. Typ. Max. Unit

5.5 Typical Delay Estimated for Each Macrocell

Table 1. Typical Delay Estimated for Each Macrocell

000-0046140-109 Page 16 of 169 SLG46140 tpd Delay PDLY 1Cells delayed output Rising edge detect 192.15 -- 75.71 -- 48.65 -- ns tpd Delay PDLY 1Cells delayed output Fall- ing edge detect -- 195.73 -- 76.60 -- 49.42 ns tpd Delay PDLY 1Cells Rising ed ge detect 31.32 -- 12.33 -- 8.65 -- ns tpd Delay PDLY 1Cells Falling ed ge detect -- 35.52 -- 13.63 -- 9.36 ns tpd Delay PDLY 2Cells delayed output Both tpd Delay PDLY 2Cells delayed output Rising edge detect 359.61 -- 140.37 -- 88.92 -- ns tpd Delay PDLY 2Cells delayed output Fall- ing edge detect -- 362.93 -- 141.33 -- 89.66 ns tpd Delay PDLY 2Cells Rising ed ge detect 31.35 -- 12.33 -- 8.65 -- ns tpd Delay PDLY 2Cells Falling ed ge detect -- 35.49 -- 13.60 -- 9.37 ns tpd Delay PDLY 3Cells delayed output Both tpd Delay PDLY 3Cells delayed output Rising edge detect 518.35 -- 203.44 -- 128.36 -- ns tpd Delay PDLY 3Cells delayed output Fall- ing edge detect -- 522.00 -- 204.27 -- 129.16 ns tpd Delay PDLY 3Cells Rising ed ge detect 31.35 -- 12.33 -- 8.68 -- ns tpd Delay PDLY 3Cells Falling ed ge detect -- 35.60 -- 13.65 -- 9.37 ns tpd Delay PDLY 4Cells delayed output Both tpd Delay PDLY 4Cells delayed output Rising edge detect 685.08 -- 267.57 -- 168.46 -- ns tpd Delay PDLY 4Cells delayed output Fall- ing edge detect -- 688.67 -- 268.47 -- 169.54 ns tpd Delay PDLY 4Cells Rising ed ge detect 31.37 -- 12.35 -- 8.66 -- ns tpd Delay PDLY 4Cells Falling ed ge detect -- 35.73 -- 13.63 -- 9.35 ns tpd Delay PDLY Both edge delay Delayed tpd Delay PDLY Both edge delay Delayed tpd Delay PDLY Both edge delay Delayed tpd Delay PDLY Both edge delay Delayed tw Width PDLY 1Cells delayed output Both tw Width PDLY 1Cells delayed output Rising edge detect 348.80 -- 152.20 -- 110.80 -- ns tw Width PDLY 1Cells delayed output Fall- ing edge detect -- 349.93 -- 152.87 -- 111.39 ns Symbol Parameter Note VDD=1.8V VDD=3.3V VDD=5.0V Unit Rising Falling Rising Falling Rising Falling

000-0046140-109 Page 17 of 169 SLG46140 tw Width PDLY 1Cells Rising edge detect 344.67 -- 153.27 -- 111.95 -- ns tw Width PDLY 1Cells Falling edge detect -- 345.80 -- 153.73 -- 112.43 n s tw Width PDLY 2Cells delayed output Both tw Width PDLY 2Cells delayed output Rising edge detect 687.33 -- 301.93 -- 219.93 -- ns tw Width PDLY 2Cells delayed output Fall- ing edge detect -- 688.60 -- 302.47 -- 220.47 ns tw Width PDLY 2Cells Rising edge detect 693.00 -- 306.87 -- 223.87 -- ns tw Width PDLY 2Cells Falling edge detect -- 693.73 -- 307.33 -- 224.13 n s tw Width PDLY 3Cells delayed output Both tw Width PDLY 3Cells delayed output Rising edge detect 1034.33 -- 452.27 -- 329.20 -- ns tw Width PDLY 3Cells delayed output Fall- ing edge detect -- 1036.80 -- 453.27 -- 330.00 ns tw Width PDLY 3Cells Rising edge det ect 1036.73 -- 458.73 -- 334.47 -- n s tw Width PDLY 3Cells Falling ed ge detect -- 1038.73 -- 459.73 -- 335.13 ns tw Width PDLY 4Cells delayed output Both tw Width PDLY 4Cells delayed output Rising edge detect 1371.47 -- 601.13 -- 438.73 -- ns tw Width PDLY 4Cells delayed output Fall- ing edge detect -- 1373.80 -- 602.20 -- 439.73 ns tw Width PDLY 4Cells Rising edge det ect 1383.40 -- 611.67 -- 446.07 -- n s tw Width PDLY 4Cells Falling ed ge detect -- 1385.13 -- 612.60 -- 446.53 ns tpd Delay Digital Input without Schmitt trigger tpd Delay Digital Input without Schmitt trigger tpd Delay Digital Input without Schmitt trigger tpd Delay Digital Input without Schmitt trigger tpd Delay Digital Input without Schmitt trigger tpd Delay Digital Input with Schmitt Trigger -- tpd Delay Low Voltage Digital Input -- Push tpd Delay Digital Input without Schmitt trigger tpd Delay Digital Input without Schmitt trigger Symbol Parameter Note VDD=1.8V VDD=3.3V VDD=5.0V Unit Rising Falling Rising Falling Rising Falling

000-0046140-109 Page 18 of 169 SLG46140 tpd Delay Digital Input without Schmitt trigger tpd Delay Digital Input without Schmitt trigger -- Push Pull Z to 1 42.03 -- 15.61 -- 10.78 -- ns tpd Delay Digital Input without Schmitt trigger -- Push Pull Z to 0 -- 36.09 -- 13.83 -- 9.51 ns tpd Delay Digital Input without Schmitt Trig- tpd Delay Digital Input without Schmitt Trig- tpd Delay Digital Input without Schmitt Trig- Symbol Parameter Note VDD=1.8V VDD=3.3V VDD=5.0V Unit Rising Falling Rising Falling Rising Falling

5.6 Typical Current Consumption

Table 2. Typical Current Consumption

2 MHz; First Clock predivider by 16; Sample rate

2 MHz; First Clock predivider by 1; Sample rate

5.7 OSC Specifications

Table 3. 25 kHz RC OSC frequency limits Table 4. 25 kHz RC OSC frequency error (error calculated relative to nominal value)

Table 5. 2 MHz RC OSC frequency limits Table 6. 2 MHz RC OSC frequency error (error calculated relative to nominal value)

Table 7. 25 MHz Ring OSC Frequency Limits Table 8. 25 MHz Ring OSC Frequency Error (Error Calculated Relative to Nominal Value)

5.7.5 OSC Power On Delay

Table 9. 1.9 kHz LF OSC Frequency Limits Table 10. 1.9 kHz LF OSC Frequency Error (Error Calculated Relative to Nominal Value) Table 11. Oscillators Power On Delay at Room Temperature, RC OSC Power Setting: "Auto Power On", RC OSC Clock

5.8 ACMP Specifications

Table 12. ACMP Specifications

000-0046140-109 Page 25 of 169 SLG46140 VHYS Built-in Hysteresis VHYS = 25 mV VIL = Vin - VHYS/2 VIH = Vin + VHYS/2 LB - Enabled, LB - Disabled, T = 25°C 13.8 -- 33.2 mV VHYS = 50 mV VIL = Vin - VHYS VIH = VHYS LB - Enabled, T = 25°C 43.5 -- 58.5 mV LB - Disabled, T = 25°C 44.8 -- 54.1 mV VHYS = 200 mV VIL = Vin - VHYS VIH = VHYS LB - Enabled, T = 25°C 192.8 -- 210.5 mV LB - Disabled, T = 25°C 192.6 -- 205.8 mV VHYS = 25 mV VIL = Vin - VHYS/2 VIH = Vin + VHYS/2 LB - Enabled, LB - Disabled, VHYS = 50 mV VIL = Vin - VHYS VIH = VHYS LB - Enabled, LB - Disabled, VHYS = 200 mV VIL = Vin - VHYS VIH = VHYS LB - Enabled, LB - Disabled, Rsin Series Input Resistance PROP Propagation Delay, Response Time Low Bandwidth - Enable, Gain = 1, Overdrive = 5 mV Low to High, High to Low, Low Bandwidth - Disable, Gain = 1, Overdrive = 5 mV Low to High, High to Low, Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit

000-0046140-109 Page 26 of 169 SLG46140 G Gain error (including threshold and internal Vref error), T = (-40…+85)°C G = 1, VDD = 1.71 V Vre f = 50…1200 mV -- 1 -- G = 1, VDD = 3.3 V Vre f = 50…1200 mV -- 1 -- G = 1, VDD = 5.5 V Vre f = 50…1200 mV -- 1 -- Vref Internal Vref error, Vref = 1200 mV VDD = 1.8 V ± 5 % VDD = 3.3 V ± 10 % VDD = 5.0 V ± 10 % Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit

5.9 ADC Specifications (Including PGA)

Table 13. Single-Ended ADC Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, unless otherwise specified

Note: To ensure linear operation, absolute input voltage on each pin should not exceed VDD-0.5.

Table 14. Differential ADC Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, Vcm = 500 mV, unless otherwise specified

000-0046140-109 Page 30 of 169 SLG46140 Note 1: Vcm range is given for stable CMRR > 34 dB. Note 2: To ensure linear operation, absolute input voltage on each pin should not exceed VDD-0.5. DNL Differential Non-Linearity G = 1, 2, 4, 8, 16 -- ±0.5 LSB NOISE -- ±0.5 LSB Symbol Parameter Description/Note Conditions Min. Max. Unit

Table 15. Pseudo-Differential ADC Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, Vcm = 500 mV, unless otherwise Note 1: Vinn is given for convenience instead of Vcm. Note 2: Vinn range is given for stable CMRR > 34 dB. Note 3: To ensure linear operation, absolute input voltage on each pin should not exceed VDD-0.5.

5.10 PGA Specifications

Note 1: RTI - referred to input. Table 16. Single-Ended PGA Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, unless otherwise specified

Note 1: RTO - referred to output. Table 17. Differential PGA Operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, Vcm = 500 mV, unless otherwise specified

Note 1: RTO - referred to output. Table 18. Pseudo-Differential PGA operation, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V, Vinn = 500 mV, unless otherwise

Note 1: RTI - referred to input. in Table 19. are for reference only. Table 19. Differential or Pseudo-Differential PGA Operation, ADC - Power Down, T = (-40 to +85)°C, VDD = (1.71 to 5.5)V,

000-0046140-109 Page 36 of 169 SLG46140

6.0 Summary of Macrocell Function

6.1 I/O Pins

Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
Open Drain Out puts (x1, x2, x4)
Push Pull Outputs (x1, x2, x4)
Analog I/O
10 k /100 k/1 Mpull-up/pull-down resistors
40 mA Open Drain 4X Drive outpu t, Pin 9 and Pin 10 (depending on VDD)
Pins 3, 5, 7, 9, 10, 13, 14, 16, 18, 19 can be configured as bidirectional IO

6.2 Connection Matrix

Digital matrix for circuit co nnections based on user design

6.3 Analog-to-Digital Converter

8-bit, 100 kHz, Successive Approximation Register ADC
DNL < ± 0.5 LSB, INL < ± 3.4 LSB
VIN Range: (0..1)/G V
3-bit Programmable Gain Ampli fier with gain values of (1, 2, 4, 8,16X in differential mode, 1, 2, 4X in Pseudo-Differential mode and 0.25, 0.5, 1, 2, 4, 8x in single-ended mode)
SPI output format

6.4 Digital-to-Analog Converter

Two 8-bit Digital-to-An alog Converters 0 to 1 V

6.5 Analog Comparators (2 total)

Selectable hysteresis 0 mV/25 mV/50 mV/200 mV
Internal or external Vref
Selectable gain (1x, 0.5x, 0.33x, 0.25x)
Low bandwidth

6.6 Voltage Reference

Used for references on Analog Comparators
Can also be driven to external pins
50 mV to 1.2 V, wit h 50 mV resolution
Chopper stabilized output amplifier

6.7 Combinational Logic Look Up Tables (LUTs – 8 total)

Four 2-bit Lookup Tables
Four 3-bit Lookup Tables

6.8 Combination Function Macrocells (8 total)

Two Selectable DFF/Latch or 2-bit LUTs
Two Selectable DFF/Latch or 3-bit LUTs
One Selectable 16-Stage / 3-O utput Pipe Delay or 3-bit LUT
One Selectable CNT/DLY or 3-bit LUT
One Selectable CNT/DLY or 4-bit LUT
One Selectable Pattern Generator or 4-bit LUT

000-0046140-109 Page 37 of 169 SLG46140

6.9 Digital Comparators or PWM (3 total)

Three 8-bit 100 kHz P WMs or 10 MHz Digital Comparators Delays/Counters (2 total)
One 14-bit Delay/Counter: Range 1 – 16383 clock cycles
One 8-bit Delay/Counter : Range 1 – 255 clock cycles
Clock cycles can be sourced from External Clock Input or LF, Ring, or RC Oscillator
Two counters can function as FSM counters

6.10 Programmable Delay

150 ns/300 ns/450 ns/600 ns @ 3.3 V
Includes Edge Detection function

6.11 RC Oscillator

25 kHz and 2 MHz s electable frequency
Pre-divider (4): OSC/1, OSC/2, OSC/4, and OSC/8
Output to Matrix: OSC /1, OSC/2, OSC/3, OSC/4, OSC/8, OSC/12, OSC/24, OSC/64
Output to CNT/DLY/FSM/PWM_ramp: OSC/1, OSC/4, OSC/12, OSC/24, OSC/64
Output to ADC: OSC/1, OSC/16

6.12 Low Frequency (LF) Oscillator

1.9 kHz
OSC/1, OSC/2, OSC/4, OSC/16 dividers

6.13 Ring Oscillator

25 MHz
Post divider: OSC/1, O SC/4, OSC/8, OSC/16
Output to Matrix: OSC /1, OSC/2, OSC/3, OSC/4, OSC/8, OSC/12, OSC/24, OSC/64
Output to CNT/DLY/FSM/PWM_ramp: OSC/1, OSC/256
Output to ADC: OSC/1, OSC/16

6.14 Digital Storage Elements

DFFs/Latches

6.15 Slave SPI

Serial-to-Parallel: 8 and 16-bit modes
Parallel-to-Serial: 8 and 16-bit modes
Can be used as ADC buffer

000-0046140-109 Page 38 of 169 SLG46140

7.0 I/O Pins

The SLG46140 has a total of 12 general purpose I/O pins (GPIO) which can be configured as either Input or Output, some with special functions (such as outputting the Vref), or serving as a signal for programming of the on-chip NVM. Normal Mode pin definitions are as follows:

Pin 1: VDD Power Supply
Pin 2: General Purpose Input (GPI)
Pin 3: GPIO with Ou tput Enable (OE)
Pin 4: GPIO with OE, AC MP0(-) Input, PGA Output
Pin 5: GPIO with OE, ACMP1(-) Input
Pin 6: GPIO without OE, PGA(+)
Pin 7: GPIO with OE, PGA(-)
Pin 8: GND
Pin 9: GPIO with OE, 4x Drive Output, ACMP1(+) Input
Pin 10: GPIO, 4x Drive Output, ACMP0(+) Input
Pin 11: GPIO, ADC Channel Select
Pin 12: GPIO with OE
Pin 13: GPIO with OE
Pin 14: GPIO with OE Programming Mode pin definitions are as follows:
Pin 1: VDD Power Supply
Pin 2: VPP Programming Voltage
Pin 3: RTSB
Pin 10: Programming Mode Control
Pin 11: Programming ID
Pin 12: Programming SDIO
Pin 13: Programming SRDWB
Pin 14: Programming SCL

7.1 Input Modes

Each GPI, GPIO pin can be configured as a:

Digital input with/without buffered Schmitt Trigger
Low Voltage Digital Input (LVDI) Pin 2 can function as a RESET pin Analog Input
Pin 3 can function as an analog input for the ADC Vref
Pins 4, 5, 9, 10 c an function as analog inputs for the ACMPs
Pins 6 and 7 can fun ction as analog input for PGA(+) and PGA(-), respectively

7.2 Output Modes

Pins 3, 4, 5, 9, 12, 13, and 14 can be configured as a digital output with 1x/2x push pull, 1x/2x Open Drain NMOS, or 1x/2x 3-state output with output enable.

7.3 Pull Up/Down Resistors

Floating
10 kΩ
100 kΩ
1 M Ω The GPI pin (PIN2) can only be configured with pull down resistors with the same values.

7.4 I/O Register Settings

7.4.1 PIN 2 Register Settings

7.4.2 PIN 3 Register Settings

Table 20. PIN 2 Register Settings Table 21. PIN 3 Register Settings

7.4.3 PIN 4 Register Settings

7.4.4 PIN 5 Register Settings

Table 22. PIN 4 Register Settings Table 23. PIN 5 Register Settings

7.4.5 PIN 6 Register Settings

7.4.6 PIN 7 Register Settings

Table 24. PIN 6 Register Settings Table 25. PIN 7 Register Settings

7.4.7 PIN 9 Register Settings

7.4.8 PIN 10 Register Settings

Table 26. PIN 9 Register Settings Table 27. PIN 10 Register Settings

7.4.9 PIN 11 Register Settings

7.4.10 PIN 12 Register Settings

Table 28. PIN 11 Register Settings Table 29. PIN 12 Register Settings

7.4.11 PIN 13 Register Settings

7.4.12 PIN 14 Register Settings

Table 30. PIN 13 Register Settings Table 31. PIN 14 Register Settings

7.5 GPI Structure (for Pin 2)

Figure 2. PIN 2 GPI IO Structure Diagram

7.6 Matrix OE IO Structure

7.6.1 Matrix OE IO Structure (for Pins 3, 4, 5, 7, 12, 13, 14)

Figure 3. Matrix OE IO Structure Diagram

7.6.2 Matrix OE 4x Drive Structure (for Pin 9)

Figure 4. Matrix OE IO 4x Drive Structure Diagram

7.7 Register OE IO Structure

7.7.1 Register OE IO Structure (for Pins 6, 11)

Figure 5. Register OE IO Structure Diagram

7.7.2 Register OE 4x Drive Structure (for Pin 10)

Figure 6. Register OE IO 4x Drive Structure Diagram

8.0 Connection Matrix

a 6-bit register to select one of these 64 input lines. For a complete list of the SLG46140’s register table, see Section 23.0 Appendix A - SLG46140 Register Definition. Figure 7. Connection Matrix Figure 8. Connection Matrix Example

8.1 Matrix Input Table

Table 32. Matrix Input Table

0 G R O U N D 000000

1 LUT2_0 output 0 0 0 0 0 1

2 LUT2_1 output 0 0 0 0 1 0

3 LUT2_2 output 0 0 0 0 1 1

4 LUT2_3 output 0 0 0 1 0 0

5 LUT2_4 / DFF0/Latch0 output 0 0 0 1 0 1

6 LUT2_5 / DFF1/Latch1 output 0 0 0 1 1 0

7 LUT3_0 output 0 0 0 1 1 1

8 LUT3_1 output 0 0 1 0 0 0

9 LUT3_2 output 0 0 1 0 0 1

10 LUT3_3 output 0 0 1 0 1 0

11 LUT3_4 / DFF2/Latch2 output 0 0 1 0 1 1

12 LUT3_5 / DFF3/Latch3 output 0 0 1 1 0 0

13 LUT4_0 output/PGEN output 0 0 1 1 0 1

14 DFF4/Latch4 Q output with resetb or setb 0 0 1 1 1 0

15 DFF4/Latch4 QB output with reset b o r s e t b 001111

16 DFF5/Latch5 Q output with resetb or setb 0 1 0 0 0 0

17 DFF5/Latch5 QB output with reset b o r s e t b 010001

19 OUT0 of pipe delay 0 1 0 0 1 1

20 OUT1 of pipe delay 0 1 0 1 0 0

22 PIN2 output 0 1 0 1 1 0

23 PIN3 output 0 1 0 1 1 1

24 PIN4 output 0 1 1 0 0 0

25 PIN5 output 0 1 1 0 0 1

26 PIN6 output 0 1 1 0 1 0

27 PIN7 output 0 1 1 0 1 1

28 PIN9 output 0 1 1 1 0 0

29 PIN10 output 0 1 1 1 0 1

30 PIN11 output 0 1 1 1 1 0

31 PIN12 output 0 1 1 1 1 1

32 PIN13 output 1 0 0 0 0 0

33 PIN14 output 1 0 0 0 0 1

35 RC oscillator output 1 0 0 0 1 1

37 CNT0/DLY0 output 1 0 0 1 0 1

38 CNT1/DLY1 output 1 0 0 1 1 0

39 CNT2/DLY2 / LUT4_1 output 1 0 0 1 1 1

40 CNT3/DLY3 / LUT3_7 output 1 0 1 0 0 0

41 PWM0_DCMP0_Out_positive 1 0 1 0 0 1

42 PWM0_DCMP0_Out_negative 1 0 1 0 1 0

43 PWM1_DCMP1_Out_positive 1 0 1 0 1 1

44 PWM1_DCMP1_Out_negative 1 0 1 1 0 0

45 PWM2_DCMP2_Out_positive 1 0 1 1 0 1

46 PWM2_DCMP2_Out_negative 1 0 1 1 1 0

47 SPI interrupt 1 0 1 1 1 1

48 ACMP0 output 1 1 0 0 0 0

49 ACMP1 output 1 1 0 0 0 1

50 ADC interrupt 1 1 0 0 1 0

62 POR output 1 1 1 1 1 0

8.2 Matrix Output Table

Table 33. Matrix Output Table

000-0046140-109 Page 56 of 169 SLG46140 9.0 8-bit SAR ADC Analog-to-Digital Converter (ADC) The Analog to Digital Converter in the SLG46140 is an 8-bit Successive Approximation Register Analog to Digital Converter (SAR ADC) which operates at a sampling speed of 100 kHz. The ADC’s DNL < ± 0.5 LSB and INL < ± 3.4 LSB and has a ADC V REF accuracy of ± 50 mV. The ADC consists of two parts: PGA which p rovides signal amplification and conditioning and SAR ADC which handles analog to digital conversion. PGA can be used as amplifier when ADC is disabled. Please see section 9.3.2 PGA Output for more details. User controlled inputs and outputs of the ADC are listed below: Inputs:

CH SELECTOR: Single-Ended Mode A DC Selection and Analog Input Mux Control Signal (PIN 11, VDD)
IN+: Single-Ended Mode Input (PI N6 or PIN7) and Differential Mode Positive Input (PIN6)
IN-: Differential Mode Nega tive Input (PIN 7 or DAC0)
VREF: ADC Voltage Reference Input (ADC V REF, VDD/4, none)
CLK or CLK/16: ADC Clock Input ( Ring OSC, Ext. CLK2 (matrix_out67), RC OSC, SPI SCLK)
Wake/Sleep Outputs:
PGA_Out: Output of the PGA to PIN4
PGA_Out: Output of the PGA to ACMP1
SER DATA: ADC seri al output (SPI)
PAR DATA: 8-bit ADC parallel da ta to either the SPI, PWM, or DCMP
INT_ OUT: ADC Interrupt Output (matrix_in50)

9.1 ADC Functional Diagram

Figure 9. ADC Functional Diagram

9.2 ADC Operation Modes

Single-Ended ADC operation using IN+ from PIN 6 or 7, when ADC_sel (reg <531>) is “0”
Differential ADC operation usi ng IN+ from PIN 6 and IN- from PIN 7, when ADC_sel (reg <531>) is “1”
Pseudo-Differential ADC operation using IN+ from PIN 6 and IN- from PIN 7, when ADC_sel (reg <531>) and ADC_pseudo-diff_en (reg <536>) bits are both set to “1”.

9.3 ADC 3-bit Programmable Gain Amplifier (PGA)

ADC_gain_control (reg<534:532>). See ADC Register Settings Table.

Single-ended: 0.25x, 0.5x, 1x, 2x, 4x, 8x;
Differential: 1x, 2x, 4x, 8x, 16x;
Pseudo-Differential: 1x, 2x, 4x. PGA inputs:
CH SELECTOR: Single-Ended Mode A DC Selection and Analog Input Mux Control Signal (PIN 11, VDD)
IN+: Single-Ended Mode Input (PI N6 or PIN7) and Differential Mode Positive Input (PIN6)
IN-: Differential Mode Nega tive Input (PIN7 or DAC0) PGA output is connected directly to ADC input. Also, it is possible to connect PIN7 to PGA output (reg<886>), when ADC is not

9.3.1 PGA 2-Channel Selection

the selection is controlled by PIN 11.

When PIN 11 is set to “0”, the ADC will sample PIN 7
When PIN 11 is set to “1”, the ADC will sample PIN 6 When ADC_channel_sel (reg <530>) is set to “0”, the PGA of the ADC will sample PIN 6 on the IN+ input.

Figure 10. ADC 2-Channel Selection

9.3.2 PGA Output

PGA can be used either in standalone mode or as ADC font-end / ACMP input buffer. affect output code calculation.

Single-ended mode: Vos(RTO) = GND
Differential mode: Vos(RTO) = 550 mV
Pseudo-Differential mo de: Vos(RTO) = 180 mV Note that the reference voltage macrocell is controlled by ADC, therefore if ADC is in POWE R DOWN mode, the reference macrocell is OFF and PGA output is referenced to GND. In this case both Differential and Pseudo-Differential modes provide the same output. Typical PGA specifications in Differential/Pseudo-Differential mode with ADC in POWER DOWN state are given in specifications section for information only. Note 1: PGA operation in Differential/Pseudo-Differential mode with ADC in POWER DOWN state is not recommended to use. Note 2: Toggling ADC POWER DOWN mode will also toggle the PGA output reference macrocell, that will influence the ACMP input voltage. PGA has a few output connection po ssibilities: to ACMP1 and/or ADC, and to external output on PIN4. Connection to external output is possible only when ADC is powered down. PGA output connection options:
Single-Ended mode:
A D C
A C M P
External output
Differential mode:
A D C
ACMP (See Note 2)
External output (Operation in this mode is not recommended)
Pseudo-Differential mode:
A D C
ACMP (See Note 2)
External output (Operation in this mode is not recommended)

9.3.3 PGA Power On Signal

On function must be enabled, reg <535> = 1.

9.3.4 PGA Register Settings

Table 34. PGA Register Settings

9.3.5 PGA Typical Performance

Figure 11. PGA Input Offset Distribution, Single-Ended Figure 12. PGA Input Offset Distribution, Single-Ended Figure 13. PGA Input Offset Distribution, Single-Ended Figure 14. PGA Input Offset Distribution, Single-Ended

9.4 ADC Input Voltage Definition

Vos - PGA offset voltage. RTI and RTO denotes referred to input and referred to output Vos. Figure 31. Typical PGA Gain Error vs. Vin, Figure 32. Typical PGA Gain Error vs. Vin,

000-0046140-109 Page 67 of 169 SLG46140 Vinn and Vinp - absolute voltage at negative and positive PGA input correspondingly Vcm - common mode PGA voltage: Note: In Pseudo-Differential mode Vcm is replaced by Vinn voltage for convenience ADC code for PGA differential input voltage Vind can be calculated as follows:

Single-ended mode: Vind = Vinp Vinp[min] and Vinp[max] - positive input voltage for bit0 and bit255 correspondingly (can be found in ADC specifications)
Differential and Pseudo-Differential mode: Vind[min] and Vind[max] - differential input voltage for bit0 and bit255 correspondingly (can be found in ADC specifications) Least significant bit size (LSB) calculates as follows: where FS is full-scale range: FS = Vind[max] - Vind[min] Vcm Vinn Vinp+ ADCcode 255 ADCcode 255 LSB FS

9.5 ADC Reference Voltage

ADC V REF from Internal Source (ADC VREF = 1.2 V)
Power Divider of (0.25) * V DD

9.6 ADC Power Down Select Mode

power cycle the ADC power on (ADC only) time is <5 s.

9.7 ADC Clock Source

16 clock cycles to sample the analog voltage and output the sampled data. Note: sampling rate should not exceed approximately 100 kbps.

00: Ring Oscillator
01: Matrix1_Out 73
10: RC Oscillator
11: SPI CLK Note: It is not recommended to design in high frequency signals (i nput our output) on pins adja cent to the following pins: Pin7, Pin8, PIn9 as this may affect ADC performance.

Figure 33. ADC Reference Voltage

9.8 ADC Outputs

16 clock cycles. See Figure 35.

9.8.1 ADC Serial Output

external device within the larger system design. cycles. The ADC_CLK is determined by either the RC Osc, Ring Osc, Matrix_Out67, or SPI CLK.

9.8.2 ADC Parallel Output

cycles. The ADC_CLK is determined by either the RC Osc, Ring Osc, Matrix_Out67, or SPI CLK. Figure 34. ADC Clock Source

9.9 ADC Interrupt Output Timing Diagram

Figure 35. ADC Interrupt Output Timing Diagram

9.10 ADC Register Settings

Note: For PGA Register settings refer to Table 34. Table 35. ADC Register Settings

000-0046140-109 Page 72 of 169 SLG46140 10.0 8-bit Digital-to-Analog Converter (DAC) There are two DACs in the SLG46140 (DAC0 and DAC1), they are 8-bit Digital to Analog Converters which operate at a maximum sampling speed of 100 ksps. The DAC's DNL is less than 1LSB and INL is less than 1LSB. DAC output to PIN resistance is 1 k. Load resistance is recommended to be no less than 10 k; load capacitance is recommended to be no more than 100 pF. User controlled inputs and outputs of the DAC are listed below: DAC0 Inputs:

R e g i s t e r s
8LSBs SPI
FSM0<7:0>
FSM1<7:0> DAC0 Outputs:
P I N 3
PGA negative input (00: 0 V; FF: 1 V)
ACMP0 negative input
ACMP1 negative input DAC1 Inputs:
R e g i s t e r s
8LSBs SPI
FSM0<7:0>
FSM1<7:0> DAC1 Outputs:
ACMP0 negative input
ACMP1 negative input If a DAC0 output is connected to external Pin3 of SLG46140's, it is necessary to enable this external pin as analog input/output. reg <544>: 0 - DAC0 power off, 1 - DAC0 power on. reg <538>: 0 - DAC1 power off, 1 - DAC1 power on. Please note that DAC1 is shared with ADC macrocell. Therefore it is impossible to use DAC1, when ADC is used. Also to activate DAC1, DAC0 must be enabled (reg <544> = 1 and reg <538> = 1). I n addition, DAC0 is used as a part of pseudo-differential mode of PGA macrocell. Therefore DAC0 is not available when PGA is in pseudo-differential mode.

10.1 DAC0 Functional Diagram

10.2 DAC1 Functional Diagram

Figure 36. DAC0 Functional Diagram Figure 37. DAC1 Functional Diagram

10.3 DAC Register Settings

Table 36. DAC Register Settings

11.0 Combinatorial Logic

Section 12.0 Combination Function Macrocells. devices (AND, NAND, OR, NOR, XOR, XNOR). Figure 38. 2-bit LUTs Table 37. 2-bit LUT0 Truth Table Table 38. 2-bit LUT1 Truth Table Table 39. 2-bit LUT2 Truth Table Table 40. 2-bit LUT3 Truth Table

Table 41. 2-bit LUT Standard Digital Functions Figure 39. 3-bit LUTs

Table 46. 3-bit LUT Standard Digital Functions Table 42. 3-bit LUT0 Truth Table Table 43. 3-bit LUT1 Truth Table Table 44. 3-bit LUT2 Truth Table Table 45. 3-bit LUT3 Truth Table

000-0046140-109 Page 78 of 169 SLG46140

12.0 Combination Function Macrocells

The SLG46140 has eight combination function macrocells that can serve more than one logic or timing function. In each case, they can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be implemented in these macrocells:

Two macrocells that can serve as either 2-bit LUTs or as D Flip Flops
Two macrocells that can serve as either 3-bit LUTs or as D Flip Flops
One macrocell that can serve as either 3-bit LUT or as Pipe Delay
One macrocell that can serve as either 3-bit LUT or as 8-Bit Counter / Delay
One macrocell that can serve as either 4-bit LUT or 16-bit Pattern Generator
One macrocell that can serve as either 4-bit LUT or as 14-Bit Counter / Delay Inputs/Outputs for the eight combination function macrocells are configured from the connection matrix with specific logic functions being defined by the state of NVM bits. When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR). When used as a D Flip Flop / Latch, the source and destination of the inputs and outputs for the DFF/Latches are configured from the connection matrix. All DFF/Latch macrocells have user selection for initial state, and all have the option to connect both the Q and Q Bar outputs to the connection matrix. The macrocells DFF2 and DFF3 have an additional input from the matrix that can serve as a nSet or nReset function to the macrocell. The operation of the D Flip-Flop and Latch will follow the functional descriptions below: DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change. Latch: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is High). 12.1 2-Bit LUT or D Flip Flop Macrocells There are two macrocells that can serve as either 2-bit LUTs or as D Flip Flops. When used to implement LUT functions, the 2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the connection matrix. When used to implement D Flip Flop function, the two input signals from the connection matrix go to the data (D) and clock (CLK) inputs for the Flip Flop, with the output going back to the connection matrix.

Table 49. LUT2_4 or DFF0 Register Settings Table 50. LUT2_5 or DFF1 Register Settings Table 47. 2-bit LUT4 Truth Table. Table 48. 2-bit LUT5 Truth Table.

Table 53. DFF2 Register Settings Table 54. DFF3 Register Settings Table 51. 3-bit LUT4 Truth Table Table 52. 3-bit LUT4 Truth Table

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay. output, which goes back into the connection matrix. <753:750> for OUT0 and reg <757:754> for OUT1. The 4-input mux is used to control the selection of the amount of delay. be the total time delay of the Pipe Delay logic cell. Figure 44. 3-bit LUT6 or Pipe Delay

16 Flip-FlopsIN

Table 56. Pipe Delay Register Settings Table 55. 3-bit LUT6 Truth Table

Figure 45. 3-bit LUT7 or CNT/DLY3/FSM1

Table 58. CNT/DLY2 Register Settings Table 57. 3-bit LUT6 Truth Table

a Look Up Table (LUT), or Programmable Pattern Generator (PGEN). pattern repeats.See Figure 47. Figure 46. 4-bit LUT0 or PGEN

Figure 47. PGEN Timing Diagram

4-Bit LUT0 is defined by reg<945:930>. Table 60. 4-bit LUT Standard Digital Functions Table 61. 4-Bit LUT0 or Programmable Pattern Generator Register Settings Table 59. 4-bit LUT0 Truth Table

Figure 48. 4-bit LUT1 or CNT/DLY2/FSM0

Table 63. 4-bit LUT Standard Digital Functions Table 62. 4-bit LUT1 Truth Table

Table 64. CNT/DLY2 Register Settings 11: 8MSBs SPI parallel data.

13.0 Analog Comparators (ACMP)

Matrix. When ACMP is powered down, output is low. enable the ACMPs with the POR signal, and not the VDD signal. selection VDD/4 and VDD/3 to maintain this input range. Input bias current < 1 nA (typ). Table 65. Gain Divider Input Resistance (typical) Figure 49. Maximum Power On Delay vs. VDD, Figure 50. Maximum Power On Delay vs. VDD,

be Vref + hysteresis/2 (high threshold) and Vref - hysteresis/2 (low threshold). Force Bandgap option is set as Disabled. Note: when VDD < 1.8V voltage reference should not exceed 1100 mV. Table 66. Gain Divider Accuracy Figure 51. Input Threshold Variation (including Vref variation, ACMP offset) vs. Voltage reference at T=(-40 … +85)°C, LBW Mode - Disable, Vhys=0 mV. Table 67. Built-in Hysteresis Tolerance.

13.1 ACMP0 Block Diagram

Figure 52. ACMP0 Block Diagram

13.2 ACMP0 Register Settings

Table 68. ACMP0 Register Settings

13.3 ACMP1 Block Diagram

Figure 53. ACMP1 Block Diagram

13.4 ACMP1 Register Settings

Table 69. ACMP1 Register Settings

000-0046140-109 Page 100 of 169 SLG46140

14.0 Digital Storage Elements (DFFs/Latches)

There are six Combination Function macrocells that can be used to implement D-Flip Flop or Latch functions. Please see Section 12.1 2-Bit LUT or D Flip Flop Macrocells and Section 12.2 3-Bit LUT or D Flip Flop with Set/Reset Macrocells for the description of this Combination Function macrocell.

14.1 Initial Polarity Operations

Figure 54. DFF Polarity Operations

Figure 55. DFF Polarity Operations with nReset

Figure 56. DFF Polarity Operations with nSet

15.0 Counters/Delay Generators (CNT/DLY)

implement longer count / delay circuits. 1) has one input from the connection matrix, which has a shared function of either a Delay Input or an external clock input. not see first period, if OSC rising edge appears immediately after input change. 12.6 4-Bit LUT or 14-Bit Counter / Delay Macrocells. Figure 57. CNT/DLY0

Figure 58. CNT/DLY1

15.1 CNT/DLY Timing Diagrams

Figure 59. Timing (rising edge) for count data = 3 Figure 60. Timing (falling edge) for count data = 3

15.1.3 CNT/FSM Mode CNT/DLY2, CNT/DLY4

Figure 64. CNT/FSM Timing Diagram (reset rising edge mode, oscillator is forced on, UP=0) for counter data = 3 Figure 65. CNT/FSM Timing Diagram (set rising edge mode, oscillator is forced on, UP=0) for counter data = 3

15.2 CNT/DLY0 Register Settings

Table 70. CNT/DLY0 Register Settings

15.3 CNT/DLY1 Register Settings

Table 71. CNT/DLY1 Register Settings

15.4 CNT/DLY2 Register Settings

Table 72. CNT/DLY2 Register Settings

15.5 CNT/DLY3 Register Settings

Table 73. CNT/DLY3 Register Settings

000-0046140-109 Page 114 of 169 SLG46140

16.0 Digital Comparator (DCMP) / Pulse Width Modulator (PWM)

The SLG46140 has three 8-bit digital comparator / pulse width modulator logic cells. Each of these three logic cells can be either a digital comparator (DCMP) or a pulse width modulator (PWM) independently of how the other two logic cells are defined. Both the DCMP and PWM logic can operate at up to a frequency of 10MHz. The input power for the three logic cells is controlled independently by reg<612> for DCMP0/PWM0, reg<601> for DCMP1/PWM1 and reg<590> for DCMP2/PWM2. PWM power down control is configured by reg <653> which is also shared with the ADC and OSC.

16.1 DCMP Input Modes

The three DCMP logic cells have a positive (IN+) and a negative (IN-) input that are compared within the logic cell. The inp signal (connected to the IN+ input) takes the value from a 4:1 mux selection between the following signals:

8-bit signal from the ADC Parallel Output
8-bit signal from the SPI logic cell output (SPI<15:8> for DCMP0 and DCMP2 or SPI<7:0> for DCMP1)
8-bit signal from the FSM0<7:0>
8-bit user defined signal value The inn signal (connected to the IN- input) takes the value from a 4:1 mux selection between the following signals:
8-bit signal from the SPI logic cell output (SPI<7:0> for DCMP0 and DCMP2 or SPI<15:8> for DCMP1)
8-bit signal from the FSM0<7:0>
8-bit signal from the FSM1<7:0 > (for DCMP0 and DCMP1) or CNT1'Q<7:0> (for DCMP2)
8-bit user defined signal value

16.2 DCMP Output Modes

The two 8-bit data inputs from IN+ and IN- are compared within the DCMP logic cells to produce the output and a match signal.

I f inp > inn, both OUT+ and OUT signals are equal to “1”, and EQ signal is equal to “0”
I f inp < inn, both OUT+ and OUT signals are equal to “0”, and EQ signal is equal to “0”
I f inp = inn, both OUT+ and OUT signals are equal to “0”, and EQ signal is equal to “1” Both the OUT+ and EQ signals are triggered by the rising or falling edge of the CKOSC signal (defined by bit reg <580:579>). There are two cases for the OUT signal controlled by reg <614>, reg <603>, reg <592>. If these registers = 0, then
i f inp > inn, OUT = 1, EQ = 0
i f inp < inn, OUT = 0, EQ = 0
i f inp = inn, OUT = 0, EQ = 1 If these registers = 1, then
i f inp > inn, OUT = 1, EQ = 0
i f inp < inn, OUT = 0, EQ = 0
i f inp = inn, OUT = 1, EQ = 1

16.3 PWM Input Modes

IN+ for the PWM is an 8-bit data string that can be selected from one of four sources:

8-bit signal from the ADC Parallel Output

000-0046140-109 Page 115 of 169 SLG46140

8-bit signal from the SPI logic cell output (SPI<15:8> for DCMP0 and DCMP1 or SPI<7:0> for DCMP2)
8-bit signal from the FSM0<7:0>
8-bit user defined signal value IN-’s 8-bit data string for all PWMs is sourced from an 8-bit signal from CNT/DLY .

16.4 PWM Output Modes

signal (EQ) will go high. The outputs (OUT- and OUT+) are non-overlapping.

PWM output duty cycle ranges from 0 % to 99.61% and is determined by: Output Duty Cycle = IN+/256
(IN+ = 0: output duty cycle = 0/256 = 0%; IN+ = 255: output duty cycle = 255/256 = 99.61%)
Output signals are triggered by the rising or falling edge of the CKOSC signal (defined by bit reg <580:579>) When reg<614/603/592> = “1”
PWM output duty cycle ranges from 0 .39% to 100% and is determined by Output Duty Cycle = (IN+ + 1)/256
(IN+ = 0: o utput duty cycle = 1/256 = 0.39%; IN+ = 255: output duty cycle = 256/256 = 100%)
Output signals are triggered by the rising or falling edge of the CKOSC signal (defined by bit reg <580:579>) When IN+ = IN- then EQ = “1”

16.5 DCMP0/PWM0 Functional Diagram

Figure 68. DCMP0/PWM0 Functional Diagram

8 MSBs SPI

8 LSBs SPI

16.6 DCMP1/PWM1 Functional Diagram

16.7 DCMP2/PWM2 Functional Diagram

Figure 69. DCMP1/PWM1 Functional Diagram Figure 70. DCMP2/PWM2 Functional Diagram

16.8 PWM Dead Band Control

reg<594:593>. The typical dead band time starts at 8 ns and can go to 64 ns, increasing by 8 ns intervals.

16.9 PWM Dead Band Control Timing Diagram

16.10 DCMP/PWM Power Down Control

When reg<612> = “0” DCMP0/PWM0 is powered down, when “1” logic cell is ON
When reg<601> = “0” DCMP1/PWM1 is powered down, when “1” logic cell is ON
When reg<590> = “0” DCMP2/PWM2 is powered down, when “1” logic cell is ON

16.11 DCMP/PWM Clock Invert Control

and reg<591> are used to control the three logic cells clock inversion for PWM0, PWM1, and PWM2 respectively. Figure 71. PWM Dead Band Control Timing Diagram

16.12 DCMP/PWM Register Settings

Table 74. DCMP/PWM Register Settings

17.0 Slave SPI - Serial to Parallel / Parallel to Serial Converter (SPI)

signal and the nCSB (Enable Control Signal) comes from the Connection Matrix Out. PWM/DCMP2_IN- and FSM1 logic cells. serial data will be output to PIN12.

17.1 SPI Functional Diagram

Figure 72. SPI Functional Diagram

17.2 Clock polarity and phase

configured by the CPOL and CPHA bits respectively. serial to parallel and from parallel to serial. Figure 73. Timing Diagram showing Clock Polarity and Phase, CPHA = 0 Table 75. CPHA = 0 Timing Characteristics

Figure 74. Timing Diagram showing Clock Polarity and Phase, CPHA = 1 Table 76. CPHA = 1 Timing Characteristics Note: *The data is based on 50 pF loading on the output PIN, and the output drive strength is 2x option.

At CPOL=0 the base valu e of the clock is zero
For CPHA=0, data are captured on the clock's rising edge (LOW→HIGH transition) and data is propagated on a falling edge. (HIGH→LOW clock transition).
For CPHA=1, data are captured on the clock's falling edge and data is propagated on a rising edge.
At CPOL=1 the base value of t he clock is one (inversion of CPOL=0)
For CPHA=0, data are captured on clock's falling edge and data is propagated on a rising edge.
For CPHA=1, data are captured on clock's rising edge and data is propagated on a falling edge. That is, CPHA=0 means sample on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or fallin g. Note that with CPHA=0, the data must be stable for a half cy cle before the first clock cycle. The MOSI and MISO signals are us ually stable (at their receptio n points) for the half cycle unt il the next clock transition. S PI master and slave devices may well sample data at different points in that half cycle. This adds more flexibility to the communication channel between the master and slave.

17.3 SPI Clock synchronization

asynchronization of SCLK and the internal clocks, see Figure 75. Figure 75. Timing Diagram showing SPI Clock synchronization

17.4 SPI data buffer function

DFF’s output (SPI[7:0]) is the ADC data’s buffered output which can be sent to DCMP/PWMs or FSM (CNT)s.

17.5 SPI Register Settings

Figure 76. The SPI used as ADC/FSM data buffer diagram Table 77. SPI Register Settings

18.0 Pipe Delay (PD)

The SLG46140 has one 16-stages DFF Pipe Delay Macrocell. by register bits. The 4-input mux is used to control the selection of the amount of delay. the total time delay of the Pipe Delay logic cell. Figure 77. Pipe Delay

19.0 Programmable Delay / Edge Detector

period. See the timing diagrams below for further information. Note: The input signal must be longer than the delay, otherwise it will be filtered out.

19.1 Programmable Delay Timing Diagram - Edge Detector Output

Figure 78. Programmable Delay Figure 79. Edge Detector Output

19.2 Programmable Delay Timing Diagram - Glitch Filtering For Edge Detector Output

Figure 80. Delayed Edge Detector Output Figure 81. Glitch Filtering for Edge Detector Output

19.3 Programmable Delay 0 Register Settings

Table 78. Programmable Delay 0Register Settings

20.0 Voltage Reference (VREF)

20.1 Voltage Reference Overview

Table 79. VREF Selection Table

11111 DAC0 _out DAC0_out

11110 DAC1_out DAC1_out

20.2 VREF Block Diagram

Table 80. VREF Range Figure 82. Voltage Reference Block Diagram

000-0046140-109 Page 132 of 169 SLG46140

21.0 Oscillators

The SLG46140 has two internal RC oscillators (25 kHz or 2 MHz, user selectable), as well as one Low-Frequency oscillator (1.9 kHz) and one Ring oscillator (25 MHz). There are two divider stages for the RC and Ring oscillators, a nd one divider stage for the Low-Frequency oscillator, that allow the user flexibility for introducing clock signals to connectio n matrix, as well as various other Macrocells. The predivider ( first stage) for RC Oscillator allows the selection of /1, /2, /4 or /8, for LF Osc - /1, /2, /4 or /1 6 and for Ring Osc - /1, /4, / 8 or /16 to divide down frequency from the fundamental. The second stage di vider of RC oscillators has an input of frequency from the predivider, and outputs one of eight different frequencies on Connection Matrix Input line <35>. The output of LF Osc Predivider goes directly on Connection Matrix Input line <50>. Please see Figure 83 below, for more details on the SLG46140 clock scheme. The Matrix Power Down function allows to switch on/off the oscillators using an external pin (reg<567> for 25 kHz / 2 MHz OSC, reg<562> for LF OSC and reg<575> for Ring Osc):

Enable <1>. If PWR DOWN input of oscillator is LOW, the oscillator will be turned on. If PWR DOWN input of oscillator is HIGH the oscillator will be turned off.
Disable <0>. Turns off the Matrix Power Down function. The PWR CONTROL signal has the highest priority. The user can select two OSC POWER MODEs (reg<564> for 25 kHz / 2 MHz RC OSC, reg<563> for LF OSC and reg<574> for Ring Osc):
If FORCE POWER ON <1> is selected, the OSC will run when the SLG46140 is powered on.
If AUTO POWER ON <0> is selected, the OSC will run only when any macrocell that uses OSC is powered on. OSC can be turned on by:
Register control (force power on);
Delay mode, when delay requires OSC;
ADC;
PWM/DCMP .

Figure 83. Oscillator Block Diagram

25 MHz

21.1 Oscillator Power On delay

Figure 84. Oscillator Startup Diagram Figure 85. Low Frequency Oscillator Maximum Power On Delay vs. VDD at room temperature Note 1: OSC power mode: "Auto Power On”. Note 2: ‘OSC enable’ signal appears when any block that uses OSC is powered on.

21.2 Oscillator Accuracy

Figure 88. Ring Oscillator Maximum Power On Delay vs. VDD at room temperature. Figure 89. RC Oscillator Frequency vs. Temperature, RC OSC=2 MHz

Note: For more information see section 5.7 OSC Specifications. Figure 92. Ring Oscillator Frequency vs. Temperature, Ring OSC=25 MHz

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22.0 Power On Reset (POR)

The SLG46140 has a power-on reset (POR) macrocell to ensure cor rect device initialization and operation of all macrocells in the device. The purpose of the POR circuit is to have consisten t behavior and predictable results when the VDD power is first ramping to the device, and also while the VDD is falling during power-down. To accomplish this goal, the POR drives a defined sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of the I/O pins.

22.1 General Operation

The SLG46140 is guaranteed to be powered down and nonoperationa l when the VDD voltage (voltage on PIN1) is less than Power Off Threshold (see in Electrical Characteristics table), but not less than -0.6V. Another essential condition for the chip to be powered down is that no voltage higher (see Note 1) than the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3V, applying a voltage higher than 0.3V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior. Note 1. There is a 0.6V margin due to forward drop voltage of the ESD protection diodes. To start the POR sequence in the SLG46140, the voltage applied on the VDD should be higher than the Power_ON threshold voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power_ON threshold. After the POR sequence has started, the SLG46140 will have a typical period of time to go through all the steps in the sequence (see Figure 80 and Figure 81), and will be ready and completely operational after the POR sequence is complete. Note 2. The Power_ON threshold is defined in Electrical Characteristics table. Note 3. VDD ramp rising speed must be less than 0.6 V/µs after power on. Violating this specification may cause chip to restart. To power down the chip the VDD voltage should be lower than the operational and to guarantee that chip is powered down it should be less than Power Off Threshold. All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step in the POR sequence releases the I/O structures from the high impedance state, at which time the device is operational. The pin configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.

22.2 POR Sequence

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 93. environmental factors, such as: slew rate, VDD value, temperature and even will vary from chip to chip (process influence). Figure 93. POR sequence

22.3 Macrocells Output States During POR Sequence

states during the POR sequence (Figure 94 describes the output signals states). last are output PINs that become active and determined by the input signals.

22.4 Initialization

Input PINs, ACMP , pull up/down;
DFFs, Delays/Counters, Pipe Delay;
Output PIN corresponds to the internal logic

Figure 94. Internal Macrocell States during POR sequence

the mentioned powerup sequence is complete. the input PIN.There is no effect from input pin when input voltage is applied at the same time as VDD.

22.5 Power Down

that during a slow rampdown, outputs can possibly switch state during this time.

22.6 POR Register Settings

22.7 External reset

The SLG46140 has an optional External Reset function on Pin2. It allows to reset the chip while powered on. NVM remains its previous state, see Figure 96 to Figure 98. Figure 95. Power Down Table 81. POR Register Settings

1.2 V VREF Out Signal

Figure 96. External reset sequence (High active).

Figure 97. External reset sequence (Rising edge detect).

Figure 98. External reset sequence (Falling edge detect). Table 82. External reset Register Settings

000-0046140-109 Page 146 of 169 SLG46140

23.0 Appendix A - SLG46140 Register Definition

Address Signal Function Register Bit Definition reg<5:0> in0 of LUT2_0 (out0) reg<11:6> in1 of LUT2_0 (out1) reg<17:12> in0 of LUT2_1 (out2) reg<23:18> in1 of LUT2_1 (out3) reg<29:24> in0 of LUT2_2 (out4) reg<35:30> in1 of LUT2_2 (out5) reg<41:36> in0 of LUT2_3 (out6) reg<47:42> in1 of LUT2_3 (out7) reg<53:48> in0 of LUT2_4 / data of DFF/Latch 0 (out8) reg<59:54> in1 of LUT2_4 / cl ock of DFF/Latch 0 (out9) reg<65:60> in0 of LUT2_5 / data of DFF/Latch 1 (out10) reg<71:66> in1 of LUT2_5 / cl ock of DFF/Latch 1 (out11) reg<77:72> in0 of LUT3_0 (out12) reg<83:78> in1 of LUT3_0 (out13) reg<89:84> in2 of LUT3_0 (out14) reg<95:90> in0 of LUT3_1 (out15) reg<101:96> in1 of LUT3_1 (out16) reg<107:102> in2 of LUT3_1 (out17) reg<113:108> in0 of LUT3_2 (out18) reg<119:114> in1 of LUT3_2 (out19) reg<125:120> in2 of LUT3_2 (out20) reg<131:126> in0 of LUT3_3 (out21) reg<137:132> in1 of LUT3_3 (out22) reg<143:138> in2 of LUT3_3 (out23) reg<149:144> in0 of LUT3_4 / re setb of DFF/Latch 2 (out24) reg<155:150> in1 of LUT3_4 / data of DFF/Latch 2 (out25) reg<161:156> in2 of LUT3_4 / cl ock of DFF/Latch 2 (out26) reg<167:162> in0 of LUT3_5 / re setb of DFF/Latch 3 (out27) reg<173:168> in1 of LUT3_5 / data of DFF/Latch 3 (out28) reg<179:174> in2 of LUT3_5 / cl ock of DFF/Latch 3 (out29) reg<185:180> in0 of LUT4_0 (out30) reg<191:186> in1 of LUT4_0 (out31) reg<197:192> in2 of LUT 4_0 or PGEN (out32) reg<203:198> in3 of LUT 4_0 or PGEN (out33) reg<209:204> nRST of DFF/Latch 4 (out34) reg<215:210> data of DF F/Latch 4 (out35) reg<221:216> clock of DFF/Latch 4 (out36) reg<227:222> nRST of DFF/Latch 5 (out37) reg<233:228> data of DF F/Latch 5 (out38) reg<239:234> clock of DFF/Latch 5 (out39) reg<245:240> clock of pipe delay / in0 of LUT3_6 (out40)

000-0046140-109 Page 147 of 169 SLG46140 reg<251:246> in of pipe delay / in1 of LUT3_6 (out41) reg<257:252> porb of pipe dela y / in2 of LUT3_6 (out42) reg<263:258> input of edge detecto r and programmable delay (out43) reg<269:264> digital ou tput of PIN3 (out44) reg<275:270> oe of PIN3 (out45) reg<281:276> digital ou tput of PIN4 (out46) reg<287:282> oe of PIN4 (out47) reg<293:288> digital ou tput of PIN5 (out48) reg<299:294> oe of PIN5 (out49) reg<305:300> digital ou tput of PIN6 (out50) reg<311:306> digital ou tput of PIN7 (out51) reg<317:312> oe of PIN7 (out52) reg<323:318> digital ou tput of PIN9 (out53) reg<329:324> oe of PIN9 (out54) reg<335:330> digital out put of PIN10 (out55) reg<341:336> digital ou tput of PIN11 (out56) reg<347:342> digital out put of PIN12 (out57) reg<353:348> oe of PIN12 (out58) reg<359:354> digital out put of PIN13 (out59) reg<365:360> oe of PIN13 (out60) reg<371:366> digital out put of PIN14 (out61) reg<377:372> oe of PIN14 (out62) reg<383:378> ADC power down (1: power down) (out63) reg<389:384> pdb(power down) for acmp0 (0: power down) (out64) reg<395:390> pdb(power down) for acmp1 (0: power down) (out65) reg<401:396> oscillator power down (1: power down) (out66) reg<407:402> counter external c lock in3 of LUT4_1 (out67) reg<413:408> input of dly/cnt0 (out68) reg<419:414> input of dly/cnt1 (out69) reg<425:420> input of dly/c nt2 in0 of LUT4_1(out70) reg<431:426> keep of dly/cnt2 (fsm0) in1 of LUT4_1 (out71) reg<437:432> up of dly/cnt2 ( fsm0) in2 of LUT4_1 (out72) reg<443:438> input of dly/c nt3 in0 of LUT3_7 (out73) reg<449:444> keep of dly/cnt3 (fsm1) in1 of LUT3_7 (out74) reg<455:450> up of dly/cnt3 ( fsm1) in2 of LUT3_7 (out75) reg<461:456> PWM/DCMP0 positive input and PWM/DCMP1 nega- tive input register selection bit 0 (out76) reg<467:462> PWM/DCMP0 positive input and PWM/DCMP1 nega- tive input register selection bit 1 (out77) reg<473:468> PWM power down (1: power down) (out78) reg<479:474> csb of SPI (out79) reg<485:480> sclk of SPI (out80) Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 148 of 169 SLG46140 Programmable Delay reg<487:486> Mode selection 00: rising edge detect 01: falling edge detect 10: both edge detect 11: both edge delay reg<489:488> Delay time selection 00: 110 ns delay 01: 220 ns delay 10: 330 ns delay 11: 440 ns delay reg<490> Output delay control 0: output no delay 1: output delay Bandgap/Reference reg<495:491> Reserved reg<500:496> ACMP0 vref value selection 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: vref_ext_acmp1 11011: vref_ext_acmp0 11100: vref_ext_acmp1 / 2 11101: vref_ext_acmp0 / 2 11100: DAC1_out 11111: DAC0_out reg<505:501> ACMP1 vref value selection 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: vref_ext_acmp1 11011: vref_ext_acmp0 11100: vref_ext_acmp1 / 2 11101: vref_ext_acmp0 / 2 11100: DAC1_out 11111: DAC0_out reg<506> Reserved reg<507> Bandgap OK for ADC, ACMP output delay time select, the start time is porb_core go to high 0: 550 us 1:100 us Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 149 of 169 SLG46140 reg<509:508> ACMP1 hysteresis control 00: 0 01: 25 mV 10: 50 mV 11: 200 mV reg<511:510> ACMP0 hysteresis control 00: 0 01: 25 mV 10: 50 mV 11: 200 mV reg<512> Bandgap turn on by register 0: off 1: turn on (if chip is power down, the bandgap will power down even if it is set to 1) reg<513> Reserved reg<514> Reserved reg<515> Reserved ADC and ACMP reg<517:516> ACMP 1 input selection 00: Pin9 input 01: ADC PGA out 10: Pin10 input 11: none reg<518> ACMP 1 low bandwidth enable 0: disable 1: enable reg<520:519> ACMP 1 gain control 00: 1x 01: 0.5x 10: 0.33x 11: 0.25x reg<521> ACMP wake sleep enable 0: disable 1: enable reg<523:522> ACMP 0 gain control 00: 1x 01: 0.5x 10: 0.33x 11: 0.25x reg<524> ACMP 0 low bandwidth enable 0: disable 1: enable reg<526:525> ACMP 0 input selection 00: Pin10 input 01: PGA out 10: VDD 11: none reg<528:527> Output buffer source selection 00: buffer power down 01: ACMP0's in 10: ACMP1's in 11: DAC0's output reg<529> ADC negative input from internal DAC0 0: disable 1: enable reg<530> Multichannel input Mux enable (controlled by pin11) 0: disable (pin11 can not control) 1: enable reg<531> ADC input mode control 0:single ended 1: differential input Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 150 of 169 SLG46140 reg<534:532> ADC PGA gain selection 000: 0.25x (For single-ended operation only) 001: 0.5x (For single-ended operation only) 010: 1x 011: 2x 100: 4x 101: 8x (For single-ended and differential operation) 110: 16x (For differential operation only) 111: Reserved reg<535> PGA power on signal 0: power down 1: power on Note: in ADC wake sleep/dynamic on/off mode, it should set to 0 reg<536> ADC Pseudo-Differential mode enable 0: disable 1: enable reg<537> Reserved reg<538> DAC1 power on signal 0: power down 1: power on When DAC0 used only, need set this bit reg<539> Reserved reg<540> ACMP 0 input 100u current source enable 0: disable 1: enable reg<541> ACMP 1 input 100u current source enable 0: disable 1: enable reg<543:542> ADC speed selection 00: Reserved 01: Reserved 10: 100 kHz 11: Reserved reg<544> DAC0 power on signal 0: power down 1: power on When DAC0 used only, need set this bit reg<546:545> ADC vref source select 00: ADC V REF 01: Reserved 10: 1/4 Vdd 11: None reg<547> DAC0 input selection 0: from register 1: from DCMP1's input reg<555:548> DAC0 8 bit register control 00: DAC0 output is 0 FF: DAC0's output is 1 v reg<556> DAC1 input selection 0: from DCMP1's input 1: all input are 0 reg<557> ADC wake sleep enable 0: disable 1: enable reg<558> force ADC analog part on 0: disable 1: enable reg<559> PGA output enable 0: disable 1: enable LF OSC Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 151 of 169 SLG46140 reg<561:560> Clock divide ratio control for LF osc 00: /1 01: /2 10: /4 11: /16 reg<562> Matrix power down (matrix_out66)enable for LF oscilla- tor 0: disable 1: enable reg<563> Low Frequency osc turn on by register 0: off 1: turn on (if chip is power down, the LFosc will power down even if it is set to 1) RC OSC reg<564> RC osc turn on by register 0: off 1: turn on (if chip is power down, the RCosc will pow- er down even if it is set to 1) reg<565> RC osc frequency select 0:25 KHz 1:2 MHz reg<566> Current source in RC osc always turn on enable, it short- en the RC oscillator start up time but with 200nA DC current on. 0: disable 1: enable reg<567> Matrix power down (matrix_out66)enable for RC oscil- lator 0: disable 1: enable reg<569:568> Clock divide ratio control for RC osc 00: /1 01:/2 10:/4 11: /8 reg<570> RC osc clock to matrix input enable 0: disable 1: enable reg<573:571> Clock divide ratio c ontrol for RC osc to matrix 000: /1 001:/2 010:/4 011: /3 100: /8 101: /12 110: /24 111: /64 Ring OSC reg<574> Ring osc turn on by register 0: off 1: turn on (if chip is power down, the Ring Osc will power down even if it is set to 1) reg<575> Matrix power down (matrix_out66)enable for ring oscil- lator 0: disable 1: enable reg<577:576> Clock divide ratio control for ring osc 00: /1 01:/4 10:/8 11: /16 reg<578> ADC clock divide by 16 BYPASS 0: no bypass 1: bypass reg<580:579> PWM and ADC clock source select 00: CK_RINGOSC 01:CK_MATRIX(matrix_out67) 10:CK_RCOSC 11:CK_SPI_SCLK(matrix_out80) reg<581> Ring osc clock to matrix input enable 0: disable 1: enable Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 152 of 169 SLG46140 reg<584:582> clock divide ratio c ontrol for ring osc to matrix 000: /1 001:/2 010:/4 011: /3 100: /8 101: /12 110: /24 111: /64 reg<585> ADC data synchronized with SPI clock enable 0: disable 1: enable reg<586> PWM data synchronized with SPI clock enable 0: disable 1: enable reg<587> FSM data synchronized with SPI clock enable 0: disable 1: enable PWM/DCMP 2 reg<588> PWM/DCMP2 clock source selection 0:clock from mux controlled by reg[580:579] 1: matrix_out67 reg<589> PWM/DCMP2 function selection 0: PWM 1: DCMP. when in PWM mode, OUTN2 is pwm2's negative output. when in DCMP mode, OUTN2 is dcmp2's match output reg<590> PWM/DCMP2 tu rn on by register 0: disable 1: enable reg<591> PWM/DCMP2 clock inversion 0: disable 1: enable reg<592> PWM/DCMP2 mode selection 0: PWM output duty cycle down to 0% and DCMP out=1 if A>B, 1: PWM output duty cycle up to 100% and DCMP out=1 if A>=B reg<594:593> PWM2 dead band zone control 00: 10 ns 01: 20 ns 10:40 ns 11:80 ns reg<596:595> PWM/DCMP2 positiv e input source selection 00: ADC 01: 8MSBs SPI 10: FSM0[7:0] 11: reg3 reg<598:597> PWM/DCMP2 negative input 00: FSM0[7:0] 01:reg2 10: 8LSBs SPI 11:CNT1_Q[7:0] PWM/DCMP 1 reg<599> PWM/DCMP1 clock source selection 0:clock from mux controlled by reg<580:579> 1: matrix_out67 reg<600> PWM/DCMP1 function selection 0: PWM 1: DCMP. when in PWM mode, OUTN1 is pwm1's negative output. when in DCMP mode, OUTN1 is dcmp1's match output reg<601> PWM/DCMP1 tu rn on by register 0: disable 1: enable reg<602> PWM/DCMP1 clock inversion 0: disable 1: enable Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 153 of 169 SLG46140 reg<603> PWM/DCMP1 mode selection 0: PWM output duty cycle down to 0% and DCMP out=1 if A>B 1: PWM output duty cycle up to 100% and DCMP out=1 if A>=B reg<605:604> PWM1 dead band zone control 00: 10 ns 01: 20 ns 10: 40 ns 11: 80 ns reg<607:606> PWM/DCMP1 positiv e input source selection 00: ADC 01: 8LSBs SPI 10: FSM1[7:0] 11: reg1 reg<609:608> PWM/DCMP1 negative input 00: FSM1[7:0] 01:regs from MUX controlled by matrix_out[77:76] 10: 8MSBs SPI 11:FSM0[7:0] PWM/DCMP 0 reg<611> PWM/DCMP0 function selection 0: PWM 1: DCMP. when in PWM mode, OUTN0 is pwm0's negative output. when in DCMP mode, OUTN0 is dcmp0's match output reg<612> PWM/DCMP0 tu rn on by register 0: disable 1: enable reg<613> PWM/DCMP0 clock inversion 0: disable 1: enable reg<614> PWM/DCMP0 mode selection 0: PWM output duty cycle down to 0% and DCMP out=1 if A>B, 1: PWM output duty cycle up to 100% and DCMP out=1 if A>=B. reg<616:615> PWM0 dead band zone control 00: 10 ns 01: 20 ns 10: 40 ns 1 1: 80 ns reg<618:617> PWM/DCMP0 positiv e input source selection 00: ADC 01: 8MSBs SPI 10: FSM0[7:0] 11: regs from MUX controlled by matrix_out[77:76] reg<620:619> PWM/DCMP0 negative input 00: FSM0[7:0] 01:reg0 10: 8LSBs SPI 11:FSM1[7:0] PWM/DCMP or DAC Data reg<628:621> reg0, 8 bit s NVM data to PWM/DCMP or DAC input data reg<636:629> reg1, 8 bit s NVM data to PWM/DCMP or DAC input data reg<644:637> reg2, 8 bit s NVM data to PWM/DCMP or DAC input data reg<652:645> reg3, 8 bit s NVM data to PWM/DCMP or DAC input data reg<653> power down sync to clock and output state control in power down mode 0: power down is not synchronized with clock, and output reset to 0 when PWM/DCMP is power down, 1: power down is synchronized with clock, when PD=0, the clock is enabled after 2 clock cycles, while when PD=1, the clock is gated immediately. and the output is kept at current state when PD=1. SPI Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 154 of 169 SLG46140 reg<654> SPI used as ADC/FSM buf fer enable (1 clock delayed) 1: enable reg<655> SPI parallel inpu t data source selection 0: FSM0[7:0],FSM1[7:0] 1: ADC reg<656> SPI clock phase ( CHPA) refer to SPI spec reg<657> SPI clock polarity (CHOL) refer to SPI spec reg<658> byte selection 0: 16 bits 1: 8 bits (less significant 8 bits) reg<659> SPI input/out put mode selection 0: Serial In Parallel out 1: Parallel In Serial out reg<660> CNT test enable 0: disable 1: enable LUT3_7 or CNT3/DLY/FSM reg<668:661> LUT3_7 data (if reg<677:676>=11) or CNT3/DLY/FSM 8-bits data data reg<669> CNT3 Value Control 0: Reset (CNT value = 0) 1: Set (CNT value = FSM data) reg<673:670> DLY3/CNT3/FS M1 clock source select 0000: CK_RCOSC 0001: CK_RCOSC_DIV4 0010: CK_RCOSC_DIV12 0011: CK_RCOSC_DIV24 0100: CK_RCOSC_DIV64 0101: CNT_END2 0110: matrix_out67 0111: matrix_out67 divide by 8 1000: CK_RINGOSC 1001: matrix_out80(SPI_SCLK) 1010: CK_LFOSC 1011: CKFSM_DIV256 1100: CKPWM. 1101: Reserved 1110: Reserved 1111: Reserved reg<675:674> DLY3 edge mode select If DLY Mode or Edge Detect: 00: Both Edge 01: Falling Edge 10: Rising Edge 11: None If CNT/FSM: 00: Both Edge Reset 01: Falling Edge Reset 10: Rising Edge Reset 11: High level Reset reg<677:676> DLY/CNT3 macrocell function select 00: DLY0 01: CNT/FSM 10: edge detect 11: 3bit LUT3_7 reg<679:678> FSM1 input data source select 00: 8 bits NVM data 01: 8 bits ADC data 10: 0 11: 8LSBs SPI parallel data DLY2/CNT2/FSM0 or LUT4_1 reg<693:680> LUT4_1 data [bits 13:0] (if reg<702:701>=11) or DLY2/CNT2/FSM0 data data Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 155 of 169 SLG46140 reg<694> LUT4_1 data [bit 14] (if reg<702:701>=11) or CNT2 Val- ue Control 0: Reset (CNT value = 0) 1: Set (CNT value = FSM data) reg<698:695> reg<698>LUT4_1 data [bit 15] (if reg<702:701>=11) or DLY2/CNT2/FSM0 clock source select 0000: CK_RCOSC 0001: CK_RCOSC_DIV4 0010: CK_RCOSC_DIV12 0011: CK_RCOSC_DIV24 0100: CK_RCOSC_DIV64 0101: DLY_OUT1 0110: matrix_out67 0111: matrix_out67 divide by 8 1000: CK_RINGOSC 1001: matrix_out80(SPI_SCLK) 1010: CK_LFOSC 1011: CKFSM_DIV256 1100: CKPWM 1101: Reserved 1110: Reserved 1111: Reserved reg<700:699> DLY2 edge mode select If DLY Mode or Edge Detect: 00: Both Edge 01: Falling Edge 10: Rising Edge 11: None If CNT/FSM: 00: Both Edge Reset 01: Falling Edge Reset 10: Rising Edge Reset 11: High level Reset reg<702:701> DLY/CNT2 macrocell function select 00: DLY 01: CNT/FSM 10: edge detect 11:4bit LUT4_1 reg<704:703> FSM0 input data source select 00: 8 bits NVM data 01: 8bits ADC data 10: 0 11: 8MSBs SPI parallel data DLY1/CNT1 reg<712:705> CNT1 8-bits data from register data reg<713> CNT1's Q are set to 1s or reset 0s selection 0: reset to 0s 1: set to Data reg<717:714> DLY1/CNT1 clock source select 0000: CK_RCOSC 0001: CK_RCOSC_DIV4 0010: CK_RCOSC_DIV12 0011: CK_RCOSC_DIV24 0100: CK_RCOSC_DIV64 0101: DLY_OUT0 0110: matrix_out67 0111: matrix_out67 divide by 8 1000: CK_RINGOSC 1001: matrix_out80(SPI_SCLK) 1010: CK_LFOSC 1011: CKFSM_DIV256 1100: CKPWM Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 156 of 169 SLG46140 reg<719:718> DLY1 edge mode select If DLY Mode or Edge Detect: 00: Both Edge 01: Falling Edge 10: Rising Edge 11: None If CNT/FSM: 00: Both Edge Reset 01: Falling Edge Reset 10: Rising Edge Reset 11: High level Reset reg<721:720> DLY/CNT1 macrocell function select 00: DLY 01: CNT/FSM 10: edge detect 11: 3bit LUT DLY0/CNT0 reg<735:722> CNT0 14bits data from register data reg<736> CNT0's Q are set to 1s or reset 0s selection 0: reset to 0s 1: set to Data reg<740:737> DLY0/CNT0 clock source select 0000: CK_RCOSC 0001: CK_RCOSC_DIV4 0010: CK_RCOSC_DIV12 0011: CK_RCOSC_DIV24 0100: CK_RCOSC_DIV64 0101: DLY_OUT3 0110: matrix_out67 0111: matrix_out67 divide by 8 1000: CK_RINGOSC 1001: matrix_out80(SPI_SCLK) 1010: CK_LFOSC 1011: CKFSM_DIV256 1100: CKPWM reg<742:741> DLY0 edge mode select If DLY Mode or Edge Detect: 00: Both Edge 01: Falling Edge 10: Rising Edge 11: None If CNT/FSM: 00: Both Edge Reset 01: Falling Edge Reset 10: Rising Edge Reset 11: High level Reset reg<744:743> DLY/CNT0 macrocell function select 00: DLY 01: CNT/FSM 10: edge detect 11: 3bit LUT reg<745> Wake sleep output state when ws oscillator is powered down 0: in power down mode 1: in normal operation state reg<746> RC osc and LF osc bypass enable 0:disable 1: enable Сlock is from matrix_out67 reg<749:747> Reserved (need to set to 0) data = 000 LUT3_6 or Pipe Delay reg<757:750> LUT3_6 Data (if reg.<759>=0) or Pipe Delay Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 157 of 169 SLG46140 reg<753:750> Pipe Delay out0 selection bits register bits from 0 to 15, data delay from 1 to 16 pipes reg<757:754> Pipe Delay out1 selection bits register bits from 0 to 15, data delay from 1 to 16 pipes reg<758> out1 output polarity control. 0: non-inverted 1: inverted reg<759> function selection 0: PIPE Delay 1: 3-bit LUT All PINs reg<760> IO precharge enable bit 0: disable 1: enable PIN 2 reg<762:761> PIN2 mode control 00: digital in without schmitt trigger 01: digital in with schmitt trigger 10: Low Voltage Digital in reg<764:763> PIN2 pull up/do wn resistor selection 00: floating 01: 10 K 10: 100 K 11: 1 M reg<765> PIN2 pull up resistor enable 0: pull down 1: pull up PIN 3 reg<767:766> PIN3 in put mode control 00: digital in without schmitt trigger 01: digital in with schmitt trigger 10: Low Voltage Digital in 11: analog IO reg<769:768> PIN3 output mode control 00: 1x push-pull 01: 2x push-pull 10: 1x open-drain 11: 2x open-drain reg<771:770> PIN3 pull up/do wn resistor selection 00: floating 01: 10 K 10: 100 K 11: 1 M reg<772> PIN3 pull up resistor enable 0: pull down 1: pull up PIN 4 reg<774:773> PIN4 in put mode control 00: digital in without schmitt trigger 01: digital in with schmitt trigger 10: Low Voltage Digital in 11: analog IO reg<776:775> PIN4 output mode control. 00: 1x push-pull 01: 2x push-pull 10: 1x open-drain 11: 2x open-drain reg<778:777> PIN4 pull up/do wn resistor selection 00: floating 01: 10 K 10: 100 K 11: 1 M reg<779> PIN4 pull up resistor enable 0: pull down 1: pull up PIN 5 Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 158 of 169 SLG46140 reg<781:780> PIN5 in put mode control 00: digital in without schmitt trigger 01: digital in with schmitt trigger 10: Low Voltage Digital in 11: analog IO reg<783:782> PIN5 output mode control. 00: 1x push-pull 01: 2x push-pull 10: 1x open-drain 11: 2x open-drain reg<785:784> PIN5 pull up/do wn resistor selection 00: floating 01: 10 K 10: 100 K 11: 1 M reg<786> PIN5 pull up resistor enable 0: pull down 1: pull up PIN 6 reg<787> Reserved reg<790:788> PIN6 in put mode control 000: digital in without schmitt trigger 001: digital in with schmitt trigger 010: Low Voltage Digital in 011: analog IO 100: push-pull mode 101: NMOS open-drain 110: PMOS open-drain 111: analog IO and NMOS open-drain mode reg<792:791> PIN6 pull up/do wn resistor selection 00: floating 01: 10 K 10: 100 K 11: 1 M reg<793> PIN6 pull up resistor enable 0: pull down 1: pull up reg<794> PIN6 output driver current x2 enable 0: disable 1: enable PIN 7 reg<796:795> PIN7 in put mode control 00: digital in without schmitt trigger 01: digital in with schmitt trigger 10: Low Voltage Digital in 11: analog IO reg<798:797> PIN7 output mode control 00: 1x push-pull 01: 2x push-pull 10: 1x open-drain 11: 2x open-drain reg<800:799> PIN7 pull up/do wn resistor selection 00: floating 01: 10 K 10: 100 K 11: 1 M reg<801> PIN7 pull up resistor enable 0: pull down 1: pull up PIN 9 reg<803:802> PIN9 in put mode control 00: digital in without schmitt trigger 01: digital in with schmitt trigger 10: Low Voltage Digital in 11: analog IO Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 159 of 169 SLG46140 reg<805:804> PIN9 output mode control. 00: 1x push-pull 01: 2x push-pull 10: 1x open-drain 11: 2x open-drain reg<807:806> PIN9 pull up/do wn resistor selection 00: floating 01: 10 K 10: 100 K 11: 1 M reg<808> PIN9 pull up resistor enable 0: pull down 1: pull up reg<809> PIN9 4x Drive enable 0: disable 1: enable PIN 10 reg<810> Reserved reg<813:811> PIN10 input mode control 000: digital in without schmitt trigger 001: digital in with schmitt trigger 010: Low Voltage Digital in 011: analog IO 100: push-pull mode 101: NMOS open-drain 110: PMOS open-drain 111: analog IO and NMOS open-drain mode reg<815:814> PIN10 pull up/d own resistor selection 00: floating 01: 10 K 10: 100 K 11: 1 M reg<816> PIN10 pull up resistor enable 0: pull down 1: pull up reg<817> PIN10 output driver current x2 enable 0: disable 1: enable reg<818> PIN10 4x Drive enable 0: disable 1: enable PIN 11 reg<819> Reserved reg<822:820> PIN11 input mode control 000: digital in without schmitt trigger 001: digital in with schmitt trigger 010: Low Voltage Digital in 011: analog IO 100: push-pull mode 101: NMOS open-drain 110: PMOS open-drain 111: analog IO and NMOS open-drain mode reg<824:823> PIN11 pull up/d own resistor selection 00: floating 01: 10 K 10: 100 K 11: 1 M reg<825> PIN11 pull up resistor enable 0: pull down 1: pull up reg<826> PIN11 output driver current x2 enable 0: disable 1: enable PIN 12 Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 160 of 169 SLG46140 reg<828:827> PIN12 input mode control 00: digital in without schmitt trigger 01: digital in with schmitt trigger 10: Low Voltage Digital in 11: analog IO reg<830:829> PIN12 ou tput mode control. 00: 1x push-pull 01: 2x push-pull 10: 1x open-drain 11: 2x open-drain reg<832:831> PIN12 pull up/d own resistor selection 00: floating 01: 10 K 10: 100 K 11: 1 M reg<833> PIN12 pull up resistor enable 0: pull down 1: pull up PIN 13 reg<835:834> PIN13 input mode control 00: digital in without schmitt trigger 01: digital in with schmitt trigger 10: Low Voltage Digital in 11: analog IO reg<837:836> PIN13 ou tput mode control. 00: 1x push-pull 01: 2x push-pull 10: 1x open-drain 11: 2x open-drain reg<839:838> PIN13 pull up/d own resistor selection 00: floating 01: 10 K 10: 100 K 11: 1 M reg<840> PIN13 pull up resistor enable 0: pull down 1: pull up PIN 14 reg<842:841> PIN14 input mode control 00: digital in without schmitt trigger 01: digital in with schmitt trigger 10: Low Voltage Digital in 11: analog IO reg<844:843> PIN14 ou tput mode control. 00: 1x push-pull 01: 2x push-pull 10: 1x open-drain 11: 2x open-drain reg<846:845> PIN14 pull up/d own resistor selection 00: floating 01: 10 K 10: 100 K 11: 1 M reg<847> PIN14 pull up resistor enable 0: pull down 1: pull up LUT2_0 reg<851:848> LUT2_0 data Data LUT2_1 reg<855:852> LUT2_1 data Data LUT2_2 reg<859:856> LUT2_2 data Data LUT2_3 Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 161 of 169 SLG46140 reg<863:860> LUT2_3 data Data LUT2_4 or DFF/Latch0 reg<867:864> LUT2_4 Data (if r eg<868>=0) or DFF/Latch0 reg<864> DFF/Latch Mode Select 0: DFF function 1: Latch function reg<865> DFF/Latch out put polarity control 0: Q output 1: QB output reg<866> DFF/Latch initial state during POR 0: initial state is 0 1: initial state is 1 reg<867> Unused if DFF/Latch Funct ion Selected Unused if DFF/Latc h Function Selected reg<868> Function Selection 0: LUT2 function 1: DFF/Latch function. LUT2_5 or DFF/Latch1 reg<872:869> LUT2_5 Data (if r eg.<873>=0) or DFF/Latch1 reg<869> DFF/Latch Mode Select 0: DFF function 1: Latch function reg<870> DFF/Latch out put polarity control 0: Q output 1: QB output reg<871> DFF/Latch initial state during POR 0: initial state is 0 1: initial state is 1 reg<872> Unused if DFF/Latch Funct ion Selected Unused if DFF/Latc h Function Selected reg<873> Function Selection. 0: LUT2 function 1: DFF/Latch function. LUT3_0 reg<881:874> LUT3 data Data LUT3_1 reg<889:882> LUT3 data Data LUT3_2 reg<897:890> LUT3 data Data LUT3_3 reg<905:898> LUT3 data Data LUT3_4 or DFF/Latch2 reg<913:906> LUT3_4 Data (if r eg.<914>=0) or DFF/Latch2 reg<906> DFF/Latch Mode Select 0: DFF function 1: Latch function reg<907> DFF/Latch out put polarity control 0: Q output 1: QB output reg<908> DFF/Latch set or reset selection 0: reset controlled by matrix 1: set controlled by matrix reg<909> DFF/Latch initial state during POR 0: initial state is 0 1: initial state is 1 reg<913:910> Unused if DFF/Latch F unction Selected Unused if DFF/ Latch Function Selected reg<914> Function Selection. 0: LUT3 function 1: DFF/Latch function. LUT3_5 or DFF/Latch3 reg<923:915> LUT3_5 Data (if r eg.<923>=0) or DFF/Latch3 Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 162 of 169 SLG46140 reg<915> DFF/Latch Mode Select 0: DFF function 1: Latch function reg<916> DFF/Latch out put polarity control 0: Q output 1: QB output reg<917> DFF/Latch set or reset selection 0: reset controlled by matrix 1: set controlled by matrix reg<918> DFF/Latch initial state during POR 0: initial state is 0 1: initial state is 1 reg<922:919> Unused if DFF/Latch F unction Selected Unused if DFF/ Latch Function Selected reg<923> Function Selection 0: LUT3 function 1: DFF/Latch function DFF/Latch4 reg<924> DFF/Latch mode select 0: DFF function 1: Latch function reg<925> DFF/Latch set or reset selection 0: reset controlled by matrix 1: set controlled by matrix reg<926> DFF/Latch initial state during POR 0: initial state is 0 1: initial state is 1 DFF/Latch5 reg<927> DFF/Latch mode select 0: DFF function 1: Latch function reg<928> DFF/Latch set or reset selection 0: reset controlled by matrix 1: set controlled by matrix reg<929> DFF/Latch initial state during POR 0: initial state is 0 1: initial state is 1 LUT4_0 or PGEN reg<945:930> LUT4_0 dat a or PGEN data Data reg<949:946> 4-Bit Counter for PGEN Data reg <950> Function Selection 0: LUT4 function 1: PGEN function. Miscellaneous reg<957:951> Reserved reg<963:958> Reserved reg<971:964> Reserved reg<977:972> Reserved reg<983:978> Reserved reg<991:984> Reserved reg<992> Reserved Reserved reg<993> Reserved reg<995:994> NVM load repeat time control 00: 1 time load & check 01: 2 times load & check 10: 3 times load & check 11: 4 times load & check. reg<997:996> SPI SDIO output control 0x: pin12 dout from matrix 0 (out57) 10: from SPI (SDO) 11: from ADC serial output Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 163 of 169 SLG46140 reg<999:998> reset output control from pin13 0x: digital output from pin13 10: reset output from pin13 11: digital output from pin13 PIN2 Reset Control reg<1000> 0: pin2 edge active 1: pin2 high active reg<1001> 0: rising edge 1: falling edge reg<1002> 0: disable 1: enable POR and Regulator reg<1003> Bypass V DD to 1.8 V device. Only when power is 1.8 V 0: 1.8v use regulator 1: bypass vdd as 1.8v device power reg<1004> Input pad enable to core resetb delay 500us enable 0: delay 4us 1: delay 500us reg<1005> Disable power auto det ector function for charge pump 0: enable 1: disable reg<1006> Reserved reg<1014:1007> Pattern ID Pattern ID reg<1015> Reserved reg<1023:1016> Reserved Register Bit Address Signal Function Register Bit Definition

000-0046140-109 Page 164 of 169 SLG46140

24.0 Package Top Marking System Definition

PPA Part Code + Assembly Code Pin 1 Identifier WWR Date Code + Revision Code NN Serial Number Code

000-0046140-109 Page 165 of 169 SLG46140

25.0 Package Drawing and Dimensions

14 Lead STQFN FC Green Package 1.6 x 2.0 x 0.55 mm

000-0046140-109 Page 166 of 169 SLG46140

26.0 Tape and Reel Specifications

26.1 Carrier Tape Drawing and Dimensions

# of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm]per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 14L 1.6x2 mm 0.4P FC Green 14 1.6x2.0x0.55 3000 3000 178/60 100 400 100 400 8 4 Package Type Pocket BTM Length [mm] Pocket BTM Width [mm] Pocket Depth [mm] Index Hole Pitch [mm] Pocket Pitch [mm] Index Hole Diameter [mm] Index Hole to Tape Edge [mm] Index Hole to Pocket Center [mm] Tape Width [mm] A0 B0 K0 P0 P1 D0 E F W STQFN 14L 1.6x2 mm 0.4P FC Green

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27.0 Recommended Land Pattern

28.0 Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow prof ile based on package volume of 1.76 mm 3 (nominal). More information can be found at www.jedec.org. Units: m

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29.0 Revision History

11/22/2017 1.09 Fixed typos 11/7/2017 1.08 Updated OSC Electrical Spec Fixed typos 10/11/2017 1.07 Updated Electrical Spec Fixed typos 10/2/2017 1.06 Fixed typos Updated ADC Typical Current Consumption 7/3/2017 1.05 Fixed typos 5/31/2017 1.04 Fixed typos Updated PGA Specification Conditions Updated POR section Updated Absolute Maximum Conditions and Electrical Characteristics 2/17/2017 1.03 Fixed typos 1/18/2017 1.02 Updated Silego Website & Support Updated Section Programmable Delay / Edge Detector Fixed typos 10/25/2016 1.01 Fixed typos 10/20/2016 1.00 Production Release

000-0046140-109 Page 169 of 169 SLG46140 Silego Website & Support Silego Technology Website Silego Technology provides online support via our website at http://www.silego.com/.This website is used as a means to make files and information easily available to customers. For more information regarding Silego Green products, please visit our website. Our Green product lines feature: GreenPAK: Programmable Mixed Signal Matrix products GreenFET1 / GreenFET3 / HFET1: MOSFET Drivers and ultra-small, low RDSon Load Switches GreenCLK1 / GreenCLK2 / GreenCLK3: Crystal replacement technology Products are also available for purchase directly from Silego at the Silego Online Store at http://www.silego.com /buy/. Silego Technical Support Datasheets and errata, application notes and example designs, u ser guides, and hardware support documents and the latest software releases are available at the Silego website or can be requested directly at info@silego.com. For specific GreenPAK design or applications questions and support please send e-mail requests to GreenPAK@silego.com Users of Silego products can receive assistance through several channels: Contact Your Local Sales Representative Customers can contact their local sales representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. More information regarding your lo cal representative is available at the Silego website or send a request to info@silego.com Contact Silego Directly Silego can be contacted directly via e-mail at info@silego.com or user submission form, located at the following URL: http://support.silego.com/ Other Information The latest Silego Technology press releases, listing of seminars and events, listings of world wide Silego Technology offices and representatives are all available at http://www.silego.com/ THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. SILEGO TECHNOLOGY DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICA- TIONS OR USES OF ITS PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE.

Selected Specification

Dialog Semiconductor SLG46140 overview.

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Summary

GreenPAK Programmable Mixed-signal Matrix

Description

GreenPAK Programmable Mixed-signal Matrix

Source title SLG46140 Datasheet(PDF) - Dialog Semiconductor

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