SLG46127

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Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 88

Technical content

Features

• Logic & Mixed Signal Circuits
• Highly Versatile Macro Cells
• Read Back Protection (Read Lock)
• 1.8V (±5%) to 5V (±10%) Supply
• Operating Temperature Range -40 °C to 85 °C
• Dual 44 mΩ, 2 A P-Channel MOSFETs
• Package
• 1.6 x 2.0 x 0.55 mm MSTQFN 16L package
• Pb-Free / Halogen-Free / RoHS compliant

Applications

• Power Sequencing with Complex Analog Control
• Power Plane Component Size Reduction Project
• LED Driver
• Haptic Motor Driver
• System RESET wit h Power Switch Pin Configuration VIN1 GPIO GPIO VIN0 GND GPIO GPIO 16pin MSTQFN (Top View) VOUT1 NC 14 13 AGND GPI GPIO VOUT0 VDD 15 16 PWR_SW_ON1 PWR_SW_ON015 3-bit LUT3_4 or Pipe Delay Programmable Delay RC Oscillator ACMP0 ACMP1 Look Up Tables (LUTs) Counters/Delay Generators CNT0 CNT3CNT1 2-bit LUT2_2 3-bit LUT3_3 2-bit LUT2_3 3-bit LUT3_2 Combination Function Macrocells 2-bit LUT2_0 or DFF0 2-bit LUT2_1 or DFF1 3-bit LUT3_1 or DFF3 3bit LUT3_0 or DFF2 4-bit LUT4_0 or CNT2 FILTER_0 Additional Logic Functions Pin 1 GPIO Pin 2 GPIO Pin 3 GND Pin 4 VIN0 Pin 9 VIN1 Pin 8 VOUT1 Pin 11 GPIO Pin 10 GPIO P-FET Power Switch1 Vref P-FET Power Switch0 Pin 5 VOUT0 Pin 6 NC Pin 7 AGND Pin 12 VDD Pin 14 GPIO Pin 13 GPI Pin 16 PWR_SW _ON1 Pin 15 PWR_SW _ON0

000-0046127-101 Page 1 of 87 SLG46127

1.0 Overview

The SLG46127 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macro cells of the SLG46127. This highly versatile device allows a wi de variety of mixed-signal functions to be designed within a ve ry small, low power single integrated circuit. The SLG46127 includes the following:

• Two Analog Comparators (ACMP)
• Four Combinatorial Look Up Tables (LUTs)
• Two 2-bit LUTs
• Two 3-bit LUTs
• Six Combination Function Macro cell
• Two Selectable DFF/Latch or 2-bit LUTs
• Two Selectable DFF/Latch or 3-bit LUTs
• One Selectable Pipe Delay or 3-bit LUT
• Pipe Delay – 8 stage / 2 output
• One Selectable Counter/Delay or 4-bit LUT
• Three Counter / Delay Generators (CNT/DLY)
• Three 8-bit counter/delays with external clock/reset
• Programmable Delay
• One Logic Function – 1 Deglitch Filter
• RC Oscillator (RC OSC)
• Power On Reset (POR)
• P-FET Power Switch
• Power Switch IDS: 2 A
• VIN: 1.71 V to 5.5 V
• Low RDSON
• 4 4 m @ 5.5 V
• 5 8 m @ 3.3 V
• 1 1 0 m @ 1.71 V

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2.0 Pin Description

2.1 Functional Pin Description

Pin # Pin Name Function Programming Function

1 GPIO General Purpose I/O or Analog Comparator 0 (-) N/A

2 GPIO General Purpose I/O or Ana log Comparator 1 (+) with OE N/A

3 GND Ground Ground

4 VIN0 P-FET Power Switch Input N/A

5 VOUT0 P-FET Power Switch Output N/A

6 NC No Connect N/A

7 AGND P-FET Power Switch Ground Power Switch Ground

8 VOUT1 P-FET Power Switch Output N/A

9 VIN1 P-FET Power Switch Input N/A

10 GPIO General Purpose I/O with OE and Vref output Programming SRDWB Pin

11 GPIO General Purpose I/O or External Clock Input Programming SCL Pin

12 VDD Power Supply Power Supply

13 GPI General Purpose Input VPP (Programming Voltage)

14 GPIO General Purpose I/O or Analog Comparator 0 (+) Programming ID Pin

15 PWR_SW_ON0 P-FET Power Switch On Programming Mode Control

16 PWR_SW_ON1 P-FET Power Switch On Programming SDIO Pin

3.0 User Programmability

as long as it remains powered and can be re-written as needed to facilitate rapid design changes. Once the design is finalized, the design file can be forwarded to Silego to integrate into the production process. Figure 1. Steps to create a custom Silego GreenPAK device

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4.0 Ordering Information

SLG46127MTR MSTQFN 16L - Tape and Reel (3k units)

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5.0 Electrical Specifications

5.1 Absolute Maximum Conditions

5.2 Electrical Characteristics (1.8V ±5% VDD) Parameter Condition/Description Min. Max. Unit Supply voltage on VDD relative to GND -0.5 7 V DC Input voltage GND - 0.5 V DD + 0.5 V Current at Input Pin -1.0 1.0 mA Storage Temperature Range -65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1000 -- V Moisture Sensitivity Level 1 VIN P-FET 0.3 V DD V ΘJA Thermal Resistance* -- 99 °C/W PD Maximum Power Dissipation, TJ,MAX Maximum Junction Temperature 150 °C P-FET Power Switch IDSCONT Total, TJ < 150°C -- 2 A P-FET Power Switch IDSPK For no more than 1 ms with 1% duty cycle -- 2.5 A Note*: Mounted on 27.4mm x 30.1 mm PCB (1.6 mm thick, 1 oz copper, FR-4 material). Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 1.71 1.80 1.89 V IQ Quiescent Current Static Inputs and Outputs -- 0.5 -- A TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VAIR Analog Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.1 V VIH HIGH-Level Input Voltage Logic Input 1.100 -- V DD V Logic Input with Schmitt Trigger 1.270 -- V DD V Low-Level Logic Input 0.980 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 0.690 V Logic Input with Schmitt Trigger -- -- 0.440 V Low-Level Logic Input -- -- 0.520 V IIH HIGH-Level Input Current Logic Input Pins; V IN = 1.8 V -1.0 -- 1.0 A IIL LOW-Level Input Current Logic Input Pins; V IN = 0 V -1.0 -- 1.0 A VOH HIGH-Level Output Voltage Push-Pull 1X, Open Drain PMOS 1X, IOH = 100 A 1.680 1.790 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 100 A 1.702 1.800 -- V

000-0046127-101 Page 6 of 87 SLG46127 VOL LOW-Level Output Voltage Push-Pull 1X, IOL= 100 A -- 0.020 0.030 V Push-Pull 2X, IOL= 100 A -- 0.010 0.020 V Open Drain NMOS 1X, IOL= 100 A -- 0.010 0.020 V Open Drain NMOS 2X, IOL= 100 A -- 0.010 0.010 V IOH HIGH-Level Output Current Push-Pull 1X, Open Drain PMOS 1X, VOH = VDD - 0.2 1.040 1.400 -- mA Push-Pull 2X, Open Drain PMOS 2X, VOH = VDD - 0.2 2.150 2.710 -- mA IOL LOW-Level Output Current Push-Pull 1X, VOL = 0.15 V 0.760 1.340 -- mA Push-Pull 2X, VOL = 0.15 V 1.520 2.660 -- mA Open Drain NMOS 1X, VOL = 0.15 V 1.530 2.670 -- mA Open Drain NMOS 2X, VOL = 0.15 V 3.060 5.130 -- mA TSU Startup Time from VDD ris ing past 1.35 V -- 0.27 -- ms PONTHR Power On Threshold V DD Level Required to Start Up the Chip 1.182 1.346 1.505 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 0.752 0.918 1.110 V Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046127-101 Page 7 of 87 SLG46127 5.3 Electrical Characteristics (3.3V ±10% VDD) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3.0 3.3 3.6 V IQ Quiescent Current Static Inputs and Outputs -- 0.75 -- A TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VAIR Analog Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 1.780 -- V DD V Logic Input with Schmitt Trigger 2.130 -- V DD V Low-Level Logic Input 1.130 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 1.210 V Logic Input with Schmitt Trigger -- -- 0.950 V Low-Level Logic Input -- -- 0.690 V IIH HIGH-Level Input Current Logic Input Pins; V IN = 3.3 V -1.0 -- 1.0 A IIL LOW-Level Input Current Logic Input Pins; V IN = 0 V -1.0 -- 1.0 A VOH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, IOH = 3 mA 2.710 3.090 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 3 mA 2.870 3.190 -- V VOL LOW-Level Output Voltage Push-Pull 1X, IOL= 3 mA -- 0.180 0.280 V Push-Pull 2X, IOL= 3 mA -- 0.090 0.130 V Open Drain NMOS 1X, IOL= 3 mA -- 0.090 0.130 V Open Drain NMOS 2X, IOL= 3 mA -- 0.050 0.070 V IOH HIGH-Level Output Current Push-Pull 1X, Open Drain PMOS 1X, VOH = 2.4 V 5.830 10.180 -- mA Push-Pull 2X, Open Drain PMOS 2X, VOH = 2.4 V 11.264 19.660 -- mA IOL LOW-Level Output Current Push-Pull 1X, VOL = 0.4 V 4.060 6.440 -- mA Push-Pull 2X, VOL = 0.4 V 8.130 12.360 -- mA Open Drain NMOS 1X, VOL = 0.4 V 8.130 12.410 -- mA Open Drain NMOS 2X, VOL = 0.4 V 16.260 22.900 -- mA TSU Startup Time from VDD ris ing past 1.35 V -- 0.27 - ms PONTHR Power On Threshold V DD Level Required to Start Up the Chip 1.182 1.346 1.505 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 0.752 0.918 1.110 V

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5.4 Electrical Characteristics (5V ±10% VDD)

Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V IQ Quiescent Current Static Inputs and Outputs -- 1.0 -- A TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VAIR Analog Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 2.640 -- V DD V Logic Input with Schmitt Trigger 3.160 -- V DD V Low-Level Logic Input 1.230 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 1.840 V Logic Input with Schmitt Trigger -- -- 1.510 V Low-Level Logic Input -- -- 0.780 V IIH HIGH-Level Input Current Logic Input Pins; V IN = 5 V -1.0 -- 1.0 A IIL LOW-Level Input Current Logic Input Pins; V IN = 0 V -1.0 -- 1.0 A VOH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, IOH = 5 mA 4.150 4.730 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 5 mA 4.300 4.860 -- V VOL LOW-Level Output Voltage Push-Pull 1X, IOL= 5 mA -- 0.230 0.330 V Push-Pull 2X, IOL= 5 mA -- 0.120 0.160 V Open Drain NMOS 1X, IOL= 5 mA -- 0.120 0.160 V Open Drain NMOS 2X, IOL= 5 mA -- 0.070 0.090 V IOH HIGH-Level Output Current Push-Pull 1X, Open Drain PMOS 1X, VOH = 2.4 V 21.808 29.100 -- mA Push-Pull 2X, Open Drain PMOS 2X, VOH = 2.4 V 40.598 56.080 -- mA IOL LOW-Level Output Current Push-Pull 1X, VOL = 0.4 V 6.010 9.730 -- mA Push-Pull 2X, VOL = 0.4 V 11.590 19.460 -- mA Open Drain NMOS 1X, VOL = 0.4 V 11.760 19.460 -- mA Open Drain NMOS 2X, VOL = 0.4 V 19.120 35.621 -- mA TSU Startup Time from VDD ris ing past 1.35 V -- 0.27 - ms PONTHR Power On Threshold V DD Level Required to Start Up the Chip 1.182 1.346 1.505 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 0.752 0.918 1.110 V

5.5 IDD Estimator

5.6 Timing Estimator

Table 1. Typical Current estimated for each block. Table 2. Typical Delay estimated for each block.

5.7 Typical Counter/Delay Offset Measurements

5.8 Expected Delays and Widths

Table 3. Typical Counter/Delay Offset Measurements. Table 4. Expected Delays and Widths for Programmable Delay (typical).

5.9 Typical Deglitch Filter Pulse Width Performance

5.10 Power Switch Electrical Characteristics (each P-FET)

Table 5. Typical Deglitch Filter Pulse Width Performance at T = 25°C. Table 6. Power Switch Electrical Characteristics, TA = -40°C to +85°C (with typical values at TA = +25°C), VDD = 5.5 V, Note 1: Pulse test: ƒ = 100 Hz, Duty cycle < 2%. Note 2: Measured to be less than 0.4 μA during production test. Note 3: RG influence has been excluded.

Figure 2. TTotal_On, TOn_Delay and Slew Rate Measurement

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6.0 Summary of Macro Cell Function

6.1 I/O Pins

• Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
• Open Drain Outputs
• Push Pull Outputs
• Analog I/O
• 10 k /100 k/1 Mpull-up/pull-down resistors

6.2 Connection Matrix

• Digital matrix for circuit co nnections based on user design

6.3 Analog Comparators (2 total)

• Selectable hysteresis 0 mV/25 mV/50 mV/200 mV

6.4 Voltage Reference

• Used for references on Analog Comparators
• Can also be driven t o external Pin 10

6.5 Combinational Logic Look Up Tables (LUTs – 4 total)

• Two 2-bit Lookup Tables
• Two 3-bit Lookup Tables

6.6 Combination Function Macrocells (7 total)

• Two Selectable DFF/Latch or 2-bit LUTs
• Two Selectable DFF/Latch or 3-bit LUTs
• One Selectable Pipe Delay or 3-bit LUT
• One Selectable CNT/DLY or 4-bit LUT
• One Programmable Delay/ Deglitch Filter

6.7 Delays/Counters (3 total)

• Three 8-bit delays/counters with external clock/reset: Range 1-255 clock cycles

6.8 Pipe Delay (Part of Combination Function Macrocell)

• 8 stage / 2 output
• Two 1-8 stage sel ectable outputs.

6.9 Programmable Delay (Part of Combination Function Macrocell)

• 125 ns/250 ns/375 ns/500 ns @ 3.3 V
• Includes Edge Detection function

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6.10 RC Oscillator

• 25 kHz and 2 MHz s electable frequency
• First stage divider (4): OSC /1, OSC/2, OSC/4, and OSC/8
• Second stage divider (8): selec table (OSC/1, OSC/2, OSC/3, OSC/4, OSC/8, OSC/12, OSC/24, or OSC/64)

6.11 Power On Reset (POR)

6.12 Dual P-FET Power Switch

• Power Switch IDS: 2.0 A
• VIN: 1.71 V to 5.5 V
• Low RDSON
• 4 4 m @ 5.5 V
• 5 8 m @ 3.3 V
• 1 1 0 m @ 1.71 V

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7.0 I/O Pins

The SLG46127 has a total of 6 multi-function I/O pins which can function as either a user defined Input or Output, as well as serving as a special function (such as outputting the voltage reference). Refer to Section 2.0 Pin Description for pin definitions. Normal Mode pin definitions are as follows and Programming Mode pin definitions are as follows according to section 2.1 Functional Pin Description. Each of the six user defined I/O pins on the SLG46127 can serve as both digital input and digital output. But Pin 13 can only serve as a digital input pin.

7.1 Input Modes

Each I/O pin can be configured as a digital input pin with/with out buffered Schmitt trigger, or can also be configured as a lo w voltage digital input. Pins 1, 2 and 14 can also be configured to serve as analog inputs to the on-chip comparators and Vref output. PIN10 can be used as Vref output.

7.2 Output Modes

Pins 1, 2, 10, 11 and 14 can all be configured as digital output pins.

7.3 Pull Up/Down Resistors

All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors are 10 k, 100 k and 1 M. In the case of Pin 13, the resistors are fixed to a pull-down configuration. In the case of all other I/O pins, the internal resistors can be configured as either pull-up or pull-downs.

7.4 I/O Register Settings

7.5 PIN 1 Register Settings

7.5.1 PIN 2 Register Settings

Table 7. PIN 1 Register Settings Table 8. PIN 2 Register Settings

7.5.2 PIN 10 Register Settings

7.5.3 PIN 11 Register Settings

Table 9. PIN 10 Register Settings Table 10. PIN 11 Register Settings

7.5.4 PIN 13 Register Settings

7.5.5 PIN 14 Register Settings

Table 11. PIN 13 Register Settings Table 12. PIN 14 Register Settings

7.6 GPI IO Structure

7.6.1 GPI IO Structure (for Pin 13)

Figure 3. PIN 13 GPI IO Structure Diagram

7.7 Matrix OE IO Structure

7.7.1 Matrix OE IO Structure (for Pin 2, 10)

Figure 4. Matrix OE IO Structure Diagram

7.8 Register OE IO Structure

7.8.1 Register OE IO Structure (for Pins 1, 11, 14)

Figure 5. Register OE IO Structure Diagram

8.0 Connection Matrix

macrocell uses a 5-bit register to select one of these 32 input lines. For a complete list of the SLG46127’s register table, see Section 19.0 Appendix A - SLG46127 Register Definition. Figure 6. Connection Matrix Figure 7. Connection Matrix Example

8.1 Matrix Input Table

Table 13. Matrix Input Table

0 G N D 00000

5 LUT2_0 output (DFF/LATCH_0 output) 0 0 1 0 1

6 LUT2_1 output (DFF/LATCH_1 output) 0 0 1 1 0

7 LUT2_2 output 0 0 1 1 1

8 LUT2_3 output 0 1 0 0 0

9 LUT3_0 output (DFF/LATCH_2 out put with nRST or nSET) 0 1 0 0 1

10 LUT3_1 output (DFF/LATCH_3 output with nRST or nSET) 0 1 0 1 0

11 LUT3_2 output 0 1 0 1 1

12 LUT3_3 output 0 1 1 0 0

13 LUT3_4 output (pipe delay ouput0) 0 1 1 0 1

15 LUT4_0 output (CNT_DLY2 output (8 bit w/ ext CK, reset)) 0 1 1 1 1

16 CNT_DLY0 output (8 bit w/ ext CK (shared bottom delay/CNT),

17 CNT_DLY1 output (8 bit w/ ext CK (from dedicated matrix output),

18 CNT_DLY3 (8 bit) output 1 0 0 1 0

21 Edge detect output 1 0 1 0 1

22 Programmable delay with edge detector output (Deglitch filter out-

23 Internal oscillator output1 (one of /1,/2,/3,/4,/8,12/,24/,64/ selected

24 Internal oscillator output2 (one of /1,/2,/3,/4,/8,12/,24/,64/ selected

25 Bandgap OK signal 1 1 0 0 1

26 POR output to matrix 1 1 0 1 0

27 Power Switch ON0, pin15 digital Input 1 1 0 1 1

28 Power Switch ON1, pin16 digital Input 1 1 1 0 0

8.2 Matrix Output Table

Table 14. Matrix Output Table

9.0 Combinatorial Logic

Section 10.0 Combination Function Macro Cells. devices (AND, NAND, OR, NOR, XOR, XNOR). created within each of the two 2-bit LUT logic cells. Figure 8. 2-bit LUTs Table 17. 2-bit LUT2/LUT3 Standard Digital Functions. Table 15. 2-bit LUT2 Truth Table. Table 16. 2-bit LUT3 Truth Table.

Figure 9. 3-bit LUTs Table 18. 3-bit LUT2 Truth Table. Table 19. 3-bit LUT3 Truth Table.

created within each of the two 3-bit LUT logic cells. Table 20. 3-bit LUT2/LUT3 Standard Digital Functions

10.0 Combination Function Macro Cells

• Two macrocells that can serve as either 2-bit LUTs or as D Flip-Flops.
• Two macrocells that can serve as either 3-bit LUTs or as D Flip-Flops.
• One macrocell that can serve as either 3-bit LUT or as Pipe Delay
• One macrocells that can serve as either 4-bit LUTs or as 8-Bit Counter / Delays Inputs/Outputs for the six combination function macrocells are configured from the connection matrix with specific logic functions being defined by the state of NVM bits. When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR). When used as a D Flip-Flop / Latch, the source and destination of the inputs and outputs for the DFF/Latches are configured from the connection matrix. All DFF/Latch macrocells have user selection for initial state, and all have the option to connect both the Q and Q Bar outputs to the connection matrix. The macrocells DF F2, DFF3 have an additional input from the matrix that can serve as a nSET or nRST function to the macrocell. The operation of the D Flip-Flop and Latch will follow the functional descriptions below: DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change Latch: if CLK = 0, then Q = D 10.1 2-Bit LUT or D Flip-Flop Macrocells There are two macrocells that can serve as either 2-bit LUTs or as D Flip-Flops. When used to implement LUT functions, the 2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the connection matrix. When used to implement D Flip-Flop function, the two in put signals from the connection matrix go to the data (D) and clock (CLK) inputs for the Flip-Flop, with the output going back to the connection matrix.

Figure 10. 2-bit LUT0 or DFF0

Figure 11. 2-bit LUT1 or DFF1 Table 21. 2-bit LUT0 Truth Table. Table 22. 2-bit LUT1 Truth Table.

Table 23. DFF0 Register Settings Table 24. DFF1Register Settings

Table 25. 3-bit LUT0 Truth Table. Table 26. 3-bit LUT1 Truth Table.

Table 27. DFF2 Register Settings Table 28. DFF3 Register Settings

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay. output, which goes back into the connection matrix. When used as an 8-stage pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK) and Reset (nRST). reg <666:663> for OUT0 and reg <670:667> for OUT1. The 3-input mux is used to control the selection of the amount of delay. be the total time delay of the Pipe Delay logic cell. Figure 14. 3-bit LUT4 or Pipe Delay

8 Flip-Flop BlockIN

Table 30. Pipe Delay Register Settings Table 29. 3-bit LUT4 Truth Table.

Figure 15. 4-bit LUT0 or CNT/DLY2

Table 31. 4-bit LUT0 Truth Table.

Table 32. CNT/DLY2 Register Settings

11.0 Analog Comparators (ACMP)

a digital signal coming from the Connection Matrix. When ACMP is powered down, output is low. either created from an internal VREF or provided by way of the external sources. also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV or 200 mV. During powerup, the ACMP output will remain low, and then become valid 110 µs (max) after POR signal goes high, see Figure 16. Note: Regulator and Charge Pump set to automatic ON/OFF. use Vref selection VDD/4 and VDD/3 to maintain this input range. Figure 16. Maximum Power On Delay vs. VDD. Table 33. Gain Divider Input Resistance (typ). Table 34. Gain Divider Accuracy.

reference/source. Internal Vref accuracy is optimized near 1000 mV selection. Note: Power supply control options have influence on the ACMP operation. Force BandGap option is set as Disabled).

• Hysteresis: Input signal hyster esis options are Disable, 25 mV, 50 mV, 200 mV.
• Low Bandwidth: Enable, Disable;
• IN+ Gain: 1X, 0.5X, 0.33X, 0.25X;
• IN+ source:
• ACMP0 IN+ options are PIN 14, VDD;
• ACMP1 IN+ options are PIN 2, ACMP0 IN+;
• I N - s o u r c e :
• ACMP0 IN- options are 24 internal reference sources (50 mV – 1200 mV) and VDD/3, VDD/4, PIN 1;
• PWR UP=0 – ACMP is powered down; PWR UP=1 – ACMP is powered up.
• All ACMPs can have a common negative input. This can be achieved by configuring ACMP0 PIN 1 analog I/O connection.

11.1 ACMP0 Block Diagram

Figure 17. ACMP0 Block Diagram

11.2 ACMP0 Register Settings

Table 35. ACMP0 Register Settings

11.3 ACMP1 Block Diagram

Figure 18. ACMP1 Block Diagram

11.4 ACMP1 Register Settings

Table 36. ACMP1 Register Settings

11.5 Typical Performance Characteristics

Note: when VDD < 1.8V voltage reference should not exceed 1100 mV. Figure 19. Typical Input Voltage Offset vs. Voltage Reference at room temperature, LBW Mode – Disable, Vhys=0 mV, VDD=(1.7 – 5.5) V. Figure 20. Typical Input Threshold Variation (including Vref variation, ACMP offset) vs. Voltage reference at room temperature, LBW Mode – Disable, Vhys=0 mV.

11.6 Timing Characteristics

Figure 25. Maximum Propagation Delay Low-to-High Figure 26. Maximum Propagation Delay Low-to-High Figure 27. Maximum Propagation Delay High-to-Low Figure 28. Maximum Propagation Delay High-to-Low

12.0 Counters/Delay Generators (CNT/DLY)

option to chain from the output of the previous (N-1) CNT/DLY macrocell, to implement longer count / delay circuits. more information please see Section 10.4 4-Bit LUT or 8- Bit Counter / Delay Macrocells. Figure 33. CNT/DLY0

12.1 CNT/DLY0 Register Settings

12.2 CNT/DLY1 Register Settings

Table 38. CNT/DLY0 Register Settings Table 39. CNT/DLY1 Register Settings

12.3 CNT/DLY3 Register Settings

Table 40. CNT/DLY3 Register Settings

13.0 Programmable Delay / Edge Detector

period. See the timing diagrams below for further information. Note: The input signal must be longer than the delay, otherwise it will be filtered out.

13.1 Programmable Delay Timing Diagram - Edge Detector Output

Figure 36. Programmable Delay Figure 37. Edge Detector Output

Note: For delays and widths refer to Table 4. Figure 38. Delayed Edge Detector Output

13.2 Programmable Delay Register Settings

Table 41. Programmable Delay Register Settings

14.0 Additional Logic Functions

14.1 Deglitch Filter

Figure 39. Deglitch Filter

15.0 Voltage Reference (VREF)

15.1 Voltage Reference Overview

for the available selections for each analog comparator. Also see Figure 40 below, which shows the reference output structure.

15.2 VREF Selection Table

Table 42. VREF Selection Table.

11001 VDD / 4 VDD / 4

11000 VDD / 3 VDD / 3

15.3 VREF Block Diagram

Figure 40. Voltage Reference Block Diagram

16.0 RC Oscillator (RC Osc)

16.1 RC Oscillator Overview

Note: RC OSC power setting: "Auto Power On”. Figure 41. Maximum Power On Delay vs. VDD, RC OSC = 2 MHz. Figure 42. Maximum Power On Delay vs. VDD, RC OSC = 25 kHz.

lines <23>, and <24>. See Figure 43 below for details of the frequencies for each of these five Connection Matrix Inputs. will be turned off. The PWR DOWN signal has the highest priority.

16.2 RC OSC Block Diagram

Figure 43. RC OSC Block Diagram

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17.0 Power On Reset (POR)

The SLG46127 has a power-on reset (POR) macrocell to ensure cor rect device initialization and operation of all macrocells in the device. The purpose of the POR circuit is to have consisten t behavior and predictable results when the VDD power is first ramping to the device, and also while the VDD is falling during power-down. To accomplish this goal, the POR drives a defined sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of the I/O pins. This application note is created to explain the whole process of POR operation and GreenPAK chip behavior during the time while it is powering up and powering down.

17.1 General Operation

The SLG46127 is guaranteed to be powered down and nonoperational when the VDD voltage (on PIN12) is less than 0.6 V, but not less than -0.6 V. Another essential condition for the chip to be powered down is that no voltage higher (see Note 1) than the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3V, applying a voltage higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior. Note 1. There is a 0.6V margin due to forward drop voltage of the ESD protection diodes. To start the POR sequence in the SLG46127, the voltage applied on the VDD should be higher than the Power_ON threshold voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power_ON threshold. After the POR sequence has started, the SLG46127 will have a typical period of time to go through all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after the POR sequence is complete. Note 2. The Power_ON threshold can vary by PVT, but typically it is 1.6V. To power down the chip the VDD voltage should be lower than the operational and to guarantee that chip is powered down it should be less than 0.6V. All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step in the POR sequence releases the I/O structures from the high impedance state, at which time the device is operational. The pin configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.

17.2 POR Sequence

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 44. environmental factors, such as: slew rate, VDD value, temperature and even will vary from chip to chip (process influence). Figure 44. POR sequence

17.3 Blocks Output States During POR Sequence

states during the POR sequence (Figure 45 describes the output signals states). last are output PINs that become active and determined by the input signals. Figure 45. Internal Block States during POR sequence

18.0 Dual, 2A P-FET Power Switches

18.1 Power Switches Overview

The SLG46127 has a dual-channel, 44 m PMOS power switch designed to switch 1.71 to 5.5 V power rails up to 2 A per channel. GreenPAK Designer, allowing the user to generate integrated mixed-signal control circuits, or externally via PWR_SW_ONx. Whether controlled externally or internally, a low signal on either ONx or PWR_SW_ONx will close the P-FET Power Switch. P-FET Power Switch while the device is not powered.

18.2 Power Dissipation

Figure 46. Dual P-FET Power Switch

Figure 47. Power Dissipation Derating Curve

18.3 Power Switch Typical Performance

TA = 25 °C, VDD = 5.5 V, unless otherwise noted. Figure 48. Typical Output Characteristics Figure 49. Drain-Source On-Resistance vs. Drain Current Figure 50. Typical Drain-Source On-Resistance vs. Ambi- Figure 51. Gate-Source On-Resistance Gate-Source Volt-

000-0046127-101 Page 71 of 87 SLG46127

19.0 Appendix A - SLG46127 Register Definition

Address Signal Function Register Bit Definition reg <4:0> Matrix Out: PIN 14 Digital Output Source reg <9:5> Matrix Out: PIN1 Digital Output Source reg <14:10> Matrix Out: PIN2 Digital Output Source reg <19:15> Matrix Out : Output Enable of PIN2 reg <24:20> Matrix Out: In0 of LUT2_0 or Clock Input of DFF0 reg <29:25> Matrix Out: In1 of LUT2_0 or Data Input of DFF0 reg <34:30> Matrix Out: In0 of LUT2_1 or Clock Input of DFF1 reg <39:35> Matrix Out: In1 of LUT2_1 or Data Input of DFF1 reg <44:40> Matrix Out: In0 of LUT2_2 reg <49:45> Matrix Out: In1 of LUT2_2 reg <54:50> Matrix Out: In0 of LUT2_3 reg <59:55> Matrix Out: In1 of LUT2_3 reg <64:60> Matrix Out: In0 of LUT3_0 or Clock Input of DFF2 reg <69:65> Matrix Out: In1 of LUT3_0 or Data Input of DFF2 reg <74:70> Matrix Out: In2 of LUT3_0 or nRST Input of DFF2 reg <79:75> Matrix Out: In0 of LUT3_1 or Clock Input of DFF3 reg <84:80> Matrix Out: In1 of LUT3_1 or Data Input of DFF3 reg <89:85> Matrix Out: In2 of LUT3_1 or nRST (nSET) of DFF3 reg <94:90> Matrix Out: In0 of LUT3_2 reg <99:95> Matrix Out: In1 of LUT3_2 reg <104:100> Matrix Out: In2 of LUT3_2 reg <109:105> Matrix Out: In0 of LUT3_3 reg <114:110> Matrix Out: In1 of LUT3_3 reg <119:115> Matrix Out: In2 of LUT3_3 reg <124:120> Matrix Out: In0 of LUT3_4 or Input of Pipe Delay reg <129:125> Matrix Out: In1 of LUT3_4 or nRST of Pipe Delay reg <134:130> Matrix Out: In2 of LUT3_4 or Clock of Pipe Delay reg <139:135> Matrix Out: In0 of LUT4_0 or Input for Delay2 (Counter2) external clock reg <144:140> Matrix Out: In1 of LUT4_0 or Input for Delay2 data (Counter2 reset) reg <149:145> Matrix Out: In2 of LUT4_0 reg <154:150> Matrix Out: In3 of LUT4_0 reg <159:155> Matrix Out: Input f or Delay0 data (Counter0 reset) reg <164:160> Matrix Out: Input f or Delay1 data (Counter1 reset) reg <169:165> Matrix Out: Input for Delay0/1 (Counter0/1) external clock reg <174:170> Matrix Out: Input f or Delay3 (Counter3) external clock reg <179:175> Matrix Out: pdb (power down) for ACMP0 reg <184:180> Matrix Out: pdb (power down) for ACMP1 reg <189:185> Matrix Out: Input for programmable Delay (deglitch filter input)

000-0046127-101 Page 72 of 87 SLG46127 reg <194:190> Matrix Out: Power down for OSC reg <199:195> Pin15 Digital Output Source and Power Switch ON0 Source reg <204:200> Pin16 Digital Output Source and Power Switch ON1 Source reg <209:205> Matrix Out: PIN 10 Digital Output Source reg <214:210> Matrix Out: Output Enable of PIN10 reg <219:215> Matrix Out: PIN 11 Digital Output Source reg <223:220> Reserved Reserved DFF0/Latch reg <227:224> reg <224> DFF0 or Latch select 0: DFF function 1: Latch function reg <225> DFF0 output select 0: Q output 1: nQ output reg <226> DFF0 initial polarity select 0: Low 1: High reg <227> Unused if DFF/Latch selected Unused DFF1/Latch reg <231:228> reg <228> DFF1 or Latch select 0: DFF function 1:Latch function reg <229> DFF1 output select 0: Q output 1: nQ output reg <230> DFF1 initial polarity select 0: Low 1:High reg <231> Unused if DFF/Latch selected Unused LUT2_2 data reg <235:232> LUT2_2 data LUT2_2 data LUT2_1 data reg <239:236> LUT2_1 data LUT2_1 data LUT2_0/DFF0 reg <240> LUT2_0 or DFF0 select 0: LUT2_0 1: DFF0 LUT2_1/DFF1 reg <241> LUT2_1 or DFF1 select 0: LUT2_1 1: DFF1 LUT3_0 or DFF2/Latch reg <249:242> reg <242> DFF2 or Latch select 0: DFF function 1: Latch function reg <243> DFF2 output select 0: Q output 1: nQ output reg <244> DFF2 nRST/nSET select 0: nRST from matrix output 1: nSET from matrix output reg <245> DFF2 initial polarity select 0: Low 1: High reg <249:246> Unused if DFF/Latch selected Unused Register Bit Address Signal Function Register Bit Definition

000-0046127-101 Page 73 of 87 SLG46127 LUT3_1 or DFF3/Latch reg <257:250> reg <250> DFF3 or Latch select 0: DFF function 1: Latch function reg <251> DFF3 output select 0: Q output 1: nQ output reg <252> DFF3 nRST/nSET select 0: nRST from matrix output 1: nSET from matrix output reg <253> DFF3 initial polarity select 0: Low 1: High reg <257:254> Unused if DFF/Latch selected Unused LUT3_2 data reg <265:258> LUT3_2 data LUT3_2 data LUT3_3 data reg <273:266> LUT3_3 data LUT3_3 data LUT3_4 or pipe number select reg <281:274> reg <276:274>: OUT0 select data (pipe number) reg <279:277>: OUT1 select data (pipe number) reg <281:280>: Unused if Pipe Delay selected Unused LUT3/DFF Select reg <282> LUT3_0 or DFF2 select 0: LUT3_0 1: DFF2 reg <283> LUT3_1 or DFF3 select 0: LUT3_1 1: DFF3 reg <284> LUT3_4 or Pipe Delay output select 0: LUT3_4 1: Pipe Delay LUT4_0 or Counter/Delay2 mode selection reg <300:285> reg <285> Counter/Delay2 mode selection 0: Delay Mode 1: Counter Mode reg <288:286> Counter/Delay2 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock 111: Counter1 Overflow reg <296:289> Counter/Delay2 Control Data 1 – 255 (Delay time = (counter control data +2) /freq) reg <298:297> Delay2 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for Delay & counter reset) 01: Delay on falling edge only (for Delay & counter reset Delay) 10: on rising edge only (for Delay & counter reset) 11: No Delay on either falling or rising edges / high level reset for counter mode reg <300:299> Unused is Counter/Delay2 selected Unused reg <301> LUT4_0 or Counter2 select 0: LUT4_0, 1: Counter2 0: LUT4_0 1: Counter2 reg <302> Force RC oscillator on 0: Auto Power on 1: Force Power on Register Bit Address Signal Function Register Bit Definition

000-0046127-101 Page 74 of 87 SLG46127 reg <303> RC Oscillator frequency control 0: 25k 1: 2M reg <305:304> Osc cl ock pre-divider 00: div1 01: div2 10: div4 11: div8 reg <308:306> Internal Oscillator frequency divider control 0 for Matrix Input 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 reg <311:309> Internal Oscillator frequency divider control 1 for Matrix Input 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 reg <312> External Clock Source Select 0: Internal Oscillator 1: External Clock from PIN11 reg <313> Reserved Reserved Reserved Counter/Delay 0 reg <327:314> reg <314>Counter/Delay0 mode selection 0: Delay Mode 1: Counter Mode reg <317:315> Counter/Delay0 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock 111: Counter3 Overflow reg <325:318> Counter0 Control Data/Delay0 Time Control 1-255: (Delay time = (counter control data +2) /freq) reg <327:326> Delay0 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for Delay & counter reset) 01: Delay on falling edge only (for Delay & counter reset) 10: Delay on rising edge only (for Delay & counter reset) 11: No Delay on either falling or rising edges / high level reset for counter mode Register Bit Address Signal Function Register Bit Definition

000-0046127-101 Page 75 of 87 SLG46127 Counter/Delay 1 reg <341:328> reg <328> Counter/Delay1 mode selection 0: Delay Mode 1: Counter Mode reg <331:329> Counter/Delay1 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock 111: Counter0 Overflow reg <339:332> Counter1 Control Data/Delay1 Time Control 1-255: (Delay time = (counter control data +2) /freq) reg <341:340> Delay1 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for Delay & counter reset) 01: Delay on falling edge only (for Delay & counter reset) 10: Delay on rising edge only (for Delay & counter reset) 11: No Delay on either falling or rising edges / high level reset for counter mode Counter/Delay 3 reg <355:342> reg <342> Counter/Delay3 mode selection 0: Delay Mode 1: Counter Mode reg <345:343> Counter/Delay3 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock 111: Counter2 Overflow reg <353:346> Counter3 Control Data/Delay4 Time Control 1-255: (Delay time = (counter control data +2) /freq) reg <355:354> Delay3 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No Delay on either falling or rising edges Register Bit Address Signal Function Register Bit Definition

000-0046127-101 Page 76 of 87 SLG46127 ACMP0 reg <366:356> reg <360:356> ACMP0 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: EXT_VREF(PIN1) reg <362:361> ACMP0 hysteresis Enable 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) reg <364:363> ACMP0 positive Input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x reg <365> ACMP0 low bandwidth (typ: Max.1MHz) enable 0: off 1: on reg <366> ACMP0 positive input source select PIN14 and VDD 0: PIN14 1: VDD Register Bit Address Signal Function Register Bit Definition

000-0046127-101 Page 77 of 87 SLG46127 ACMP1 reg <378:367> reg <371:367> ACMP1 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: EXT_VREF(PIN1) reg <373:372> ACMP1 hysteresis Enable 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) reg <375:374> ACMP1 positive Input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x reg <376> ACMP1 100uA current source option 0: disable 1: enable reg <377> ACMP1 low bandwidth (typ: Max.1 MHz) en- able 0: off 1: on reg <378> ACMP1 positive input source select PIN2 and PIN14 0: PIN2 1: PIN14 PIN 1 reg <396:390> reg <392:390> PIN1 mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Analog Input / Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input / Output & Open drain reg <394:393> PIN1 pull up/down resistor value selec- tion 00: floating 01: 10K 10: 100K 11: 1M reg <395> PIN1 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <396> PIN1 driver strength selection 0: 1X 1: 2X Register Bit Address Signal Function Register Bit Definition

000-0046127-101 Page 78 of 87 SLG46127 PIN2 reg <403:397> reg <398:397> PIN2 mode control (sig_PIN2_oe =0) 00: Digital Input without Schmitt trigger 01: Digital Input with Schmitt trigger 11: Low Voltage Digital Input 10: Analog Input / Output reg <400:399> PIN2 mode control (sig_PIN2_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg <402:401> PIN2 pull up/down resistor value selec- tion 00: floating 01: 10K 10: 100K 11: 1M reg <403> PIN2 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable PIN10 reg <424:418> reg <419:418> PIN10 mode control (sig_PIN10_oe =0) 00: Digital Input without Schmitt trigger 01: Digital Input with Schmitt trigger 11: Low Voltage Digital Input 10: Analog Input / Output reg <421:420> PIN10 mode control (sig_PIN10_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg <423:422> PIN10 pull up/down resistor value selec- tion 00: floating 01: 10K 10: 100K 11: 1M reg <424> PIN10 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable PIN11 reg <431:425> reg <427:425> PIN11 mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved reg <429:428> PIN11 pull up/down resistor value selec- tion 00: floating 01: 10K 10: 100K 11: 1M reg <430> PIN11 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <431> PIN11 driver strength selection 0: 1X 1: 2X Register Bit Address Signal Function Register Bit Definition

000-0046127-101 Page 79 of 87 SLG46127 PIN 13 reg <382:379> reg <380:379> PIN13 mode control 00: Digital Input without Schmitt trigger 01: Digital Input with Schmitt trigger 10: Low voltage digital input 11: Reserved reg <382:381> PIN13 pull down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M PIN 14 reg <389:383> reg <385:383> PIN14 mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Analog Input / Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input / Output & Open drain reg <387:386> PIN14 pull up/down resistor value selec- tion 00: floating 01: 10K 10: 100K 11: 1M reg <388> PIN14 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <389> PIN14 driver strength selection 0: 1X 1: 2X PIN15 reg <410:404> reg <406:404> PIN15 mode control 000: Digital Input without Schmitt trigger 001: Reserved 010: Reserved 011: Reserved 100: Push Pull 101: Reserved 110: Reserved 111: Reserved reg <408:407> PIN15 pull up/down resistor value selec- tion 00: Reserved 01: Reserved 10: Reserved 11: Reserved reg <409> PIN15 pull up/down resistor select 0: Reserved 1: Reserved reg <410> PIN15 driver strength selection 0: Reserved 1: 2X Register Bit Address Signal Function Register Bit Definition

000-0046127-101 Page 80 of 87 SLG46127 PIN16 reg <417:411> reg <413:411> PIN16 mode control 000: Digital Input without Schmitt trigger 001: Reserved 010: Reserved 011: Reserved 100: Push Pull 101: Reserved 110: Reserved 111: Reserved reg <415:414> PIN16 pull down resistor value selection 00: Reserved 01: Reserved 10: Reserved 11: Reserved reg <416> PIN16 pull up/down resistor select 0: Reserved 1: Reserved reg <417> PIN16 driver strength selection 0: Reserved 1: 2X reg <432> Pipe Delay OUT1 polarity select bit 0: non-inverting 1: inverting reg <440:433> 8-bit pattern id 8-bit pattern id reg <441> filter0 output polarity select 0: non-inverting 1: inverting reg <443:442> Reserved Reserved reg <444> GPIO quick charge enable 0: Disable 1: Enable reg <445> Force bandgap on 0: Auto-mode 1: Enable reg <446> VREF Output Active Buffer Control 0: Disabled 1: Enabled reg <449:447> VREF Output Source Select 000: ACMP0 reference voltage 001: ACMP1 reference voltage 100: VDD/2 101: VDD/3 110: VDD/4 011: Reserved 010: Reserved 111: Reserved reg <450> NVM data read disable 0: Disable (read enable) 1: Enable (read disable) reg <451> NVM power down (or NVM data programming disable) 0: None (or programming enable) 1: Power Down (or programming disable) reg <452> Power Divider Power 0: Power down 1: Power On reg <453> POR Auto Power detect 0: Enable 1: Disable reg <454> Charge pump for analog block enable (when VDD <=

2.7 V turn on)

0: Disable (automatic on/off control) 1: Enable (always on) reg <455> VDD bypass enable 0: Regulator auto on 1: Regulator off (VDD bypass) reg <471:456> Reserved Reserved reg <479:472> Reserved Reserved Register Bit Address Signal Function Register Bit Definition

000-0046127-101 Page 81 of 87 SLG46127 reg <481:480> Reserved Reserved reg <482> PIN13 edge detect mode 0: rising edge 1: falling edge reg <483> Bypass the PIN13 0: PIN13 edge active 1: PIN13 high active reg <484> PIN13 reset enable 0: Disable 1: Enable reg <485> programmable Dela y or filter output select 0: programmable Delay output 1: filter output reg <487:486> Select the edge mode of programmable Delay & edge detector 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge Delay reg <489:488> Delay value select for programmable Delay & edge de- tector (VDD = 3.3 V, typical condition) 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns reg <490> Reserved Reserved reg <495:491> Reserved Reserved reg <501:496> Reserved Reserved reg <502> Reserved reg <503> Reserved Reserved reg <511:504> Reserved Reserved Register Bit Address Signal Function Register Bit Definition

000-0046127-101 Page 82 of 87 SLG46127

20.0 Package Top Marking System Definition

PPA Part Code + Assembly Code Pin 1 Identifier WWR Date Code + Revision Code NN Serial Number Code

000-0046127-101 Page 83 of 87 SLG46127

21.0 Package Drawing and Dimensions

16 Lead MSTQFN Package 1.6 x 2 mm JEDEC MO-252 IC Net Weight: 0.059 g

000-0046127-101 Page 84 of 87 SLG46127

22.0 Tape and Reel Specifications

23.0 Carrier Tape Drawing and Dimensions

# of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm]per Reel per Box Pockets Length [mm] Pockets Length [mm] MSTQFN 16L 1.6x2.0mm FC 0.4P Green 16 1.6x2x0.55 3000 3000 178/60 100 400 100 400 8 4 Package Type Pocket BTM Length [mm] Pocket BTM Width [mm] Pocket Depth [mm] Index Hole Pitch [mm] Pocket Pitch [mm] Index Hole Diameter [mm] Index Hole to Tape Edge [mm] Index Hole to Pocket Center [mm] Tape Width [mm] A0 B0 K0 P0 P1 D0 E F W MSTQFN 16L 1.6x2.0mm FC 0.4P Green

000-0046127-101 Page 85 of 87 SLG46127

24.0 Recommended Landing Pattern

25.0 Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow prof ile based on package volume of 2.2 mm 3 (nominal). More information can be found at www.jedec.org.

000-0046127-101 Page 86 of 87 SLG46127

26.0 Revision History

9/28/2017 1.01 Updated Power On Pins Settings Fixed typos Updated Power Switch Electrical Characteristics (each P-FET) Updated Absolute Maximum Conditions Updated Dual, 2A P-FET Power Switches 9/15/2017 1.00 Production Release Updated Power Switch Electrical Characteristics (each P-FET)

000-0046127-101 Page 87 of 87 SLG46127 Silego Website & Support Silego Technology Website Silego Technology provides online support via our website at http://www.silego.com/.This website is used as a means to make files and information easily available to customers. For more information regarding Silego Green products, please visit our website. Our Green product lines feature: GreenPAK: Programmable Mixed Signal Matrix products GreenFET1 / GreenFET3: MOSFET Drivers and ultra-small, low RDSon Load Switches GreenCLK1 / GreenCLK2 / GreenCLK3: Crystal replacement technology Products are also available for purchase directly from Silego at the Silego Online Store at http://www.silego.com /buy/. Silego Technical Support Datasheets and errata, application notes and example designs, u ser guides, and hardware support documents and the latest software releases are available at the Silego website or can be requested directly at info@silego.com. For specific GreenPAK design or applications questions and support please send e-mail requests to GreenPAK@silego.com Users of Silego products can receive assistance through several channels: Contact Your Local Sales Representative Customers can contact their local sales representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. More information regarding your lo cal representative is available at the Silego website or send a request to info@silego.com Contact Silego Directly Silego can be contacted directly via e-mail at info@silego.com or user submission form, located at the following URL: http://support.silego.com/ Other Information The latest Silego Technology press releases, listing of seminars and events, listings of world wide Silego Technology offices and representatives are all available at http://www.silego.com/ THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. SILEGO TECHNOLOGY DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICA- TIONS OR USES OF ITS PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE.