SLG46121VTR

2 manufacturer specifications

GreenPAK Dual Supply Programmable Mixed-signal Matrix March 10, 2023

Manufacturer variants: 2

Selected specification: Renesas Technology Corp

Documents: 2

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Online Datasheet

Read the Renesas Technology Corp document online.

SLG46121 RENESAS

Document overview

Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
PDF pages: 99

Technical content

Features

Logic & Mixed Signal Circuits
Highly Versatile Macrocells
1.8 V (±5%) to 5 V (±10%) VDD2 (VDD2 ≤ VDD)
Operating Temperature Range: -40to 85°C
RoHS Compliant / Halogen-Free
Pb-Free 12-pin STQFN: 1.6 x 1.6 x 0.55 mm, 0.4 mm pitch

Applications

Personal Computers and Servers
PC Peripherals
Consumer Electronics
Data Communications Equipment
Handheld and Portable Electronics Pin Configuration GND GPIO GPIO GPIO GPIO GPIO 4 7 GPI VDD 1 STQFN-12 (Top View) GPIO GPIO 5 6 GPIO VDD2 11 12 3-bit LUT3_1 or DFF5 Pin 1 VDD Pin 2 GPI Pin 3 GPIO Pin 4 GPIO Pin 12 GPIO Pin 11 VDD2 Pin 5 GPIO Pin 6 GPIO Pin 8 GPIO Pin 7 GND Pin 10 GPIO Pin 9 GPIO ACMP0 ACMP1 Look Up Tables (LUTs) Counters/Delay Generators CNT0 CNT1 2-bit LUT2_4 3-bit LUT3_5 3-bit LUT3_4 Combination Function Macrocells 2-bit LUT2_0 or DFF0 2-bit LUT2_1 or DFF1 3-bit LUT3_0 or DFF4 2bit LUT2_3 or DFF3 2-bit LUT2_2 or DFF2 3-bit LUT3_8 or Pipe Delay 3-bit LUT3_2 or DFF6 3-bit LUT3_3 or DFF7 4-bit LUT4_1 or CNT3 4bit LUT4_0 or CNT2 3-bit LUT2_6 3-bit LUT3_7 Vref RC Oscillator FILTER_0/Prog. Delay Additional Combination Functions POR Bandgap INV_0 Additional Logic Functions

000-0046121--111 Page 0 of 96 SLG46121

1.0 Overview

The SLG46121 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Mem ory (NVM) to configure the interconnect logic, the I/O Pins and the macrocells of the SLG46121. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The additional power supply (VDD2) on the SLG46121 provides the ability to interface two independent voltage domains within the same design. Users can configure pins, dedicated to each power supply, as inputs, outputs, or both (controlled dynamically by internal logic) to both VDD and VDD2 voltage domains. Using the available macrocells designers can implement mixed-signal functions bridging both domains or simply pass through level-translation in both High to Low and Low to High directions. The macrocells in the device include the following:

Two Analog Comparators (ACMP)
Voltage References (Vref)
Five Combinatorial Look Up Tables (LUTs)
One 2-bit LUTs
Four 3-bit LUTs
Twelve Combination Function Macrocell
Four Selectable DFF/Latch or 2-bit LUTs
Four Selectable DFF/Latch or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
Pipe Delay – 8 stage / 2 output, one 1 stage fixed output
Two Selectable Counter/Delay or 4-bit LUT
One Programmable Delay / Deglitch Filter
Two Counter / Delay Generators (CNT/DLY)
One 8-bit counter/delay
One 14-bit counter/delay with external clock/reset
Eight D Flip-Flop / Latches (DFF) (Part of Combina tion Function Macrocell)
Additional Logic Function - 1 Inverter
Pipe Delay – 8 stage/2 output (Part of Combination Function Macrocell)
One Bandgap
RC Oscillator (RC OSC)
Power On Reset (POR)

000-0046121--111 Page 1 of 96 SLG46121

2.0 Pin Description

2.1 Functional Pin Description

Pin # Pin Name Function

1 VDD Power Supply (PIN 2, 3, 4, 5, 6)

2 GPI General Purpose Input

3 GPIO General Purpose I/O or Analog Comparator 0 (+)

4 GPIO General Purpose I/O or Analog Comparator 0 (-)

5 GPIO General Purpose I/O

6 GPIO General Purpose I/O or Analog Comparator 1 (+) with OE

7 GND Ground

8 GPIO General Purpose I/O

9 GPIO General Purpose I/O

10 GPIO General Purpose I/O with OE and Vref output

11 VDD2 Power Supply (PIN 8, 9, 10, 12)

12 GPIO General Purpose I/O or External Clock Input

3.0 User Programmability

device as long as it remains powered and can be re-written as needed to facilitate rapid design changes. Once the design is finalized, the design file can be forwarded to Renesas to integrate into the production process. Figure 1. Steps to create a custom Renesas GreenPAK device

000-0046121--111 Page 3 of 96 SLG46121

4.0 Ordering Information

Note 1: Use SLG46121V to order. Shipments are automatically in Tape and Reel. Note 2: “TR” suffix is no longer used. It is a legacy naming convention shown here only for informational purposes. Part Number Type SLG46121V 12-pin STQFN SLG46121VTR 12-pin STQFN - Tape and Reel (3k units)

000-0046121--111 Page 4 of 96 SLG46121

5.0 Electrical Specifications

5.1 Absolute Maximum Conditions

5.2 Electrical Characteristics (1.8V ±5% V DD ) Parameter Min. Max. Unit Supply voltage on VDD relative to GND -0.5 7 V Supply voltage on VDD2 relative to GND -0.5 VDD + 0.5 V DC Input voltage Pins 2,3,4,5,6 GND - 0.5 VDD + 0.5 V Pins 8,9,10,12 VDD2 + 0.5 Maximum Average or DC Current (Through pin) Push-Pull 1x -- 12 mA Push-Pull 2x -- 17 OD 1x -- 18 OD 2x -- 28 Current at Input Pin -1.0 1.0 mA Storage Temperature Range -65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 500 -- V Moisture Sensitivity Level 1 Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage VDD2 ≤ VDD 1.71 1.80 1.89 V IQ Quiescent Current Static Inputs and Outputs (when ACMP, Vref and RC OSC are powered down and non-operational) -- 0.5 -- µA T A Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VACMP ACMP Input Voltage Range Positive Input 0 -- V DD Negative Input 0 -- 1.1 VIH HIGH-Level Input Voltage PIN 2, 3, 4, 5, 6 Logic Input 1.100 -- V DD V Logic Input with Schmitt Trigger 1.270 -- V DD V Low-Level Logic Input 0.980 -- V DD V VIL LOW-Level Input Voltage PIN 2, 3, 4, 5, 6 Logic Input -- -- 0.690 V Logic Input with Schmitt Trigger -- -- 0.440 V Low-Level Logic Input -- -- 0.520 V V HYS Schmitt Trigger Hysteresis Voltage Logic Input with Schmitt Trigger 0.280 0.445 0.600 V I LGK Input leakage PIN 2, 3, 4, 5, 6 (Absolute Value) -- 1 1000 nA V OH HIGH-Level Output Voltage PIN 2, 3, 4, 5, 6 Push-Pull 1X, Open Drain PMOS 1X, I OH = 100 µA 1.680 1.790 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 100 µA 1.700 1.800 -- V

000-0046121--111 Page 5 of 96 SLG46121 VOL LOW-Level Output Voltage PIN 2, 3, 4, 5, 6 Push-Pull 1X, I OL = 100 µA -- 0.020 0.030 V Push-Pull 2X, I OL = 100 µA -- 0.010 0.020 V Open Drain NMOS 1X, I OL = 100 µA -- 0.010 0.020 V Open Drain NMOS 2X, I OL = 100 µA -- 0.010 0.010 V IOH HIGH-Level Output Current (see Note 1) PIN 2, 3, 4, 5, 6 Push-Pull 1X, Open Drain PMOS 1X, V OH = V DD - 0.2 1.000 1.390 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = V DD - 0.2 2.100 2.680 -- mA IOL LOW-Level Output Current (see Note 1) PIN 2, 3, 4, 5, 6 Push-Pull 1X, V OL = 0.15 V 0.760 1.340 -- mA Push-Pull 2X, V OL = 0.15 V 1.520 2.660 -- mA Open Drain NMOS 1X, V OL = 0.15 V 1.530 2.670 -- mA Open Drain NMOS 2X, V OL = 0.15 V 3.060 5.136 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T TSU Startup Time from VDD rising past 1.35 V -- 0.31 -- ms PON THR Power On Threshold VDD Level Required to Start Up the Chip 1.180 1.353 1.516 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.730 0.914 1.103 V RPUP Pull Up Resistance

1 M Pull Up -- 1000 -- k Ω

100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance

1 M Pull Down -- 1000 -- k Ω

100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046121--111 Page 6 of 96 SLG46121 5.3 Electrical Characteristics (3.3V ±10% V DD ) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3.0 3.3 3.6 V IQ Quiescent Current Static Inputs and Outputs (when ACMP , Vref and RC OSC are powered down and non-operational) -- 0.75 -- µA T A Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VACMP ACMP Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage PIN 2, 3, 4, 5, 6 Logic Input 1.780 -- V DD V Logic Input with Schmitt Trigger 2.130 -- V DD V Low-Level Logic Input 1.130 -- V DD V VIL LOW-Level Input Voltage PIN 2, 3, 4, 5, 6 Logic Input -- -- 1.210 V Logic Input with Schmitt Trigger -- -- 0.950 V Low-Level Logic Input -- -- 0.690 V V HYS Schmitt Trigger Hysteresis Voltage Logic Input with Schmitt Trigger 0.498 0.685 0.866 V I LGK Input leakage PIN 2, 3, 4, 5, 6 (Absolute Value) -- 1 1000 nA V OH HIGH-Level Output Voltage PIN 2, 3, 4, 5, 6 Push-Pull 1X,Open Drain PMOS 1X, I OH = 3 mA 2.720 3.090 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 3 mA 2.850 3.190 -- V VOL LOW-Level Output Voltage PIN 2, 3, 4, 5, 6 Push-Pull 1X, I OL = 3 mA -- 0.180 0.280 V Push-Pull 2X, I OL = 3 mA -- 0.090 0.130 V Open Drain NMOS 1X, I OL = 3 mA -- 0.090 0.130 V Open Drain NMOS 2X, I OL = 3 mA -- 0.050 0.070 V IOH HIGH-Level Output Current (see Note 1) PIN 2, 3, 4, 5, 6 Push-Pull 1X, Open Drain PMOS 1X, V OH = 2.4 V 6.010 10.150 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = 2.4 V 11.460 19.610 -- mA IOL LOW-Level Output Current (see Note 1) PIN 2, 3, 4, 5, 6 Push-Pull 1X, V OL = 0.4 V 4.060 6.440 -- mA Push-Pull 2X, V OL = 0.4 V 8.130 12.360 -- mA Open Drain NMOS 1X, V OL = 0.4 V 8.130 12.410 -- mA Open Drain NMOS 2X, V OL = 0.4 V 16.260 22.900 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T

000-0046121--111 Page 7 of 96 SLG46121

5.4 Electrical Characteristics (5V ±10% V DD )

(Per chip side, see Note 2) T TSU Startup Time from VDD rising past 1.35 V -- 0.31 -- ms PON THR Power On Threshold VDD Level Required to Start Up the Chip 1.180 1.353 1.516 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.730 0.914 1.103 V RPUP Pull Up Resistance 100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance 100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V IQ Quiescent Current Static Inputs and Outputs (when ACMP , Vref and RC OSC are powered down and non-operational) -- 1.0 -- µA T A Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VACMP ACMP Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage PIN 2, 3, 4, 5, 6 Logic Input 2.640 -- V DD V Logic Input with Schmitt Trigger 3.160 -- V DD V Low-Level Logic Input 1.230 -- V DD V VIL LOW-Level Input Voltage PIN 2, 3, 4, 5, 6 Logic Input -- -- 1.840 V Logic Input with Schmitt Trigger -- -- 1.510 V Low-Level Logic Input -- -- 0.780 V V HYS Schmitt Trigger Hysteresis Voltage Logic Input with Schmitt Trigger 0.694 0.923 1.182 V I LGK Input leakage PIN 2, 3, 4, 5, 6 (Absolute Value) -- 1 1000 nA V OH HIGH-Level Output Voltage PIN 2, 3, 4, 5, 6 Push-Pull 1X,Open Drain PMOS 1X, I OH = 5 mA 4.170 4.740 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 5 mA 4.320 4.860 -- V Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046121--111 Page 8 of 96 SLG46121 VOL LOW-Level Output Voltage PIN 2, 3, 4, 5, 6 Push-Pull 1X, I OL = 5 mA -- 0.230 0.330 V Push-Pull 2X, I OL = 5 mA -- 0.120 0.160 V Open Drain NMOS 1X, I OL = 5 mA -- 0.120 0.160 V Open Drain NMOS 2X, I OL = 5 mA -- 0.070 0.090 V IOH HIGH-Level Output Current (see Note 1) PIN 2, 3, 4, 5, 6 Push-Pull 1X, Open Drain PMOS 1X, V OH = 2.4 V 21.980 29.010 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = 2.4 V 41.886 55.990 -- mA IOL LOW-Level Output Current (see Note 1) PIN 2, 3, 4, 5, 6 Push-Pull 1X, V OL = 0.4 V 6.010 9.730 -- mA Push-Pull 2X, V OL = 0.4 V 11.590 19.460 -- mA Open Drain NMOS 1X, V OL = 0.4 V 11.760 19.460 -- mA Open Drain NMOS 2X, V OL = 0.4 V 19.120 35.952 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T TSU Startup Time from VDD rising past 1.35 V -- 0.31 -- ms PON THR Power On Threshold VDD Level Required to Start Up the Chip 1.180 1.353 1.516 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.730 0.914 1.103 V RPUP Pull Up Resistance 100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance 100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046121--111 Page 9 of 96 SLG46121 5.5 Electrical Characteristics (1.8V ±5% V DD2 ) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD2 Supply Voltage VDD2 ≤ VDD 1.71 1.80 1.89 V ILGK Input leakage PIN 8, 9, 10, 12 (Absolute Value) -- 1 1000 nA V IH2 HIGH-Level Input Voltage PIN 8, 9, 10, 12 Logic Input 1.100 -- V DD2 V Logic Input with Schmitt Trigger 1.270 -- V DD2 V Low-Level Logic Input 0.980 -- V DD2 V VIL2 LOW-Level Input Voltage PIN 8, 9, 10, 12 Logic Input -- -- 0.690 V Logic Input with Schmitt Trigger -- -- 0.440 V Low-Level Logic Input -- -- 0.520 V V OH2 HIGH-Level Output Voltage PIN 8, 9, 10, 12 Push-Pull 1X, Open Drain PMOS 1X, I OH = 100 µA 1.680 1.790 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 100 µA 1.700 1.800 -- V VOL2 LOW-Level Output Voltage PIN 8, 9, 10, 12 Push-Pull 1X, I OL = 100 µA -- 0.020 0.030 V Push-Pull 2X, I OL = 100 µA -- 0.010 0.020 V Open Drain NMOS 1X, I OL = 100 µA -- 0.010 0.020 V Open Drain NMOS 2X, I OL = 100 µA -- 0.010 0.010 V IOH2 HIGH-Level Output Current (see Note 1) PIN 8, 9, 10, 12 Push-Pull 1X, Open Drain PMOS 1X, V OH = V DD - 0.2 1.000 1.390 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = V DD - 0.2 2.100 2.680 -- mA IOL2 LOW-Level Output Current (see Note 1) PIN 8, 9, 10, 12 Push-Pull 1X, V OL = 0.15 V 0.760 1.340 -- mA Push-Pull 2X, V OL = 0.15 V 1.520 2.660 -- mA Open Drain NMOS 1X, V OL = 0.15 V 1.530 2.670 -- mA Open Drain NMOS 2X, V OL = 0.15 V 3.060 5.136 -- mA IVDD2 Maximum Average or DC Current Through VDD2 Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and 12 to another.

000-0046121--111 Page 10 of 96 SLG46121 5.6 Electrical Characteristics (3.3V ±10% V DD2 ) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD2 Supply Voltage VDD2 ≤ VDD 1.71 -- V DD2 V ILGK Input leakage PIN 8, 9, 10, 12 (Absolute Value) -- 1 1000 nA V IH2 HIGH-Level Input Voltage PIN 8, 9, 10, 12 Logic Input, V DD2 = 1.8 V 1.100 -- V DD2 V Logic Input with Schmitt Trigger, V DD2 = 1.8 V 1.270 -- V DD2 V Low-Level Logic Input, V DD2 = 1.8 V 0.980 -- V DD2 V VIL2 LOW-Level Input Voltage PIN 8, 9, 10, 12 Logic Input, V Logic Input with Schmitt Trigger, V Low-Level Logic Input, V DD2 = 1.8 V -- -- 0.520 V VOH2 HIGH-Level Output Voltage PIN 8, 9, 10, 12 Push-Pull 1X, Open Drain PMOS 1X, I OH = 100 µA, V DD2 = 1.8 V 1.680 1.790 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 100 µA, V DD2 = 1.8 V 1.700 1.800 -- V VOL2 LOW-Level Output Voltage PIN 8, 9, 10, 12 Push-Pull 1X, I OL = 100 µA, V DD2 = 1.8 V -- 0.020 0.030 V Push-Pull 2X, I OL = 100 µA, V DD2 = 1.8 V -- 0.010 0.020 V Open Drain NMOS 1X, I OL = 100 µA, V DD2 = 1.8 V -- 0.010 0.020 V Open Drain NMOS 2X, I OL = 100 µA, V DD2 = 1.8 V -- 0.010 0.010 V IOH2 HIGH-Level Output Current (see Note 1) PIN 8, 9, 10, 12 Push-Pull 1X, Open Drain PMOS 1X, V OH = V DD - 0.2, V DD2 = 1.8 V 1.000 1.390 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = V DD - 0.2, V DD2 = 1.8 V 2.100 2.680 -- mA IOL2 LOW-Level Output Current (see Note 1) PIN 8, 9, 10, 12 Push-Pull 1X, V OL = 0.15 V, V DD2 = 1.8 V 0.760 1.340 -- mA Push-Pull 2X, V OL = 0.15 V, V DD2 = 1.8 V 1.520 2.660 -- mA Open Drain NMOS 1X, V OL = 0.15 V, V DD2 = 1.8 V 1.530 2.670 -- mA Open Drain NMOS 2X, V OL = 0.15 V, V DD2 = 1.8 V 3.060 5.136 -- mA IVDD2 Maximum Average or DC Current Through VDD2 Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and 12 to another.

000-0046121--111 Page 11 of 96 SLG46121

5.7 Electrical Characteristics (5V ±10% V DD2 )

Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD2 Supply Voltage VDD2 ≤ VDD 1.71 -- V DD2 V ILGK Input leakage PIN 8, 9, 10, 12 (Absolute Value) -- 1 1000 nA V IH2 HIGH-Level Input Voltage PIN 8, 9, 10, 12 Logic Input, V DD2 = 3.3 V 1.780 -- V DD2 V Logic Input with Schmitt Trigger, V DD2 = 3.3 V 2.130 -- V DD2 V Low-Level Logic Input, V DD2 = 3.3 V 1.130 -- V DD2 V VIL2 LOW-Level Input Voltage PIN 8, 9, 10, 12 Logic Input, V Logic Input with Schmitt Trigger, V Low-Level Logic Input, V DD2 = 3.3 V -- -- 0.690 V VOH2 HIGH-Level Output Voltage PIN 8, 9, 10, 12 Push-Pull 1X,Open Drain PMOS 1X, I OH = 3 mA, V DD2 = 3.3 V 2.720 3.090 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 3 mA, V DD2 = 3.3 V 2.850 3.190 -- V VOL2 LOW-Level Output Voltage PIN 8, 9, 10, 12 Push-Pull 1X, I OL = 3 mA, V DD2 = 3.3 V -- 0.180 0.280 V Push-Pull 2X, I OL = 3 mA, V DD2 = 3.3 V -- 0.090 0.130 V Open Drain NMOS 1X, I OL = 3 mA, V DD2 = 3.3 V -- 0.090 0.130 V Open Drain NMOS 2X, I OL = 3 mA, V DD2 = 3.3 V -- 0.050 0.070 V IOH2 HIGH-Level Output Current (see Note 1) PIN 8, 9, 10, 12 Push-Pull 1X, Open Drain PMOS 1X, V OH = 2.4 V, V DD2 = 3.3 V 6.010 10.150 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = 2.4 V, V DD2 = 3.3 V 11.460 19.610 -- mA IOL2 LOW-Level Output Current (see Note 1) PIN 8, 9, 10, 12 Push-Pull 1X, V OL = 0.4 V, V DD2 = 3.3 V 4.060 6.440 -- mA Push-Pull 2X, V OL = 0.4 V, V DD2 = 3.3 V 8.130 12.360 -- mA Open Drain NMOS 1X, V OL = 0.4 V, V DD2 = 3.3 V 8.130 12.410 -- mA Open Drain NMOS 2X, V OL = 0.4 V, V DD2 = 3.3 V 16.260 22.900 -- mA VIH2 HIGH-Level Input Voltage PIN 8, 9, 10, 12 Logic Input, V DD2 = 1.8 V 1.100 -- V DD V Logic Input with Schmitt Trigger, V DD2 = 1.8 V 1.270 -- V DD V Low-Level Logic Input, V DD2 = 1.8 V 0.980 -- V DD V VIL2 LOW-Level Input Voltage PIN 8, 9, 10, 12 Logic Input, V Logic Input with Schmitt Trigger, V Low-Level Logic Input, V DD2 = 1.8 V -- -- 0.520 V IIH2 HIGH-Level Input Current PIN 8, 9, 10, 12 Logic Input Pins; V IN = 1.8 V,

000-0046121--111 Page 12 of 96 SLG46121 IIL2 LOW-Level Input Current PIN 8, 9, 10, 12 Logic Input Pins; V IN = 0 V, VOH2 HIGH-Level Output Voltage PIN 8, 9, 10, 12 Push-Pull 1X, Open Drain PMOS 1X, I OH = 100 µA, V DD2 = 1.8 V 1.680 1.790 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 100 µA, V DD2 = 1.8 V 1.700 1.800 -- V VOL2 LOW-Level Output Voltage PIN 8, 9, 10, 12 Push-Pull 1X, I OL = 100 µA, V DD2 = 1.8 V -- 0.020 0.030 V Push-Pull 2X, I OL = 100 µA, V DD2 = 1.8 V -- 0.010 0.020 V Open Drain NMOS 1X, I OL = 100 µA, V DD2 = 1.8 V -- 0.010 0.020 V Open Drain NMOS 2X, I OL = 100 µA, V DD2 = 1.8 V -- 0.010 0.010 V IOH2 HIGH-Level Output Current (see Note 1) PIN 8, 9, 10, 12 Push-Pull 1X, Open Drain PMOS 1X, V OH = V DD - 0.2, V DD2 = 1.8 V 1.000 1.390 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = V DD - 0.2, V DD2 = 1.8 V 2.100 2.680 -- mA IOL2 LOW-Level Output Current (see Note 1) PIN 8, 9, 10, 12 Push-Pull 1X, V OL = 0.15 V, V DD2 = 1.8 V 0.760 1.340 -- mA Push-Pull 2X, V OL = 0.15 V, V DD2 = 1.8 V 1.520 2.660 -- mA Open Drain NMOS 1X, V OL = 0.15 V, V DD2 = 1.8 V 1.530 2.670 -- mA Open Drain NMOS 2X, V OL = 0.15 V, V DD2 = 1.8 V 3.060 5.136 -- mA IVDD2 Maximum Average or DC Current Through VDD2 Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

5.8 IDD Estimator

5.9 Timing Estimator

Table 1. Typical Current estimated for each macrocell. Table 2. Typical Delay estimated for each macrocell.

5.10 Typical Counter/Delay Offset Measurements

5.11 Expected Delays and Widths

Table 3. Typical Counter/Delay Offset Measurements.

2 MHz either 35 14 10 ns

Table 4. Expected Delays and Widths for Programmable Delay (typical).

5.12 Typical Pulse Width Performance

Table 5. Typical Pulse Width Performance.

000-0046121--111 Page 16 of 96 SLG46121

6.0 Summary of Macrocell Function

6.1 I/O Pins

Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
Open Drain NMOS and Open Drain PMOS Outputs
Push Pull Outputs
Analog I/O
10 k Ω /100 k Ω /1 M Ω pull-up/pull-down resistors

6.2 Connection Matrix

Digital matrix for circuit connections based on us er design

6.3 Analog Comparators (2 total)

Selectable hysteresis 0 mV/25 mV/50 mV/200 mV and selectable gain 1x/0.5x/0.33x/0.25x

6.4 Voltage Reference

Used for references on Analog Comparators
Can also be driven to external pins

6.5 Combinational Logic Look Up Tables (LUTs – 5 total)

One 2-bit Lookup Tables
Four 3-bit Lookup Tables

6.6 Combination Function Macrocells (12 total)

Four Selectable DFF/Latches or 2-bit LUTs
Four Selectable DFF/Latches or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
Two Selectable CNT/DLYs or 4-bit LUTs
One Programmable Delay or Deglitch Filter

6.7 Delays/Counters (2 total)

One 8-bit delay/counter with external clock/reset: Range 1-255 clock cycles
One 14-bit delay/counter with external clock: Rang e 1-16383 clock cycles

6.8 Pipe Delay (Part of Combination Function Macrocell)

8 stage / 2 output
Two 1-8 stage selectable outputs
One 1 stage fixed output

6.9 Additional Logic Functions (Part of Combination Function Macrocell)

One Deglitch filter macrocell
One Programmable Delay
163 ns / 305 ns / 446 ns / 588 ns @ 3.3 V
Includes Edge Detection function

000-0046121--111 Page 17 of 96 SLG46121

6.10 Additional Logic Function

One Inverter

6.11 RC Oscillator

25 kHz and 2 MHz selectable frequency
First Stage Clock pre=divider (4): OSC/1, OSC/2, O SC/4, and OSC/8
Second stage divider control with two outputs, OUT 0 and OUT1 (8): selectable (OSC/1, OSC/2, OSC/3, OSC/4, OSC/8, OSC/12, OSC/24, or OSC/64)

6.12 Power On Reset (POR)

000-0046121--111 Page 18 of 96 SLG46121

7.0 I/O Pins

The SLG46121 has a total of 9 multi-function I/O pi ns which can function as either a user defined Inpu t or Output, as well as serving as a special function (such as outputting the voltage reference). Refer to Section 2.0 Pin Description for pin definitions. All of the 9 user defined I/O pins on the SLG46121, except Pin 2 can serve as both digital input and digital output. Pin 2 can only serve as a digital input pin. The high side of the user selectable push-pull or o pen-drain pin output structures for each GPIO is co nnected to either VDD or VDD2. This allows for the appropriate voltage level output compatible with each voltage domain. The level shifters are located in lower power IO PADs (pins 8, 9, 10 and 12) powered from VDD2. All configuration registers of the SLG46121 are powered from VDD, so it is possible to maintain the configuration information even after VDD2 was turned off, discharged and turned back on again. Pins 2, 3, 4, 5 and 6 are powered V DD and pins 8, 9, 10 and 12 are powered from V DD2. All internal macrocells are powered from VDD. Voltage on V DD2 Pin must be less or equal voltage on V DD Pin. In case V DD2 floating and any Pin powered from V DD2 is configured as input, ESD pin protection diodes must be considered when applying an input signal to the pin. This will cause a significant current leakage. In case V DD2 floating and any Pin powered from V DD2 is configured as Output, the pin will behave as NMOS Open Drain. It is not recommended to connect V DD2 to the GND.

7.1 Input Modes

Each I/O pin can be configured as a digital input p in with/without buffered Schmitt Trigger, or can al so be configured as a low voltage digital input. Pins 3, 4, and 6 can also be configured to serve as analog inputs to the on-chip comparators.

7.2 Output Modes

Pins 3, 4, 5, 6, 8, 9, 10, and 12 can all be configured as digital output pins.

7.3 Pull Up/Down Resistors

All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors are 10 k Ω , 100 k Ω and 1 M Ω . In the case of Pin 2, the resistors are fixed to a pull-down configuration. In the case of all other I/O pins, the internal resistors can be configured as either pull-up or pull-downs.

7.4 I/O Register Settings

7.4.1 PIN 2 Register Settings

7.4.2 PIN 3 Register Settings

Table 6. PIN 2 Register Settings Table 7. PIN 3 Register Settings

7.4.3 PIN 4 Register Settings

7.4.4 PIN 5 Register Settings

Table 8. PIN 4 Register Settings Table 9. PIN 5 Register Settings

7.4.5 PIN 6 Register Settings

7.5 PIN 8 Register Settings

Table 10. PIN 6 Register Settings Table 11. PIN 8 Register Settings

7.5.1 PIN 9 Register Settings

7.6 PIN 10 Register Settings

Table 12. PIN 9 Register Settings Table 13. PIN 10 Register Settings

7.7 PIN 12 Register Settings

Table 14. PIN 12 Register Settings

7.8 GPI IO Structure

7.8.1 GPI IO Structure (for Pin 2)

Figure 2. PIN 2 GPI IO Structure Diagram

7.9 Matrix OE IO Structure

7.9.1 Matrix OE IO Structure (for Pin 6)

Figure 3. Matrix OE IO Structure Diagram

7.9.2 Matrix OE IO Structure (for Pin 10)

Figure 4. Matrix OE IO Structure Diagram

7.10 Register OE IO Structure

7.10.1 Register OE IO Structure (for Pins 3, 4, 5)

Figure 5. Register OE IO Structure Diagram

7.10.2 Register OE IO Structure (for Pins 8, 9, 12)

Figure 6. Register OE IO Structure Diagram

8.0 Connection Matrix

macrocell uses a 6-bit register to select one of these 40 input lines. For a complete list of the SLG46121’s register table, see Section 17.0 Appendix A - SLG46121 Register Definition. Figure 7. Connection Matrix Figure 8. Connection Matrix Example

8.1 Matrix Input Table

Table 15. Matrix Input Table

0 VSS 0 0 0 0 0 0

6 LUT2_0 output (DFF/LATCH_0 output) 0 0 0 1 1 0

7 LUT2_1 output (DFF/LATCH_1 output) 0 0 0 1 1 1

8 LUT2_2 output (DFF/LATCH_2 output) 0 0 1 0 0 0

9 LUT2_3 output (DFF/LATCH_3 output) 0 0 1 0 0 1

10 LUT2_4 output 0 0 1 0 1 0

12 LUT3_0 output (DFF/LATCH_4 output with resetb or seb) 0 0 1 1 0 0

13 LUT3_1 output (DFF/LATCH_5 output with resetb or seb) 0 0 1 1 0 1

14 LUT3_2 output (DFF/LATCH_6 output with resetb or seb) 0 0 1 1 1 0

15 LUT3_3 output (DFF/LATCH_7 output with resetb or seb) 0 0 1 1 1 1

16 LUT3_4 output 0 1 0 0 0 0

17 LUT3_5 output 0 1 0 0 0 1

18 LUT3_6 output 0 1 0 0 1 0

19 LUT3_7 output 0 1 0 0 1 1

20 LUT3_8 output (pipe delay output0) 0 1 0 1 0 0

21 LUT4_0 output (CNT_DLY3 output (8 bit w/ ext CK,r eset)) 0 1 0 1 0 1

22 LUT4_1 output (CNT_DLY4 output (8 bit w/ ext CK,r eset)) 0 1 0 1 1 0

23 CNT_DLY0(14bit) output 0 1 0 1 1 1

24 CNT_DLY1 output (8 bit w/ ext CK,reset) 0 1 1 0 0 0

25 Edge detector output from CNT_DLY4 0 1 1 0 0 1

26 ACMP_0 output 0 1 1 0 1 0

27 ACMP_1 output 0 1 1 0 1 1

29 Programmable delay with edge detector output (Deglitch filter out -

32 Bandgap OK signal 1 0 0 0 0 0

33 Resetb_core as matrix input 1 0 0 0 0 1

37 Inverter INV_0 Output 1 0 0 1 0 1

38 Pin12 digital Input 1 0 0 1 1 0

39 VDD 1 0 0 1 1 1

8.2 Matrix Output Table

Table 16. Matrix Output Table

9.0 Combinatorial Logic

Combinatorial logic is supported via five Lookup Tables (LUTs) within the SLG46121. There is one 2-bit LUT and four 3-bit LUTs. 10.0 Combination Function Macrocells. devices (AND, NAND, OR, NOR, XOR, XNOR). created within each of the two 2-bit LUT logic cells. Figure 9. 2-bit LUT Table 18. 2-bit LUT Standard Digital Functions. Table 17. 2-bit LUT4 Truth Table.

Figure 10. 3-bit LUTs Table 19. 3-bit LUT4 Truth Table. Table 20. 3-bit LUT5 Truth Table. Table 21. 3-bit LUT6 Truth Table. Table 22. 3-bit LUT7 Truth Table.

created within each of the two 3-bit LUT logic cells. Table 23. 3-bit LUT Standard Digital Functions.

000-0046121--111 Page 37 of 96 SLG46121

10.0 Combination Function Macrocells

The SLG46121 has twelve combination function macroc ells that can serve more than one logic or timing f unction. In elven of these cases, they can serve as a Look Up Table (LUT ), or as another logic or timing function. In the l ast case, it can serve as either a programmable delay or deglitch filter. See the list below for the functions that can be implemented in these macrocells.

Four macrocells that can serve as either 2-bit LUT s or as D Flip Flops
Four macrocells that can serve as either 3-bit LUT s or as D Flip Flops
One macrocell that can serve as either 3-bit LUT o r as Pipe Delay
Two macrocells that can serve as either 4-bit LUTs or as 8-Bit Counter / Delays
One macrocell that can serve as either a Programma ble Delay or as a Deglitch Filter Inputs/Outputs for the eleven combination function macrocells are configured from the connection matri x with specific logic functions being defined by the state of NVM bits. When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR). When used as a D Flip Flop / Latch, the source and destination of the inputs and outputs for the DFF/Latches are configured from the connection matrix. All DFF/Latch macrocells have user selection for initial state, and all have th e option to connect both the Q and Q Bar outputs to the connection matrix. The m acrocells DFF4, DFF5, DFF6 and DFF7 have an additio nal input from the matrix that can serve as a nSet or nReset function to the macrocell. The operation of the D Flip-Flop and Latch will follow the functional descriptions below: DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change Latch: if CLK = 0, then Q = D 10.1 2-Bit LUT or D Flip Flop Macrocells There are four macrocells that can serve as either 2-bit LUTs or as D Flip Flops. When used to implement LUT functions, the 2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the connection matrix. When used to implement D Flip Flop function, the two input signals from the connection matrix go to the data (d) and clock (clk) inputs for the Flip Flop, with the output going back to the connection matrix.

Table 24. 2-bit LUT0 Truth Table. Table 25. 2-bit LUT1 Truth Table. Table 26. 2-bit LUT3 Truth Table. Table 27. 2-bit LUT4 Truth Table.

Table 28. DFF0 Register Settings Table 29. DFF1 Register Settings Table 30. DFF2 Register Settings

Table 31. DFF3 Register Settings

Table 32. 3-bit LUT0 Truth Table. Table 33. 3-bit LUT1 Truth Table. Table 34. 3-bit LUT2 Truth Table. Table 35. 3-bit LUT3 Truth Table.

Table 36. DFF4 Register Settings Table 37. DFF5 Register Settings Table 38. DFF6 Register Settings

Table 39. DFF7 Register Settings

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay. output, which goes back into the connection matrix. When used as an 8-stage pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK) and Reset (nRESET). options for 1 to 8 stages of delay. be the total time delay of the Pipe Delay logic cell. Figure 19. 3-bit LUT4 or Pipe Delay

8 Flip-Flops IN

Table 41. Pipe Delay Register Settings Table 40. 3-bit LUT8 Truth Table.

Note: Counters initialize with counter data=0 after POR. Figure 20. 4-bit LUT0 or CNT/DLY2

Figure 21. 4-bit LUT1 or CNT/DLY3

4-bit LUT Standard Digital Functions. Table 42. 4-bit LUT0 Truth Table. Table 43. 4-bit LUT1 Truth Table.

Table 45. CNT/DLY2 Register Settings Table 46. CNT/DLY3 Register Settings

10.5 Programmable Delay / Edge Detector

period. See the timing diagrams below for further information. Note : The input signal must be longer than the delay, otherwise it will be filtered out.

10.6 Programmable Delay Timing Diagram - Edge Detector Output

Figure 22. Programmable Delay Figure 23. Edge Detector Output

Note: For delays and widths refer to Table 4 . Figure 24. Delayed Edge Detector Output

10.6.1 Programmable Delay Register Settings

Table 47. Programmable Delay Register Settings

10.7 Deglitch Filter

Figure 25. Deglitch Filter

11.0 Analog Comparators (ACMP)

a digital signal coming from the Connection Matrix. When ACMP is powered down, output is low. either created from an internal VREF or provided by way of the external sources. also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV or 200 mV. Note: Applies to first time power ON. Note: Regulator and Charge Pump set to automatic ON/OFF. use Vref selection VDD/4 and VDD/3 to maintain this input range. Figure 26. Maximum Power On Delay vs. VDD. Table 48. Gain Divider Input Resistance (typ).

12 POWER ON DELAY (µS)

reference/source. Internal Vref accuracy is optimized near 1000 mV selection. Note: Power supply control options have influence on the ACMP operation. Force BandGap option is set as Disabled).

Hysteresis: Input signal hysteresis options are Di sable, 25 mV, 50 mV, 200 mV.
Low Bandwidth: Enable, Disable;
IN+ Gain: 1X, 0.5X, 0.33X, 0.25X;
IN+ source:
ACMP0 IN+ options are PIN 3, VDD;
ACMP1 IN+ options are PIN 6, ACMP0 IN+;
IN- source:
ACMP0 IN- options are 24 internal reference source s (50 mV – 1200 mV) and VDD/3, VDD/4, PIN 4;
PWR UP=0 – ACMP is powered down; PWR UP=1 – ACMP i s powered up. All ACMPs can have a common negative input. This can be achieved by configuring ACMP0 PIN 4 analog I/O connection.

Table 49. Gain Divider Accuracy.

11.1 ACMP0 Block Diagram

11.2 ACMP0 Register Settings

Figure 27. ACMP0 Block Diagram Table 50. ACMP0 Register Settings

11.3 ACMP1 Block Diagram

Figure 28. ACMP1 Block Diagram

11.4 ACMP1 Register Settings

Table 51. ACMP1 Register Settings

11.5 Typical Performance Characteristics

Note: when VDD < 1.8V voltage reference should not exceed 1100 mV. Figure 29. Typical Input Voltage Offset vs. Voltage Reference at room temperature, LBW Mode – Disable, Vhys=0 mV, VDD=(1.7 – 5.5) V. Figure 30. Typical Input Threshold Variation (including Vref variation, ACMP offset) vs. Voltage reference at room temperature, LBW Mode – Disable, Vhys=0 mV.

11.6 Timing Characteristics

Figure 35. Maximum Propagation Delay Low-to-High Figure 36. Maximum Propagation Delay Low-to-High

1100 E (mV)

Figure 37. Maximum Propagation Delay High-to-Low Figure 38. Maximum Propagation Delay High-to-Low

Figure 39. Maximum Propagation Delay Low-to-High Figure 40. Maximum Propagation Delay Low-to-High Figure 41. Maximum Propagation Delay High-to-Low Figure 42. Maximum Propagation Delay High-to-Low

12.0 Counters/Delay Generators (CNT/DLY)

of the previous (N-1) CNT/DLY macrocell, to implement longer count / delay circuits. Input (Delay_In/Reset_In), and one for an external counter/clock source. For more information please see Section 10.4 4-Bit LUT or 8- Bit Counter / Delay Macrocells. Figure 43. CNT/DLY0

12.1 CNT/DLY0 Register Settings

Figure 44. CNT/DLY1 Table 53. CNT/DLY0 Register Settings

12.2 CNT/DLY1 Register Settings

Table 54. CNT/DLY1 Register Settings

13.0 Voltage Reference (VREF)

13.1 Voltage Reference Overview

13.2 VREF Selection Table

Table 55. VREF Selection Table.

11001 VDD / 4 VDD / 4

11000 VDD / 3 VDD / 3

13.3 VREF Block Diagram

Figure 45. Voltage Reference Block Diagram

14.0 RC Oscillator (RC Osc)

14.1 RC Oscillator Overview

Note: RC OSC power setting: "Auto Power On”. Figure 46. Maximum Power On Delay vs. VDD, RC OSC = 2 MHz. Figure 47. Maximum Power On Delay vs. VDD, RC OSC = 25 kHz.

lines <30>, and <31>. See Figure 48. below for details of the frequencies for each of these two Connection Matrix Inputs. will be turned off. The PWR DOWN signal has the highest priority.

14.2 RC OSC Block Diagram

Figure 48. RC OSC Block Diagram

15.0 Additional Logic Functions

one inverter which can switch the polarity of any Connection Matrix signal.

15.1 INV_0 Gate

Figure 49. INV_0 Gate

000-0046121--111 Page 76 of 96 SLG46121

16.0 Power On Reset (POR)

The SLG46121 has a power-on reset (POR) macrocell t o ensure correct device initialization and operatio n of all macrocells in the device. The purpose of the POR circuit is to ha ve consistent behavior and predictable results when the VDD power is first ramping to the device, and also while the VDD is fa lling during power-down. To accomplish this goal, the POR drives a defined sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of the I/O pins. This application note is created to explain the whole process of POR operation and GreenPAK chip behavior during the time while it is powering up and powering down.

16.1 General Operation

The SLG46121 is guaranteed to be powered down and nonoperational when the VDD voltage (voltage on PIN1) is less than 0.6V, but not less than -0.6V. Another essential condition for the chip to be powered down is that no voltag e higher (see Note 1) than the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3V, applying a voltage higher than 0.3V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior. Note 1. There is a 0.6V margin due to forward drop voltage of the ESD protection diodes. To start the POR sequence in the SLG46121, the volt age applied on the VDD should be higher than the Po wer_ON threshold VDD voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power_ON threshold. After the POR sequ ence has started, the SLG46121 will have a typical period of time to go through all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after the POR sequence is complete. Note 2. The Power_ON threshold can vary by PVT, but typically it is 1.6 V. To power down the chip the VDD voltage should be lo wer than the operational and to guarantee that chip is powered down it should be less than 0.6 V. All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step in the POR sequence releases the I/O structures from the high impedance state, at which time the device is operational. The pin configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on. Note that VDD2 has no influence on POR sequence, al l internal macrocells are powered from VDD. It mean s, VDD2 can be switched on/off while VDD is on. If voltage on VDD2 appears after the POR sequence, pins 8, 9, 10, 12 become available when VDD2 reaches 0.6 V. For proper power up sequence, make sure VDD2 will not exceed VDD at any point during startup. For normal operation VDD should not be switched off while VDD2 is on, due to VDD2≤VDD,see section 5.0 Electrical Specifica - tions.

16.2 POR Sequence

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 50. environmental factors, such as: slew rate, VDD value, temperature and even will vary from chip to chip (process influence). Figure 50. POR sequence

16.3 Macrocells Output States During POR Sequence

states during the POR sequence ( Figure 51. describes the output signals states). last are output PINs that become active and determined by the input signals. Figure 51. Internal Macrocell States during POR sequence

000-0046121--111 Page 79 of 96 SLG46121

17.0 Appendix A - SLG46121 Register Definition

Address Signal Function Register Bit Definition reg<5:0> Matrix Out: PIN3 Digital Output Source reg<11:6> Matrix Out: PIN4 Digital Output Source reg<17:12> Matrix Out: PIN5 Digital Output Source reg<23:18> Matrix Out: PIN6 Digital Output Source reg<29:24> Matrix Out: Output Enable of PIN6 reg<35:30> Matrix Out: In0 of LUT2_0 or Clock Input of DFF0 reg<41:36> Matrix Out: In1 of LUT2_0 or Data Input o f DFF0 reg<47:42> Matrix Out: In0 of LUT2_1 or Clock Input of DFF1 reg<53:48> Matrix Out: In1 of LUT2_1 or Data Input o f DFF1 reg<59:54> Matrix Out: In0 of LUT2_2 or Clock Input of DFF2 reg<65:60> Matrix Out: In1 of LUT2_2 1 or Data Input of DFF2 reg<71:66> Matrix Out: In0 of LUT2_3 or Clock Input of DFF3 reg<77:72> Matrix Out: In1 of LUT2_3 1 or Data Input of DFF3 reg<83:78> Matrix Out: In0 of LUT2_4 reg<89:84> Matrix Out: In1 of LUT2_4 reg<95:90> Matrix Out: In0 of Inverter INV_0 reg<101:96> Matrix Out: PIN12 Digital Output Source reg<107:102> Matrix Out: In0 of LUT3_0 or Clock Inpu t of DFF4 reg<113:108> Matrix Out: In1 of LUT3_0 or Data Input of DFF4 reg<119:114> Matrix Out: In2 of LUT3_0 or Resetb Inp ut of DFF4 reg<125:120> Matrix Out: In0 of LUT3_1 or Clock Inpu t of DFF5 reg<131:126> Matrix Out: In1 of LUT3_1 or Data Input of DFF5 reg<137:132> Matrix Out: In2 of LUT3_1 or Resetb(Set b) of DFF5 reg<143:138> Matrix Out: In0 of LUT3_2 or Clock Inpu t of DFF6 reg<149:144> Matrix Out: In1 of LUT3_2 or Data Input of DFF6 reg<155:150> Matrix Out: In2 of LUT3_2 or Resetb Inp ut of DFF6 reg<161:156> Matrix Out: In0 of LUT3_3 or Clock Inpu t of DFF7 reg<167:162> Matrix Out: In1 of LUT3_3 or Data Input of DFF7 reg<173:168> Matrix Out: In2 of LUT3_3 or Resetb(Set b) of DFF7 reg<179:174> Matrix Out: In0 of LUT3_4 reg<185:180> Matrix Out: In1 of LUT3_4 reg<191:186> Matrix Out: In2 of LUT3_4 reg<197:192> Matrix Out: In0 of LUT3_5 reg<203:198> Matrix Out: In1 of LUT3_5 reg<209:204> Matrix Out: In2 of LUT3_5 reg<215:210> Matrix Out: In0 of LUT3_6 reg<221:216> Matrix Out: In1 of LUT3_6 reg<227:222> Matrix Out: In2 of LUT3_6 reg<233:228> Matrix Out: In0 of LUT3_7 reg<239:234> Matrix Out: In1 of LUT3_7 reg<245:240> Matrix Out: In2 of LUT3_7

000-0046121--111 Page 80 of 96 SLG46121 reg<251:246> Matrix Out: In0 of LUT3_8 or Input of P ipe delay reg<257:252> Matrix Out: In1 of LUT3_8 or Resetb of Pipe delay reg<263:258> Matrix Out: In2 of LUT3_8 or Clock of P ipe delay reg<269:264> Matrix Out: In0 of LUT4_0 or Input for delay2(couter2) external clock reg<275:270> Matrix Out: In1 of LUT4_0 or Input for delay2 da - ta(counter2 reset) reg<281:276> Matrix Out: In2 of LUT4_0 reg<287:282> Matrix Out: In3 of LUT4_0 reg<293:288> Matrix Out: In0 of LUT4_1 or Input for delay3(couter3) external clock reg<299:294> Matrix Out: In1 of LUT4_1 or Input for delay3 da - ta(counter3 reset) reg<305:300> Matrix Out: In2 of LUT4_1 reg<311:306> Matrix Out: In3 of LUT4_1 reg<317:312> Matrix Out: Input for delay0 data(counter0 external clock) reg<323:318> Matrix Out: Input for delay1(counter1) external clock reg<329:324> Matrix Out: Input for delay1 data(count er1 reset) reg<335:330> Matrix Out: Not used reg<341:336> Matrix Out: pdb(power down) for ACMP0 reg<347:342> Matrix Out: pdb(power down) for ACMP1 reg<353:348> Matrix Out: Input for programmable delay (deglitch filter input) reg<359:354> Matrix Out: Power down for osc (1: Powe r down) reg<365:360> Matrix Out: PIN8 Digital Output Source reg<371:366> Matrix Out: PIN9 Digital Output Source reg<377:372> Matrix Out: PIN10 Digital Output Source reg<383:378> Matrix Out: Output Enable of PIN10 reg<389:384> Reserved reg<395:390> Reserved LUT2_0 or DFF0 reg<399:396> LUT2_0 data or the following reg<396> DFF0 or Latch select 0: DFF function 1: Latch function reg<397> DFF0 output select 0: Q output 1: nQ output reg<398> DFF0 initial polarity select 0: Low 1: High LUT2_1 or DFF1 reg<403:400> LUT2_1 data or the following 0: DFF function 1: Latch function reg<400> DFF1 or Latch select 0: DFF function 1: Latch function reg<401> DFF1 output select 0: Q output 1: nQ output Register Bit Address Signal Function Register Bit Definition

000-0046121--111 Page 81 of 96 SLG46121 reg<402> DFF1 initial polarity select 0: Low 1: High LUT2_2 or DFF2 reg<407:404> LUT2_2 data or the following reg<404> DFF2 or Latch select 0: DFF function 1: Latch function reg<405> DFF2 output select 0: Q output 1: nQ output reg<406> DFF2 initial polarity select 0: Low 1: High LUT2_3 or DFF3 reg<411:408> LUT2_3 data or the following reg<408> DFF3 or Latch select 0: DFF function 1: Latch function reg<409> DFF3 output select 0: Q output 1: nQ output reg<410> DFF3 initial polarity select 0: Low 1: High LUT2_4 reg<415:412> LUT2_4 data reg<419:416> Reserved LUT2/DFF Select reg<420> LUT2_0 or DFF0 select 0: LUT2_0 1: DFF0 reg<421> LUT2_1 or DFF1 select 0: LUT2_1 1: DFF1 reg<422> LUT2_2 or DFF2 select 0: LUT2_2 1: DFF2 reg<423> LUT2_3 or DFF3 select 0: LUT2_3 1: DFF3 LUT3_0 or DFF4 reg<431:424> LUT3_0 data or the following reg<424> DFF4 or Latch select 0: DFF function 1: Latch function reg<425> DFF4 output select 0: Q output 1: nQ output reg<426> DFF4 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg<427> DFF4 initial polarity select 0: Low 1: High LUT3_1 or DFF5 reg<439:432> LUT3_1 data or the following reg<432> DFF5 or Latch select 0: DFF function 1: Latch function reg<433> DFF5 output select 0: Q output 1: nQ output reg<434> DFF5 rstb/setb select 0: resetb from matrix output 1: setb from matrix output Register Bit Address Signal Function Register Bit Definition

000-0046121--111 Page 82 of 96 SLG46121 reg<435> DFF5 initial polarity select 0: Low 1: High LUT3_2 or DFF6 reg<447:440> LUT3_2 data or the following reg<440> DFF6 or Latch select 0: DFF function 1: Latch function reg<441> DFF6 output select 0: Q output 1: nQ output reg<442> DFF6 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg<443> DFF6 initial polarity select 0: Low 1: High LUT3_3 or DFF7 reg<455:448> LUT3_3 data or the following reg<448> DFF7 or Latch select 0: DFF function 1: Latch function reg<449> DFF7 output select 0: Q output 1: nQ output reg<450> DFF7 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg<451> DFF7 initial polarity select 0: Low 1: High LUT3_4 reg<463:456> LUT3_4 data LUT3_5 reg<471:464> LUT3_5 data LUT3_6 reg<479:472> LUT3_6 data LUT3_7 reg<487:480> LUT3_7 data LUT3_8 or pip number select reg<495:488> reg<490:488>: OUT0 select data (pipe number) reg<493:491>: OUT1 select data (pipe number) reg<495:494>: Unused if Pipe Delay selected Unused LUT3/DFF Select reg<496> LUT3_0 or DFF4 select 0: LUT3_0 1: DFF4 reg<497> LUT3_1 or DFF5 select 0: LUT3_1 1: DFF5 reg<498> LUT3_2 or DFF6 select 0: LUT3_3 1: DFF6 reg<499> LUT3_3 or DFF7 select 0: LUT3_4 1: DFF7 reg<500> LUT3_8 or pipe delay output select 0: LUT3_8 1: pipe delay LUT4_0 or Counter/Delay2 reg<516:501> LUT4_0 data data or the following Register Bit Address Signal Function Register Bit Definition

000-0046121--111 Page 83 of 96 SLG46121 reg<501> Counter/delay2 mode selection 0: Delay Mode 1: Counter Mode reg<504:502> Counter/delay2 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter1 Overflow reg<512:505> Counter/delay2 Control Data 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg <514:513> Delay2 Mode Select or asynchronous co unter reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset for counter mode reg<517> LUT4_0 or Counter2 select 0: LUT4_0 1: Counter2 LUT4_1 or Counter/Delay3 reg<533:518> LUT4_1 data or the following reg<518> Counter/delay3 mode selection 0: Delay Mode 1: Counter Mode reg<521:519> Counter/delay3 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter2 Overflow reg<529:522> Counter/delay3 Control Data 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg<531:530> Delay3 Mode Select or asynchronous cou nter reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges reg<534> LUT4_1 or Counter3 select 0: LUT4_1 1: Counter3 RC Osc reg<535> Force RC oscillator on 0: Auto Power on 1: Force Power on reg<536> RC Oscillator frequency control 0: 25 kHz 1: 2 MHz reg<538:537> Osc clock pre-divider 00:div1 01:div2 10: div4 11: div8 Register Bit Address Signal Function Register Bit Definition

000-0046121--111 Page 84 of 96 SLG46121 reg<541:539> Internal Oscillator frequency divider c ontrol 0 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 reg<544:542> Internal Oscillator frequency divider c ontrol 1 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 reg<545> External Clock Source Select 0: Internal Oscillator 1: External Clock from Pin12 reg<546> Manufacturing test mode reg<547> Reserved Counter/Delay 0 reg<548> Counter/delay0 mode selection 0: Delay Mode 1: Counter Mode reg<551:549> Counter/delay0 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter3 Overflow reg<565:552> Counter0 Control Data/Delay0 Time Contr ol 1-16383: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg<567:566> Delay0 Mode Select or asynchronous coun ter reset 00: on both falling and rising edges 01: on falling edge only 10: on rising edge only 11: no delay on either falling or rising edges Counter/Delay 1 reg<568> Counter/delay1 mode selection 0: Delay Mode 1: Counter Mode reg<571:569> Counter/delay1 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter0 Overflow reg<579:572> Counter1 Control Data/Delay1 Time Contr ol 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 Register Bit Address Signal Function Register Bit Definition

000-0046121--111 Page 85 of 96 SLG46121 reg<581:580> Delay1 Mode Select or asynchronous coun ter reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset for counter mode reg<595:582> Reserved ACMP0 reg<600:596> ACMP0 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: EXT_VREF(PIN4) reg<602:601> ACMP0 hysteresis Enable 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) reg<604:603> ACMP0 positive Input divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X reg<605> ACMP0 low bandwidth (typ: Max.1 MHz) enable . 0: off 1: on reg<606> ACMP0 positive input source select PIN3 and VDD 0: PIN3 1: VDD ACMP1 reg<611:607> ACMP1 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: EXT_VREF(PIN4) reg<613:612> ACMP1 hysteresis Enable 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) Register Bit Address Signal Function Register Bit Definition

000-0046121--111 Page 86 of 96 SLG46121 reg<615:614> ACMP1 positive Input divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X reg<616> ACMP1 100uA current source option 0: disable 1: enable reg<617> ACMP1 low bandwidth (typ: Max.1Mhz) enable. 0: off 1: on reg<618> ACMP1 positive input source select PIN6 and PIN3 0: PIN3 1: PIN6 reg<622:619> Reserved Reserved PIN 2 reg<624:623> PIN2 mode control 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved reg<626:625 > PIN2 pull down resistor value selectio n 00: floating 01: 10K 10: 100K 11: 1M PIN 3 reg<629:627 > PIN3 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Analog Input 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input & Open Drain reg<631:630 > PIN3 pull up/down resistor value selec tion 00: floating 01: 10K 10: 100K 11: 1M reg<632> PIN3 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<633> PIN3 driver strength selection 0: 1X 1: 2X PIN 4 reg<636:634> PIN4 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Analog Input 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input & Open Drain reg<638:637> PIN4 pull up/down resistor value select ion 00: floating 01: 10K 10: 100K 11: 1M reg<639> PIN4 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable Register Bit Address Signal Function Register Bit Definition

000-0046121--111 Page 87 of 96 SLG46121 reg<640> PIN4 driver strength selection 0: 1X 1: 2X PIN 5 reg<643:641> PIN5 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Open Drain NMOS reg<645:644> PIN5 pull up/down resistor value select ion 00: floating 01: 10K 10: 100K 11: 1M reg<646> PIN5 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<647> PIN5 driver strength selection 0: 1X 1: 2X PIN 6 reg<649:648> PIN6 mode control (sig_pin6_oe =0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Analog Input / Output reg<651:650> PIN6 mode control (sig_pin6_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11:Open Drain NMOS 2X reg<653:652> PIN6 pull up/down resistor value select ion 00: floating 01: 10K 10: 100K 11: 1M reg<654> PIN6 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable PIN8 reg<657:655> PIN8 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Open Drain NMOS reg<659:658> PIN8 pull up/down resistor value select ion 00: floating 01: 10K 10: 100K 11: 1M reg<660> PIN8 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<661> PIN8 driver strength selection 0: 1X 1: 2X Register Bit Address Signal Function Register Bit Definition

000-0046121--111 Page 88 of 96 SLG46121 PIN 9 reg<664:662> PIN9 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Open Drain NMOS reg<666:665> PIN9 pull down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M reg<667> PIN9 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<668> PIN9 driver strength selection 0: 1X 1: 2X PIN 10 reg<670:669> PIN10 mode control (sig_pin10_oe =0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Analog Input / Output reg<672:671> PIN10 mode control (sig_pin10_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11:Open Drain NMOS 2X reg<674:673> PIN10 pull up/down resistor value selec tion 00: floating 01: 10K 10: 100K 11: 1M reg<675> PIN10 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable Reserved reg<678:676> Reserved reg<680:679> Reserved reg<681> Reserved reg<682> Reserved PIN 12 reg<685:683> PIN12 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Open drain reg<687:686> PIN12 pull up/down resistor value selec tion 00: floating 01: 10k 10: 100K 11: 1M reg<688> PIN12 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable Register Bit Address Signal Function Register Bit Definition

000-0046121--111 Page 89 of 96 SLG46121 reg<689> PIN12 driver strength selection 0: 1X 1: 2X reg<690> Pipe delay OUT1 polarity select bit 0: Non-inverted 1: Inverted reg<698:691> 8-bit pattern id reg<699> filter0 output polarity select 0: Non-inverting 1: Inverting reg<701:700> Reserved Reserved reg<702> GPIO quick charge enable 0: Disable 1: Enable reg<706:703> Reserved Reserved reg<707> Force bandgap on 0: Auto-mode 1: Enable reg<708> VREF1 Output Active Buffer Control 0: Disabled 1: Enabled reg<711:709> VREF1 Output Source Select 000: ACMP0 reference voltage 001: ACMP1 reference voltage 100: VDD/2 101: VDD/3 110: VDD/4 reg<712> NVM data read disable 0: Disable (read enable) 1: Enable (read disable) reg<713> NVM power down (or NVM data programming dis able) 0: None (or programming enable) 1: Power Down (or programming disable) reg<714> Power Divider Power 0: Power down 1: Power On reg<715> POR Auto Power detect 0: Enable 1: Disable reg<716> Charge pump for analog macrocell enable (when VDD <=2.7V turn on) 0: Disable (automatic on/off control) 1: Enable (always on) reg<717> VDD bypass enable 0: Regulator auto on 1: Regulator off (VDD bypass) reg<718> PIN2 edge detect mode 0: rising edge 1: falling edge reg<719> Bypass the pin2 0: PIN2 edge active 1: PIN2 high active reg<720> PIN2 reset enable 0: Disable 1: Enable reg<721> Reserved Reserved reg<727:722> Reserved Reserved reg<735:728> Reserved Reserved reg<741:736> Reserved Reserved reg<743:742> Delay value select for programmable delay & edge de- tector (VDD = 3.3V, typical condition) 00: 163 ns 01: 305 ns 10: 446 ns 11: 588 ns reg<745:744> Select the edge mode of programmable delay & edge detector 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay Register Bit Address Signal Function Register Bit Definition

000-0046121--111 Page 90 of 96 SLG46121 reg<746> programmable delay or filter output select 0: programmable delay output 1: filter output reg<751:747> Reserved Reserved reg<757:752> Reserved Reserved reg<758> Reserved Reserved reg<759> Reserved Reserved reg<767:760> Reserved Reserved Register Bit Address Signal Function Register Bit Definition

000-0046121--111 Page 91 of 96 SLG46121

18.0 Package Top Marking System Definition

18.1 Before February 1, 2021

18.2 After February 1, 2021

P P A Part Code + Assembly Code Pin 1 Identifier WWR Date Code + Revision Code NN Serial Number Code P P P Part Code Pin 1 Identifier WWR Date Code + Revision Code NN Serial Number Code

000-0046121--111 Page 92 of 96 SLG46121

19.0 Package Drawing and Dimensions

12 Lead STQFN FCA Package 1.6 x 1.6 mm

000-0046121--111 Page 93 of 96 SLG46121

20.0 Tape and Reel Specifications

20.1 Carrier Tape Drawing and Dimensions

# of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 12L FCA 0.4P Green 10 1.6x1.6x0.55 3000 3000 178/60 100 400 100 400 8 4 Package Type Pocket BTM Length [mm] Pocket BTM Width [mm] Pocket Depth [mm] Index Hole Pitch [mm] Pocket Pitch [mm] Index Hole Diameter [mm] Index Hole to Tape Edge [mm] Index Hole to Pocket Center [mm] Tape Width [mm] A0 B0 K0 P0 P1 D0 E F W STQFN 12L FCA 0.4P Green

000-0046121--111 Page 94 of 96 SLG46121

21.0 Recommended Land Pattern

22.0 Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 1.408 mm 3 (nominal). More information can be found at www.jedec.org. Units: µm

000-0046121--111 Page 95 of 96 SLG46121

23.0 Revision History

3/10/2023 1.11 Added notes to section Ordering Inform ation 3/4/2022 1.10 Updated Pull Up/Down Resistance in Electrical Characteristics Renesas rebranding Updated tables CNT/DLY Register Settings Corrected registers [512:505], [529:522], [565:552], [579:572] in Appendix A - SLG46121 Register Definition 2/2/2021 1.09 Updated section Package Top Marking System Definition Added note for CNTs Corrected registers [579:569], [565:549], [529:519], [512:502] 10/29/2019 1.08 Updated last page with disclaimer and contacts Added pre front page Fixed typos Added additional information about V DD2 to IO Pins section 2/27/2018 1.07 Fixed typos 10/11/2017 1.06 Updated Electrical Spec Fixed typos Updated POR sequence 5/7/2017 1.05 Fixed typos Updated Silego Website & Support Updated Section Programmable Delay / Edge Detector Updated Electrical Spec 5/30/2016 1.04 Updated Programmable Delay information 2/1/2016 1.03 Updated section Power On Reset 1/29/2016 1.02 Updated Silego Website & Support Fixed typos 12/29/2015 1.01 Updated Electrical Spec 12/9/2015 1.00 Production Release 12/7/2015 0.52 Updated front page 11/19/2015 0.51 Added VDD2 information to POR section Updated pin description Updated Absolute maximum conditions 11/04/2015 0.50 Preliminary Release 10/28/2015 0.15 Updated Absolute maximum conditions 10/20/2015 0.14 Fixed typos 9/16/2015 0.13 Added VDD2 tables Added Vhys, Rpup, Rpdwn, PONthr, POFFthr Added El. Spec table for VDD = 1.8 V 8/25/2015 0.12 Updated references to VDD and VDD2 Fixed typos Updated Front Page, Sections 1, 5, 6, 7, 8 , 9, 10, 12. 7/21/2015 0.11 Updated Electrical Characteristics 6/24/2015 0.1 Initial release

000-0046121--111 Page 96 of 96 SLG46121 RoHS Compliance Renesas Electronics Corporation’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous sub stances in electrical and electronic equipment. RoH S certificates from our suppliers are available on request.

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) © 2021 Renesas Electronics Corporation. All rights reserved.

Selected Specification

Renesas Technology Corp SLG46121VTR overview.

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Summary

GreenPAK Dual Supply Programmable Mixed-signal Matrix March 10, 2023

Description

GreenPAK Dual Supply Programmable Mixed-signal Matrix March 10, 2023

Source title SLG46121VTR Datasheet(PDF) - Renesas Technology Corp

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