SLG46120V

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Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 92

Technical content

Features

Logic & Mixed Signal Circuits
Highly Versatile Macrocells
1.8V (±5%) to 5V (±10%) Supply
Operating Temperature Range: -40°C to 85°C
RoHS Compliant / Halogen-Free
Pb-Free 12-pin STQFN: 1.6 x 1.6 x 0.55 mm, 0.4 mm pitch

Applications

Personal Computers and Servers
PC Peripherals
Consumer Electronics
Data Communications Equipment
Handheld and Portable Electronics Pin Configuration GND GPIO GPIO GPIO GPIO GPIO 4 7 GPI VDD 1 STQFN-12 (Top View) GPIO GPIO 5 6 GPIO GPIO 1112 3-bit LUT3_1 or DFF5 Pin 1 VDD Pin 2 GPI Pin 3 GPIO Pin 4 GPIO Pin 12 GPIO Pin 11 GPIO Pin 5 GPIO Pin 6 GPIO Pin 8 GPIO Pin 7 GND Pin 10 GPIO Pin 9 GPIO ACMP0 ACMP1 Look Up Tables (LUTs) Counters/Delay Generators CNT0 CNT1 2-bit LUT2_4 3-bit LUT3_5 3-bit LUT3_4 Combination Function Macrocells 2-bit LUT2_0 or DFF0 2-bit LUT2_1 or DFF1 3-bit LUT3_0 or DFF4 2bit LUT2_3 or DFF3 2-bit LUT2_2 or DFF2 3-bit LUT3_8 or Pipe Delay 3-bit LUT3_2 or DFF6 3-bit LUT3_3 or DFF7 4-bit LUT4_1 or CNT3 4bit LUT4_0 or CNT2 3-bit LUT2_6 3-bit LUT3_7 Vref RC Oscillator FILTER_0/Prog. Delay Additional Combination Functions PORBandgap

000-0046120-108 Page 1 of 91 SLG46120

1.0 Overview

The SLG46120 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macrocells of the SLG46120. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The macrocells in the device include the following:

Two Analog Comparators (ACMP)
Voltage References (Vref)
Five Combinatorial Look Up Tables (LUTs)
One 2-bit LUTs
Four 3-bit LUTs
Twelve Combination Function Macrocell
Four Selectable DFF/Latch or 2-bit LUTs
Four Selectable DFF/Latch or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
Pipe Delay – 8 stage / 2 output, one 1 stage fixed output
Two Selectable Counter/Delay or 4-bit LUT
One Programmable Delay / Deglitch Filter
Two Counter / Delay Generators (CNT/DLY)
One 8-bit counter/delay
One 14-bit counter/delay with external clock/reset
Eight D Flip-Flop / Latches (DFF) (Part of Combination Functio n Macrocell)
Pipe Delay – 8 stage/2 output ( Part of Combination Function Macrocell)
One Bandgap
RC Oscillator (RC OSC)
Power On Reset (POR)

000-0046120-108 Page 2 of 91 SLG46120

2.0 Pin Description

2.1 Functional and Programming Pin Description

Pin # Pin Name Function Programming Function

1 VDD Power Supply Power Supply

2 GPI General Purpose Input V PP (Programming Voltage)

3 GPIO General Purpose I/O or Anal og Comparator 0 (+) Programming ID Pin

4 GPIO General Purpose I/O or Analog Comparator 0 (-) N/A

5 GPIO General Purpose I/O N/A

6 GPIO General Purpose I/O or Anal og Comparator 1 (+) with OE N/A

7 GND Ground N/A

8 GPIO General Purpose I/O Programming Mode Control

9 GPIO General Purpose I/O Programming SDIO Pin

10 GPIO General Purpose I/O with OE and Vref output Programming S RDWB Pin

11 GPIO General Purpose I/O N/A

12 GPIO General Purpose I/O or Ex ternal Clock Input Programming SC L Pin

3.0 User Programmability

long as it remains powered and can be re-written as needed to facilitate rapid design changes. Once the design is finalized, the design file can be forwarded to Silego to integrate into the production process. Figure 1. Steps to create a custom Silego GreenPAK device

000-0046120-108 Page 4 of 91 SLG46120

4.0 Ordering Information

SLG46120VTR 12-pin STQFN - Tape and Reel (3k units)

000-0046120-108 Page 5 of 91 SLG46120

5.0 Electrical Specifications

5.1 Absolute Maximum Conditions

5.2 Electrical Characteristics (1.8V ±5% VDD) Parameter Min. Max. Unit Supply voltage on VDD relative to GND -0.5 7 V DC Input voltage G ND - 0.5 VDD + 0.5 V Maximum Average or DC Current (Through pin) Push-Pull 1x -- 12 mA Push-Pull 2x -- 17 OD 1x -- 18 OD 2x -- 28 Current at Input Pin -1.0 1.0 mA Storage Temperature Range -65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1000 -- V Moisture Sensitivity Level 1 Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 1.71 1.80 1.89 V IQ Quiescent Current Static Inputs and Outputs (when ACMP, Vref and RC OSC are powered down and non-operational) -- 0.5 -- A TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VAIR Analog Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.1 V VIH HIGH-Level Input Voltage Logic Input 1.100 -- V DD V Logic Input with Schmitt Trigger 1.270 -- V DD V Low-Level Logic Input 0.980 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 0.690 V Logic Input with Schmitt Trigger -- -- 0.440 V Low-Level Logic Input -- -- 0.520 V IIH HIGH-Level Input Current Logic Input Pins; V IN = 1.8 V -1.0 -- 1.0 A IIL LOW-Level Input Current Logic Input Pins; V IN = 0 V -1.0 -- 1.0 A VOH HIGH-Level Output Voltage Push-Pull 1X, Open Drain PMOS 1X, IOH = 100 A 1.680 1.790 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 100 A 1.700 1.800 -- V

000-0046120-108 Page 6 of 91 SLG46120 VOL LOW-Level Output Voltage Push-Pull 1X, IOL= 100 A -- 0.020 0.030 V Push-Pull 2X, IOL= 100 A -- 0.010 0.020 V Open Drain NMOS 1X, IOL= 100 A -- 0.010 0.020 V Open Drain NMOS 2X, IOL= 100 A -- 0.010 0.010 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, VOH = VDD - 0.2 1.000 1.390 -- mA Push-Pull 2X, Open Drain PMOS 2X, VOH = VDD - 0.2 2.100 2.680 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, VOL = 0.15 V 0.760 1.340 -- mA Push-Pull 2X, VOL = 0.15 V 1.520 2.660 -- mA Open Drain NMOS 1X, VOL = 0.15 V 1.530 2.670 -- mA Open Drain NMOS 2X, VOL = 0.15 V 3.060 5.136 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) TSU Startup Time from VDD rising past 1.35 V -- 0.31 -- ms PONTHR Power On Threshold V DD Level Required to Start Up the Chip 1.180 1.353 1.516 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 0.730 0.914 1.103 V Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10, 11 and 12 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046120-108 Page 7 of 91 SLG46120 5.3 Electrical Characteristics (3.3V ±10% VDD) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3.0 3.3 3.6 V IQ Quiescent Current Static Inputs and Outputs (when ACMP, Vref and RC OSC are powered down and non-operational) -- 0.75 -- A TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VAIR Analog Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 1.780 -- V DD V Logic Input with Schmitt Trigger 2.130 -- V DD V Low-Level Logic Input 1.130 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 1.210 V Logic Input with Schmitt Trigger -- -- 0.950 V Low-Level Logic Input -- -- 0.690 V IIH HIGH-Level Input Current Logic Input Pins; V IN = 3.3 V -1.0 -- 1.0 A IIL LOW-Level Input Current Logic Input Pins; V IN = 0 V -1.0 -- 1.0 A VOH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, IOH = 3 mA 2.720 3.090 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 3 mA 2.850 3.190 -- V VOL LOW-Level Output Voltage Push-Pull 1X, IOL= 3 mA -- 0.180 0.280 V Push-Pull 2X, IOL= 3 mA -- 0.090 0.130 V Open Drain NMOS 1X, IOL= 3 mA -- 0.090 0.130 V Open Drain NMOS 2X, IOL= 3 mA -- 0.050 0.070 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, VOH = 2.4 V 6.010 10.150 -- mA Push-Pull 2X, Open Drain PMOS 2X, VOH = 2.4 V 11.460 19.610 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, VOL = 0.4 V 4.060 6.440 -- mA Push-Pull 2X, VOL = 0.4 V 8.130 12.360 -- mA Open Drain NMOS 1X, VOL = 0.4 V 8.130 12.410 -- mA Open Drain NMOS 2X, VOL = 0.4 V 16.260 22.900 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2)

000-0046120-108 Page 8 of 91 SLG46120

5.4 Electrical Characteristics (5V ±10% VDD)

TSU Startup Time from VDD rising past 1.35 V -- 0.31 -- ms PONTHR Power On Threshold V DD Level Required to Start Up the Chip 1.180 1.353 1.516 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 0.730 0.914 1.103 V Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10, 11 and 12 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V IQ Quiescent Current Static Inputs and Outputs (when ACMP, Vref and RC OSC are powered down and non-operational) -- 1.0 -- A TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VAIR Analog Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 2.640 -- V DD V Logic Input with Schmitt Trigger 3.160 -- V DD V Low-Level Logic Input 1.230 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 1.840 V Logic Input with Schmitt Trigger -- -- 1.510 V Low-Level Logic Input -- -- 0.780 V IIH HIGH-Level Input Current Logic Input Pins; V IN = 5 V -1.0 -- 1.0 A IIL LOW-Level Input Current Logic Input Pins; V IN = 0 V -1.0 -- 1.0 A VOH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, IOH = 5 mA 4.170 4.740 -- V Push-Pull 2X, Open Drain PMOS 2X, IOH = 5 mA 4.320 4.860 -- V VOL LOW-Level Output Voltage Push-Pull 1X, IOL= 5 mA -- 0.230 0.330 V Push-Pull 2X, IOL= 5 mA -- 0.120 0.160 V Open Drain NMOS 1X, IOL= 5 mA -- 0.120 0.160 V Open Drain NMOS 2X, IOL= 5 mA -- 0.700 0.090 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, VOH = 2.4 V 21.980 29.001 0 -- mA Push-Pull 2X, Open Drain PMOS 2X, VOH = 2.4 V 41.886 55.990 -- mA Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046120-108 Page 9 of 91 SLG46120 IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, VOL = 0.4 V 6.010 9.730 -- mA Push-Pull 2X, VOL = 0.4 V 11.590 19.460 -- mA Open Drain NMOS 1X, VOL = 0.4 V 11.760 19.460 -- mA Open Drain NMOS 2X, VOL = 0.4 V 19.120 35.952 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) TSU Startup Time from VDD rising past 1.35 V -- 0.31 -- ms PONTHR Power On Threshold V DD Level Required to Start Up the Chip 1.180 1.353 1.516 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 0.730 0.914 1.103 V Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10, 11 and 12 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

5.5 IDD Estimator

5.6 Timing Estimator

Table 1. Typical Current estimated for each macrocell. Table 2. Typical Delay estimated for each macrocell.

5.7 Typical Counter/Delay Offset Measurements

5.8 Expected Delays and Widths

Table 3. Typical Counter/Delay Offset Measurements. Table 4. Expected Delays and Widths for Programmable Delay (typical).

5.9 Typical Pulse Width Performance

Table 5. Typical Pulse Width Performance.

000-0046120-108 Page 13 of 91 SLG46120

6.0 Summary of Macrocell Function

6.1 I/O Pins

Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
Open Drain NMOS and O pen Drain PMOS Outputs
Push Pull Outputs
Analog I/O
10 k /100 k/1 Mpull-up/pull-down resistors

6.2 Connection Matrix

Digital matrix for circuit co nnections based on user design

6.3 Analog Comparators (2 total)

Selectable hysteresis 0 mV/25 m V/50 mV/200 mV and selectable gain 1x/0.5x/0.33x/0.25x

6.4 Voltage Reference

Used for references on Analog Comparators
Can also be driven to external pins

6.5 Combinational Logic Look Up Tables (LUTs – 5 total)

One 2-bit Lookup Tables
Four 3-bit Lookup Tables

6.6 Combination Function Macrocells (12 total)

Four Selectable DFF/Latches or 2-bit LUTs
Four Selectable DFF/Latches or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
Two Selectable CNT/DLYs or 4-bit LUTs
One Programmable Delay or Deglitch Filter

6.7 Delays/Counters (2 total)

One 8-bit delay/counter with ex ternal clock/reset: Range 1-255 clock cycles
One 14-bit delay/count er with external clock/reset: Range 1-16383 clock cycles

6.8 Pipe Delay (Part of Combination Function Macrocell)

8 stage / 2 output
Two 1-8 stage sel ectable outputs
One 1 stage fixed output

6.9 Additional Logic Functions (Part of Combination Function Macrocell)

One Deglitch filter macrocell
One Programmable Delay
163 ns / 305 ns / 446 ns / 588 ns @ 3.3 V
Includes Edge Detection function

000-0046120-108 Page 14 of 91 SLG46120

6.10 RC Oscillator

25 kHz and 2 MHz s electable frequency
First Stage Clock pre=divider (4) : OSC/1, OSC/2, OSC/4, and OSC/8
Second stage divider control wit h two outputs, OUT0 and OUT1 (8): selectable (OSC/1, OSC/2, OSC/3, OSC/4, OSC/8, OSC/12, OSC/24, or OSC/64)

6.11 Power On Reset (POR)

000-0046120-108 Page 15 of 91 SLG46120

7.0 I/O Pins

The SLG46120 has a total of 10 mu lti-function I/O pins which ca n function as either a user defined Input or Output, as well as serving as a special function (s uch as outputting the voltage r eference), or serving as a signal for programming of the on-chi p Non Volatile Memory (NVM). Normal Mode pin definitions are as follows:

Pin 1: V DD Power Supply
Pin 2: General Purpose Input
Pin 3: General Purpose I/O or Analog Comparator 0 (+)
Pin 4: General Purpose I/O or Analog Comparator 0 (-)
Pin 5: General Purpose I/O
Pin 6: General Purpose I/O or Analog Comparator 1 (+) with OE
Pin 7: Ground
Pin 8: General Purpose I/O
Pin 9: General Purpose I/O
Pin 10: General Purpose I/O with OE and Vref Output
Pin 11: General Purpose I/O
Pin 12: General Purpose I /O or External Clock Input Programming Mode pin definitions are as follows:
Pin 1: V DD Power Supply
Pin 2: V PP Programming Voltage
Pin 3: Programming ID Pin
Pin 7: Ground
Pin 8: Programming Mode Control
Pin 9: Programming SDIO Pin
Pin 10: Programming SRDWB Pin
Pin 12: Programming SCL Pin Of the 10 user defined I/O pins on the SLG46120, all but one of the pins (Pin 2) can serve as both digital input and digital output. Pin 2 can only serve as a digital input pin.

7.1 Input Modes

Each I/O pin can be configured as a digital input pin with/with out buffered Schmitt Trigger, or can also be configured as a lo w voltage digital input. Pins 3, 4, and 6 can also be configured to serve as analog inputs to the on-chip comparators.

7.2 Output Modes

Pins 3, 4, 5, 6, 8, 9, 10, 11, and 12 can all be configured as digital output pins.

7.3 Pull Up/Down Resistors

All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors are 10 k, 100 k and 1 M. In the case of Pin 2, the resistors are fixed to a pull-down configuration. In the case of all other I/O pins, the internal resistors can be configured as either pull-up or pull-downs.

7.4 I/O Register Settings

7.4.1 PIN 2 Register Settings

7.4.2 PIN 3 Register Settings

Table 6. PIN 2 Register Settings Table 7. PIN 3 Register Settings

7.4.3 PIN 4 Register Settings

7.4.4 PIN 5 Register Settings

Table 8. PIN 4 Register Settings Table 9. PIN 5 Register Settings

7.4.5 PIN 6 Register Settings

7.5 PIN 8 Register Settings

Table 10. PIN 6 Register Settings Table 11. PIN 8 Register Settings

7.5.1 PIN 9 Register Settings

7.6 PIN 10 Register Settings

7.7 PIN 11 Register Settings

Table 12. PIN 9 Register Settings Table 13. PIN 10 Register Settings Table 14. PIN 11 Register Settings

7.8 PIN 12 Register Settings

Table 15. PIN 12 Register Settings

7.9 GPI IO Structure

7.9.1 GPI IO Structure (for Pin 2)

Figure 2. PIN 2 GPI IO Structure Diagram

7.10 Matrix OE IO Structure

7.10.1 Matrix OE IO Structure (for Pin 6, 10)

Figure 3. Matrix OE IO Structure Diagram

7.11 Register OE IO Structure

7.11.1 Register OE IO Structure (for Pins 3, 4, 5, 8, 9, 11, 12)

Figure 4. Register OE IO Structure Diagram

8.0 Connection Matrix

macrocell uses a 6-bit register to select one of these 40 input lines. For a complete list of the SLG46120’s register table, see Section 16.0 Appendix A - SLG46120 Register Definition. Figure 5. Connection Matrix Figure 6. Connection Matrix Example

8.1 Matrix Input Table

Table 16. Matrix Input Table

0 V S S 00 0000

6 LUT2_0 output (DFF/LATCH_0 output) 0 0 0 1 1 0

7 LUT2_1 output (DFF/LATCH_1 output) 0 0 0 1 1 1

8 LUT2_2 output (DFF/LATCH_2 output) 0 0 1 0 0 0

9 LUT2_3 output (DFF/LATCH_3 output) 0 0 1 0 0 1

10 LUT2_4 output 0 0 1 0 1 0

12 LUT3_0 output (DFF/LATCH_4 out put with resetb or seb) 0 0 1 1 0 0

13 LUT3_1 output (DFF/LATCH_5 out put with resetb or seb) 0 0 1 1 0 1

14 LUT3_2 output (DFF/LATCH_6 out put with resetb or seb) 0 0 1 1 1 0

15 LUT3_3 output (DFF/LATCH_7 out put with resetb or seb) 0 0 1 1 1 1

16 LUT3_4 output 0 1 0 0 0 0

17 LUT3_5 output 0 1 0 0 0 1

18 LUT3_6 output 0 1 0 0 1 0

19 LUT3_7 output 0 1 0 0 1 1

20 LUT3_8 output (pipe delay output0) 0 1 0 1 0 0

21 LUT4_0 output (CNT_DLY3 output (8 bit w/ ext CK,reset)) 0 1 0 1 0 1

22 LUT4_1 output (CNT_DLY4 output (8 bit w/ ext CK,reset)) 0 1 0 1 1 0

23 CNT_DLY0(14bit) output 0 1 0 1 1 1

24 CNT_DLY1 output (8 bit w/ ext CK,reset) 0 1 1 0 0 0

25 Edge detector output from CNT_DLY4 0 1 1 0 0 1

26 ACMP_0 output 0 1 1 0 1 0

27 ACMP_1 output 0 1 1 0 1 1

29 Programmable delay with edge detector output (Deglitch filter out-

32 Bandgap OK signal 1 0 0 0 0 0

33 Resetb_core as matrix input 1 0 0 0 0 1

38 Pin12 digital Input 1 0 0 1 1 0

8.2 Matrix Output Table

Table 17. Matrix Output Table

9.0 Combinatorial Logic

Combinatorial logic is supported via five Lookup Tables (LUTs) within the SLG46120. There is one 2-bit LUT and four 3-bit LUTs. 10.0 Combination Function Macrocells. devices (AND, NAND, OR, NOR, XOR, XNOR). created within each of the two 2-bit LUT logic cells. Figure 7. 2-bit LUT4 Table 19. 2-bit LUT Standard Digital Functions. Table 18. 2-bit LUT4 Truth Table.

Figure 8. 3-bit LUTs Table 20. 3-bit LUT4 Truth Table. Table 21. 3-bit LUT5 Truth Table. Table 22. 3-bit LUT6 Truth Table. Table 23. 3-bit LUT7 Truth Table.

created within each of the two 3-bit LUT logic cells. Table 24. 3-bit LUT Standard Digital Functions.

000-0046120-108 Page 33 of 91 SLG46120

10.0 Combination Function Macrocells

The SLG46120 has twelve combination function macrocells that ca n serve more than one logic or timing function. In elven of these cases, they can serve as a Look Up Table (LUT), or as ano ther logic or timing function. In the last case, it can serve a s either a programmable delay or deglitch filter. See the list below for the functions that can be implemented in these macrocells.

Four macrocells that can serve as either 2-bit LUTs or as D Fl ip Flops
Four macrocells that can serve as either 3-bit LUTs or as D Fl ip Flops
One macrocell that can serve as either 3-bit LUT or as Pipe Delay
Two macrocells that can serve as either 4-bit LUTs or as 8-Bit Counter / Delays
One macrocell that can serve as either a Programmable Delay or as a Deglitch Filter Inputs/Outputs for the eleven combination function macrocells a re configured from the connection matrix with specific logic functions being defined by the state of NVM bits. When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR). When used as a D Flip Flop / Latch, the source and destination of the inputs and outputs for the DFF/Latches are configured from the connection matrix. All DFF/Latch macrocells have user selection for initial state, and all have the option to connect both the Q and Q Bar outputs to the connection matrix. The macrocells DF F2, DFF3 have an additional input from the matrix that can serve as a nSet or nReset function to the macrocell. The operation of the D Flip-Flop and Latch will follow the functional descriptions below: DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change Latch: if CLK = 0, then Q = D 10.1 2-Bit LUT or D Flip Flop Macrocells There are four macrocells that can serve as either 2-bit LUTs or as D Flip Flops. When used to implement LUT functions, the 2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the connection matrix. When used to implement D Flip Flop function, the two input signals from the connection matrix go to the data (d) and clock (clk) inputs for the Flip Flop, with the output going back to the connection matrix.

Table 25. 2-bit LUT0 Truth Table. Table 26. 2-bit LUT1 Truth Table. Table 27. 2-bit LUT3 Truth Table. Table 28. 2-bit LUT4 Truth Table.

Table 29. DFF0 Register Settings Table 30. DFF1 Register Settings Table 31. DFF2 Register Settings

Table 32. DFF3 Register Settings

Table 33. 3-bit LUT0 Truth Table. Table 34. 3-bit LUT1 Truth Table. Table 35. 3-bit LUT2 Truth Table. Table 36. 3-bit LUT3 Truth Table.

Table 37. DFF4 Register Settings Table 38. DFF5 Register Settings Table 39. DFF6 Register Settings

Table 40. DFF7 Register Settings

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay. output, which goes back into the connection matrix. When used as an 8-stage pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK) and Reset (nRESET). options for 1 to 8 stages of delay. be the total time delay of the Pipe Delay logic cell. Figure 17. 3-bit LUT8 or Pipe Delay

8 Flip-FlopsIN

Table 42. Pipe Delay Register Settings Table 41. 3-bit LUT8 Truth Table.

Figure 18. 4-bit LUT0 or CNT/DLY2

Figure 19. 4-bit LUT1 or CNT/DLY3

Table 45. 4-bit LUT Standard Digital Functions. Table 43. 4-bit LUT0 Truth Table. Table 44. 4-bit LUT1 Truth Table.

Table 46. CNT/DLY2 Register Settings Table 47. CNT/DLY3 Register Settings

10.5 Programmable Delay / Edge Detector

period. See the timing diagrams below for further information. Note: The input signal must be longer than the delay, otherwise it will be filtered out.

10.6 Programmable Delay Timing Diagram - Edge Detector Output

Figure 20. Programmable Delay Figure 21. Edge Detector Output

Note: For delays and widths refer to Table 4. Figure 22. Delayed Edge Detector Output

10.6.1 Programmable Delay Register Settings

Table 48. Programmable Delay Register Settings

10.7 Deglitch Filter

Figure 23. Deglitch Filter

11.0 Analog Comparators (ACMP)

a digital signal coming from the Connection Matrix. When ACMP is powered down, output is low. either created from an internal VREF or provided by way of the external sources. also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV or 200 mV. During powerup, the ACMP output will remain low, and then become valid 110 µs (max) after POR signal goes high, see Figure 24. Note: Applies to first time power ON. Note: Regulator and Charge Pump set to automatic ON/OFF. use Vref selection VDD/4 and VDD/3 to maintain this input range. Figure 24. Maximum Power On Delay vs. VDD. Table 49. Gain Divider Input Resistance (typ). Table 50. Gain Divider Accuracy.

reference/source. Internal Vref accuracy is optimized near 1000 mV selection. Note: Power supply control options have influence on the ACMP operation. Force BandGap option is set as Disabled).

Hysteresis: Input signal hyster esis options are Disable, 25 mV, 50 mV, 200 mV.
Low Bandwidth: Enable, Disable;
IN+ Gain: 1X, 0.5X, 0.33X, 0.25X;
IN+ source:
ACMP0 IN+ options are PIN 3, VDD;
ACMP1 IN+ options are PIN 6, ACMP0 IN+;
I N - s o u r c e :
ACMP0 IN- options are 24 internal reference sources (50 mV – 1200 mV) and VDD/3, VDD/4, PIN 4;
PWR UP=0 – ACMP is powered down; PWR UP=1 – ACMP is powered up. All ACMPs can have a common negative input. This can be achieved by configuring ACMP0 PIN 4 analog I/O connection.

11.1 ACMP0 Block Diagram

Figure 25. ACMP0 Block Diagram

11.2 ACMP0 Register Settings

Table 51. ACMP0 Register Settings

11.3 ACMP1 Block Diagram

Figure 26. ACMP1 Block Diagram

11.4 ACMP1 Register Settings

Table 52. ACMP1 Register Settings

11.5 Typical Performance Characteristics

Note: when VDD < 1.8V voltage reference should not exceed 1100 mV. Figure 27. Typical Input Voltage Offset vs. Voltage Reference at room temperature, LBW Mode – Disable, Vhys=0 mV, VDD=(1.7 – 5.5) V. Figure 28. Typical Input Threshold Variation (including Vref variation, ACMP offset) vs. Voltage reference at room temperature, LBW Mode – Disable, Vhys=0 mV.

11.6 Timing Characteristics

Figure 33. Maximum Propagation Delay Low-to-High Figure 34. Maximum Propagation Delay Low-to-High Figure 35. Maximum Propagation Delay High-to-Low Figure 36. Maximum Propagation Delay High-to-Low

12.0 Counters/Delay Generators (CNT/DLY)

of the previous (N-1) CNT/DLY macrocell, to implement longer count / delay circuits. Input (Delay_In/Reset_In), and one for an external counter/clock source. delays, For more information please see Section 10.4 4-Bit LUT or 8- Bit Counter / Delay Macrocells. Figure 41. CNT/DLY0

12.1 CNT/DLY0 Register Settings

Figure 42. CNT/DLY1 Table 54. CNT/DLY0 Register Settings

12.2 CNT/DLY1 Register Settings

Table 55. CNT/DLY1 Register Settings

13.0 Voltage Reference (VREF)

13.1 Voltage Reference Overview

13.2 VREF Selection Table

Table 56. VREF Selection Table.

11001 VDD / 4 VDD / 4

11000 VDD / 3 VDD / 3

13.3 VREF Block Diagram

Figure 43. Voltage Reference Block Diagram

14.0 RC Oscillator (RC Osc)

14.1 RC Oscillator Overview

Note: RC OSC power setting: "Auto Power On”. Figure 44. Maximum Power On Delay vs. VDD, RC OSC = 2 MHz. Figure 45. Maximum Power On Delay vs. VDD, RC OSC = 25 kHz.

lines <30>, and <31>. See Figure 46 below for details of the frequencies for each of these five Connection Matrix Inputs. will be turned off. The PWR DOWN signal has the highest priority.

14.2 RC OSC Block Diagram

Figure 46. RC OSC Block Diagram

000-0046120-108 Page 71 of 91 SLG46120

15.0 Power On Rest (POR)

The SLG46120 has a power-on reset (POR) macrocell to ensure cor rect device initialization and operation of all macrocells in the device. The purpose of the POR circuit is to have consisten t behavior and predictable results when the VDD power is first ramping to the device, and also while the VDD is falling during power-down. To accomplish this goal, the POR drives a defined sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of the I/O pins. This application note is created to explain the whole process of POR operation and GreenPAK chip behavior during the time while it is powering up and powering down.

15.1 General Operation

The SLG46120 is guaranteed to be powered down and nonoperational when the VDD voltage (voltage on PIN1) is less than 0.6V, but not less than -0.6 V. Another essential condition for the chip to be powered down is that no voltage higher (see Note 1) than the VDD voltage is applied to any other PIN. For example, if VD D voltage is 0.3 V, applying a voltage higher than 0.3V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior. Note 1. There is a 0.6 V margin due to forward drop voltage of the ESD protection diodes. To start the POR sequence in the SLG46120, the voltage applied on the VDD should be higher than the Power_ON threshold voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power_ON threshold. After the POR sequence has started, the SLG46120 will have a typical period of time to go through all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after the POR sequence is complete. Note 2. The Power_ON threshold can vary by PVT, but typically it is 1.6V. To power down the chip the VDD voltage should be lower than the operational and to guarantee that chip is powered down it should be less than 0.6 V. All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step in the POR sequence releases the I/O structures from the high impedance state, at which time the device is operational. The pin configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.

15.2 POR Sequence

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 47. environmental factors, such as: slew rate, VDD value, temperature and even will vary from chip to chip (process influence). Figure 47. POR sequence

15.3 Macrocells Output States During POR Sequence

states during the POR sequence (Figure 48 describes the output signals states). last are output PINs that become active and determined by the input signals. Figure 48. Internal Macrocell States during POR sequence

000-0046120-108 Page 74 of 91 SLG46120

16.0 Appendix A - SLG46120 Register Definition

Address Signal Function Register Bit Definition reg<5:0> Matrix Out: PIN3 Digital Output Source reg<11:6> Matrix Out: PIN4 Digital Output Source reg<17:12> Matrix Out: PIN 5 Digital Output Source reg<23:18> Matrix Out: PIN 6 Digital Output Source reg<29:24> Matrix Out: Output Enable of PIN6 reg<35:30> Matrix Out: In0 of LU T2_0 or Clock Input of DFF0 reg<41:36> Matrix Out: In1 of LUT2_0 or Data Input of DFF0 reg<47:42> Matrix Out: In0 of LU T2_1 or Clock Input of DFF1 reg<53:48> Matrix Out: In1 of LUT2_1 or Data Input of DFF1 reg<59:54> Matrix Out: In0 of LU T2_2 or Clock Input of DFF2 reg<65:60> Matrix Out: In1 of LUT2_2 1 or Data Input of DFF2 reg<71:66> Matrix Out: In0 of LU T2_3 or Clock Input of DFF3 reg<77:72> Matrix Out: In1 of LUT2_3 1 or Data Input of DFF3 reg<83:78> Matrix Out: In0 of LUT2_4 reg<89:84> Matrix Out: In1 of LUT2_4 reg<95:90> Matrix Out: PIN 11 Digital Output Source reg<101:96> Matrix Out: PIN12 Digital Output Source reg<107:102> Matrix Out: In0 of LU T3_0 or Clock Input of DFF4 reg<113:108> Matrix Out: In1 of LUT3_0 or Data Input of DFF4 reg<119:114> Matrix Out: In2 of LUT3_0 or Resetb Input of DFF4 reg<125:120> Matrix Out: In0 of LU T3_1 or Clock Input of DFF5 reg<131:126> Matrix Out: In1 of LUT3_1 or Data Input of DFF5 reg<137:132> Matrix Out: In2 of LU T3_1 or Resetb(Setb) of DFF5 reg<143:138> Matrix Out: In0 of LU T3_2 or Clock Input of DFF6 reg<149:144> Matrix Out: In1 of LUT3_2 or Data Input of DFF6 reg<155:150> Matrix Out: In2 of LU T3_2 or Resetb Input of DFF6 reg<161:156> Matrix Out: In0 of LU T3_3 or Clock Input of DFF7 reg<167:162> Matrix Out: In1 of LUT3_3 or Data Input of DFF7 reg<173:168> Matrix Out: In2 of LU T3_3 or Resetb(Setb) of DFF7 reg<179:174> Matrix Out: In0 of LUT3_4 reg<185:180> Matrix Out: In1 of LUT3_4 reg<191:186> Matrix Out: In2 of LUT3_4 reg<197:192> Matrix Out: In0 of LUT3_5 reg<203:198> Matrix Out: In1 of LUT3_5 reg<209:204> Matrix Out: In2 of LUT3_5 reg<215:210> Matrix Out: In0 of LUT3_6 reg<221:216> Matrix Out: In1 of LUT3_6 reg<227:222> Matrix Out: In2 of LUT3_6 reg<233:228> Matrix Out: In0 of LUT3_7 reg<239:234> Matrix Out: In1 of LUT3_7 reg<245:240> Matrix Out: In2 of LUT3_7

000-0046120-108 Page 75 of 91 SLG46120 reg<251:246> Matrix Out: In0 of LU T3_8 or Input of Pipe delay reg<257:252> Matrix Out: In1 of LUT3_8 or Resetb of Pipe delay reg<263:258> Matrix Out: In2 of LUT3_8 or Clock of Pipe delay reg<269:264> Matrix Out: In0 of LUT4_0 or Input for delay2(couter2) external clock reg<275:270> Matrix Out: In1 of LUT4_0 or Input for delay2 da- ta(counter2 reset) reg<281:276> Matrix Out: In2 of LUT4_0 reg<287:282> Matrix Out: In3 of LUT4_0 reg<293:288> Matrix Out: In0 of LUT4_1 or Input for delay3(couter3) external clock reg<299:294> Matrix Out: In1 of LUT4_1 or Input for delay3 da- ta(counter3 reset) reg<305:300> Matrix Out: In2 of LUT4_1 reg<311:306> Matrix Out: In3 of LUT4_1 reg<317:312> Matrix Out: Input for delay0 data(counter0 external clock) reg<323:318> Matrix Out: Input for delay1(counter1) external clock reg<329:324> Matrix Out: Input for delay1 data(counter1 reset) reg<335:330> Matrix Out: Not used reg<341:336> Matrix Out: pdb(power down) for ACMP0 reg<347:342> Matrix Out: pdb(power down) for ACMP1 reg<353:348> Matrix Out: Input for programmable delay (deglitch filter input) reg<359:354> Matrix Out: Power down for osc (1: Power down) reg<365:360> Matrix Out: PIN8 Digital Output Source reg<371:366> Matrix Out: PIN9 Digital Output Source reg<377:372> Matrix Out: PIN 10 Digital Output Source reg<383:378> Matrix Out: Output Enable of PIN10 reg<389:384> Reserved reg<395:390> Reserved LUT2_0 or DFF0 reg<399:396> LUT2_0 data or the following reg<396> DFF0 or Latch select 0: DFF function 1: Latch function reg<397> DFF0 output select 0: Q output 1: nQ output reg<398> DFF0 initial polarity select 0: Low 1: High LUT2_1 or DFF1 reg<403:400> LUT2_1 data or the following 0: DFF function 1: Latch function reg<400> DFF1 or Latch select 0: DFF function 1: Latch function reg<401> DFF1 output select 0: Q output 1: nQ output Register Bit Address Signal Function Register Bit Definition

000-0046120-108 Page 76 of 91 SLG46120 reg<402> DFF1 initial polarity select 0: Low 1: High LUT2_2 or DFF2 reg<407:404> LUT2_2 data or the following reg<404> DFF2 or Latch select 0: DFF function 1: Latch function reg<405> DFF2 output select 0: Q output 1: nQ output reg<406> DFF2 initial polarity select 0: Low 1: High LUT2_3 or DFF3 reg<411:408> LUT2_3 dat a or the following reg<408> DFF3 or Latch select 0: DFF function 1: Latch function reg<409> DFF3 output select 0: Q output 1: nQ output reg<410> DFF3 initial polarity select 0: Low 1: High LUT2_4 reg<415:412> LUT2_4 data reg<419:416> Reserved LUT2_0/DFF_0 Select reg<420> LUT2_0 or DFF0 select 0: LUT2_0 1: DFF0 reg<421> LUT2_1 or DFF1 select 0: LUT2_1 1: DFF1 reg<422> LUT2_2 or DFF2 select 0: LUT2_2 1: DFF2 reg<423> LUT2_3 or DFF3 select 0: LUT2_3 1: DFF3 LUT3_0 or DFF4 reg<431:424> LUT3_0 data or the following reg<424> DFF4 or Latch select 0: DFF function 1: Latch function reg<425> DFF4 output select 0: Q output 1: nQ output reg<426> DFF4 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg<427> DFF4 initial polarity select 0: Low 1: High LUT3_1 or DFF5 reg<439:432> LUT3_1 data or the following reg<432> DFF5 or Latch select 0: DFF function 1: Latch function reg<433> DFF5 output select 0: Q output 1: nQ output reg<434> DFF5 rstb/setb select 0: resetb from matrix output 1: setb from matrix output Register Bit Address Signal Function Register Bit Definition

000-0046120-108 Page 77 of 91 SLG46120 reg<435> DFF5 initial polarity select 0: Low 1: High LUT3_2 or DFF6 reg<447:440> LUT3_2 data or the following reg<440> DFF6 or Latch select 0: DFF function 1: Latch function reg<441> DFF6 output select 0: Q output 1: nQ output reg<442> DFF6 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg<443> DFF6 initial polarity select 0: Low 1: High LUT3_3 or DFF7 reg<455:448> LUT3_3 data or the following reg<448> DFF7 or Latch select 0: DFF function 1: Latch function reg<449> DFF7 output select 0: Q output 1: nQ output reg<450> DFF7 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg<451> DFF7 initial polarity select 0: Low 1: High LUT3_4 reg<463:456> LUT3_4 data LUT3_5 reg<471:464> LUT3_5 data LUT3_6 reg<479:472> LUT3_6 data LUT3_7 reg<487:480> LUT3_7 data LUT3_8 or pipe number select reg<495:488> LUT3_8 data or the following reg<490:488> OUT0 select data (pipe number) reg<493:491> OUT1 select data (pipe number) reg<495:494> Unused if Pipe Delay selected Unused LUT3/DFF Select reg<496> LUT3_0 or DFF4 select 0: LUT3_0 1: DFF4 reg<497> LUT3_1 or DFF5 select 0: LUT3_1 1: DFF5 reg<498> LUT3_2 or DFF6 select 0: LUT3_3 1: DFF6 reg<499> LUT3_3 or DFF7 select 0: LUT3_4 1: DFF7 reg<500> LUT3_8 or pipe delay output select 0: LUT3_8 1: pipe delay Register Bit Address Signal Function Register Bit Definition

000-0046120-108 Page 78 of 91 SLG46120 LUT4_0 or Counter/Delay2 reg<516:501> LUT4_0 data data or the following reg<501> Counter/delay 2 mode selection 0: Delay Mode 1: Counter Mode reg<504:502> Counter/delay 2 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock 111: Counter1 Overflow reg<512:505> Counter/delay2 Contro l Data 1 - 256 (delay time = ( counter control data +2) /freq ) reg<514:513> Delay2 Mode Selec t or asynchronous counter reset 00: on both falling and rising edges(for delay & count- er reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset for counter mode reg<517> LUT4_0 or Counter2 select 0: LUT4_0 1: Counter2 LUT4_1 or Counter/Delay3 reg<533:518> LUT4_1 data or the following reg<518> Counter/delay 3 mode selection 0: De lay Mode 1: Counter Mode reg<521:519> Counter/delay 3 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock 111: Counter1 Overflow reg<529:522> Counter/delay3 Contro l Data 1 - 256 (delay time = (counter control data +2) /freq ) reg<531:530> Delay3 Mode Select or asynchronous counter reset 00: on both falling and rising edges(for delay & count- er reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset for counter mode reg<534> LUT4_1 or Counter3 select 0: LUT4_1 1: Counter3 RC Osc reg<535> Force RC oscillator on 0: Auto Power on 1: Force Power on reg<536> RC Oscillato r frequency control 0: 25 kHz 1: 2 MHz reg<538:537> Osc clock pre-divider 00:div1 01:div2 10: div4 11: div8 Register Bit Address Signal Function Register Bit Definition

000-0046120-108 Page 79 of 91 SLG46120 reg<541:539> Internal Oscillator frequency divider control 0 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 reg<544:542> Internal Oscillator frequency divider control 1 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 reg<545> External Clock Source Select 0: Internal Oscillator 1: External Clock from Pin12 reg<546> Manufacturing test mode reg<547> Reserved Counter/Delay 0 reg<548> Counter/delay 0 mode selection 0: Delay Mode 1: Counter Mode reg<551:549> Counter/delay0 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock 111: Counter3 Overflow reg<565:552> Counter0 Control Data/Delay0 Time Control 1-16384: (delay time = (counter control data +2) /freq) reg<567:566> Delay0 Mode Select o r asynchronous counter reset 00: on both falling and rising edges(for delay & count- er reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset for counter mode Counter/Delay 1 reg<568> Counter/delay 1 mode selection 0: Delay Mode 1: Counter Mode reg<571:569> Counter/delay 1 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock 111: Counter0 Overflow reg<579:572> Counter1 Control Data /Delay1 Time Control 1-256: (de lay time = (counter control data +2) /freq) Register Bit Address Signal Function Register Bit Definition

000-0046120-108 Page 80 of 91 SLG46120 reg<581:580> Delay1 Mode Select o r asynchronous counter reset 00: on both falling and rising edges(for delay & count- er reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset for counter mode reg<595:582> Reserved ACMP0 reg<600:596> ACMP0 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: EXT_VREF(PIN4) reg<602:601> ACMP0 hysteresis Enable 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) reg<604:603> ACMP0 positive Input divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X reg<605> ACMP0 low bandwidth ( typ: Max.1 MHz) enable. 0: off 1: on reg<606> ACMP0 positive input source select PIN3 and VDD 0: PIN3 1: VDD ACMP1 reg<611:607> ACMP1 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: EXT_VREF(PIN4) reg<613:612> ACMP1 hysteresis Enable 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) Register Bit Address Signal Function Register Bit Definition

000-0046120-108 Page 81 of 91 SLG46120 reg<615:614> ACMP1 positive Input divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X reg<616> ACMP1 100uA c urrent source option 0: disable 1: enable reg<617> ACMP1 low bandwidth (typ: Max.1Mhz) enable. 0: off 1: on reg<618> ACMP1 positive input source select PIN6 and PIN3 0: PIN3 1: PIN6 reg<622:619> Reserved Reserved PIN 2 reg<624:623> PIN2 mode control 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved reg<626:625 > PIN2 pull down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M PIN 3 reg<629:627 > PIN3 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Analog Input 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input & Open drain reg<631:630 > PIN3 pull up/down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M reg<632> PIN3 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<633> PIN3 driver strength selection 0: 1X 1: 2X PIN 4 reg<636:634> PIN4 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Analog Input 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input & Open drain reg<638:637> PIN4 pull up/down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M reg<639> PIN4 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable Register Bit Address Signal Function Register Bit Definition

000-0046120-108 Page 82 of 91 SLG46120 reg<640> PIN4 driver strength selection 0: 1X 1: 2X PIN 5 reg<643:641> PIN5 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Analog Input 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input & Open drain reg<645:644> PIN5 pull up/down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M reg<646> PIN5 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<647> PIN5 driver strength selection 0: 1X 1: 2X PIN 6 reg<649:648> PIN6 mode c ontrol (sig_pin6_oe =0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Analog Input / Output reg<651:650> PIN6 mode c ontrol (sig_pin6_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11:Open Drain NMOS 2X reg<653:652> PIN6 pull up/down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M reg<654> PIN6 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable PIN8 reg<657:655> PIN8 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Analog Input / Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved reg<659:658> PIN8 pull up/down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M reg<660> PIN8 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<661> PIN8 driver strength selection 0: 1X 1: 2X Register Bit Address Signal Function Register Bit Definition

000-0046120-108 Page 83 of 91 SLG46120 PIN 9 reg<664:662> PIN9 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Open drain reg<666:665> PIN9 pull down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M reg<667> PIN9 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<668> PIN9 driver strength selection 0: 1X 1: 2X PIN 10 reg<670:669> PIN10 mode control (sig_pin10_oe =0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Analog Input / Output reg<672:671> PIN10 mode control (sig_pin10_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11:Open Drain NMOS 2X reg<674:673> PIN10 pull up/dow n resistor value selection 00: floating 01: 10K 10: 100K 11: 1M reg<675> PIN10 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable PIN 11 reg<678:676> PIN11 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Open drain reg<680:679> PIN11 pull up/dow n resistor value selection 00: floating 01: 10K 10: 100K 11: 1M reg<681> PIN11 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<682> PIN11 driver strength selection 0: 1X 1: 2X Register Bit Address Signal Function Register Bit Definition

000-0046120-108 Page 84 of 91 SLG46120 PIN 12 reg<685:683> PIN12 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Open drain reg<687:686> PIN12 pull up/dow n resistor value selection 00: floating 01: 10k 10: 100K 11: 1M reg<688> PIN12 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<689> PIN12 driver strength selection 0: 1X 1: 2X Reg<690> Pipe delay OUT1 polarity select bit 0: Non-inverted 1: Inverted reg<698:691> 8-bit pattern id reg<699> filter0 output polarity select 0: Non-inverting 1: Inverting reg<701:700> Reserved Reserved reg<702> GPIO quick charge enable 0: Disable 1: Enable reg<706:703> Reserved Reserved reg<707> Force bandgap on 0: Auto-mode 1: Enable reg<708> VREF1 Output Active Buffer Control 0: Disabled 1: Enabled reg<711:709> VREF1 Output Source Select 000: ACMP0 reference voltage 001: ACMP1 reference voltage 100: VDD/2 101: VDD/3 110: VDD/4 reg<712> NVM dat a read disable 0: Disable (read enable) 1: Enable (read disable) reg<713> NVM power down (or NV M data programming disable) 0: None (or programming enable) 1: Power Down (or programming disable) reg<714> Power Divider Power 0: Power down 1: Power On reg<715> POR Auto Power detect 0: Enable 1: Disable reg<716> Charge pump for analog macrocell enable (when VDD <=2.7V turn on) 0: Disable (automatic on/off control) 1: Enable (always on) reg<717> VDD bypass enable 0: Regulator auto on 1: Regualtor off (VDD bypass) reg<718> PIN2 edge detect mode 0: rising edge 1: falling edge reg<719> Bypass the pin2 0: PIN2 edge active 1: PIN2 high active Register Bit Address Signal Function Register Bit Definition

000-0046120-108 Page 85 of 91 SLG46120 reg<720> PIN2 reset enable 0: Disable 1: Enable reg<721> Reserved Reserved reg<727:722> Reserved Reserved reg<735:728> Reserved Reserved reg<741:736> Reserved Reserved reg<743:742> Delay value select for programmable delay & edge de- tector (VDD = 3.3V, typical condition) 00: 163 ns 01: 305 ns 10: 446 ns 11: 588 ns reg<745:744> Select the edge mode of programmable delay & edge detector 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay reg<746> programmable delay or filter output select 0: programmable delay output 1: filter output reg<751:747> Reserved Reserved reg<757:752> Reserved Reserved reg<758> Reserved Reserved reg<759> Reserved Reserved reg<767:760> Reserved Reserved Register Bit Address Signal Function Register Bit Definition

000-0046120-108 Page 86 of 91 SLG46120

17.0 Package Top Marking System Definition

P P A Part Code + Assembly Code Pin 1 Identifier WWR Date Code + Revision Code NN Serial Number Code

000-0046120-108 Page 87 of 91 SLG46120

18.0 Package Drawing and Dimensions

12 Lead STQFN FCA Package 1.6 x 1.6 mm

000-0046120-108 Page 88 of 91 SLG46120

19.0 Tape and Reel Specifications

19.1 Carrier Tape Drawing and Dimensions

# of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm]per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 12L FCA 0.4P Green 10 1.6x1.6x0.55 3000 3000 178/60 100 400 100 400 8 4 Package Type Pocket BTM Length [mm] Pocket BTM Width [mm] Pocket Depth [mm] Index Hole Pitch [mm] Pocket Pitch [mm] Index Hole Diameter [mm] Index Hole to Tape Edge [mm] Index Hole to Pocket Center [mm] Tape Width [mm] A0 B0 K0 P0 P1 D0 E F W STQFN 12L FCA 0.4P Green

000-0046120-108 Page 89 of 91 SLG46120

20.0 Recommended Land Pattern

21.0 Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: l atest revision for reflow prof ile based on package volume of 1.408 mm 3 (nominal). More information can be found at www.jedec.org. Units: m

000-0046120-108 Page 90 of 91 SLG46120

22.0 Revision History

10/10/2017 1.08 Updated Electrical Spec Fixed typos Updated POR sequence 7/7/2017 1.07 Updated Section Programmable Delay / Edge Detector Fixed typos Updated Electrical Spec 12/22/2016 1.06 Fixed typos Updated Silego Website & Support 5/30/2016 1.05 Updated Silego Website & Support Updated Programmable Delay information Added PON THR and POFFTHR in Electrical Spec 10/28/2015 1.04 Updated Abso lute maximum conditions 10/20/2015 1.03 Fixed typos 8/11/2015 1.02 Fixed Programmabl e delay values in Section 7.0 7/23/2015 1.01 Updated User Programmability Updated Register Table for clarification 5/26/2015 1.0 Production Release 5/21/2015 0.59 Updated ACMP Diagram s and added Timing Characteristics Diagrams 4/23/2015 0.58 Updated ACMP section 4/9/2015 0.57 Updated Tsu condition and value 3/27/2015 0.56 Updated ACMP section Updated RC Oscillator section 3/10/2015 0.55 Added Con nection Matrix Example 3/9/2015 0.54 Added POR section 2/10/2015 0.53 Fixed Pr eliminary watermark 1/14/2015 0.52 Added IDD Estimator, Timing Estimator, Expected Delays sections 12/3/2014 0.51 Updated Electrical C haracteristics VIH/VIL/VOH/VOL values 9/26/2014 0.50 Preliminary Release 9/24/2014 0.27 Fixed typos 8/11/2014 0.26 Updated package information Added Recommended Land Pattern 7/29/2014 0.25 Fixed ESD information 6/20/2014 0.24 Updated Electrical Specifications VIH/VIL levels Fixed typos 5/21/2014 0.23 Updated block diagram Fixed typos Updated Pipe Delay information Moved Programmable Delay and Deglitch Filter to Combination Macrocells section 4/29/2014 0.22 Added ESD R atings and MSL to Absolute Maximum Conditions 4/15/2014 0.21 Updated bl ock diagrams and timing diagrams for clarity 2/12/2014 0.2 Added Macrocell Function Sections 1/16/2014 0.11 Added Register Table 9/16/2013 0.1 Initial release

000-0046120-108 Page 91 of 91 SLG46120 Silego Website & Support Silego Technology Website Silego Technology provides online support via our website at http://www.silego.com/.This website is used as a means to make files and information easily available to customers. For more information regarding Silego Green products, please visit our website. Our Green product lines feature: GreenPAK: Programmable Mixed Signal Matrix products GreenFET1 / GreenFET3 / HFET1: MOSFET Drivers and ultra-small, low RDSon Load Switches GreenCLK1 / GreenCLK2 / GreenCLK3: Crystal replacement technology Products are also available for purchase directly from Silego at the Silego Online Store at http://www.silego.com /buy/. Silego Technical Support Datasheets and errata, application notes and example designs, u ser guides, and hardware support documents and the latest software releases are available at the Silego website or can be requested directly at info@silego.com. For specific GreenPAK design or applications questions and support please send e-mail requests to GreenPAK@silego.com Users of Silego products can receive assistance through several channels: Contact Your Local Sales Representative Customers can contact their local sales representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. More information regarding your lo cal representative is available at the Silego website or send a request to info@silego.com Contact Silego Directly Silego can be contacted directly via e-mail at info@silego.com or user submission form, located at the following URL: http://support.silego.com/ Other Information The latest Silego Technology press releases, listing of seminars and events, listings of world wide Silego Technology offices and representatives are all available at http://www.silego.com/ THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. SILEGO TECHNOLOGY DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICA- TIONS OR USES OF ITS PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTI

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Dialog Semiconductor SLG46120V overview.

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Summary

Personal Computers and Servers

Description

Personal Computers and Servers

Source title SLG46120V Datasheet(PDF) - Dialog Semiconductor

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