SLG46117VTR

2 manufacturer specifications

Programmable Mixed-signal Matrix with P-FET Power Switch with Discharge Revised March 4, 2022

Manufacturer variants: 2

Selected specification: Renesas Technology Corp

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Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 91

Technical content

Features

Logic & Mixed Signal Circuits
Highly Versatile Macrocells
Read Back Protection (Read Lock)
1.8V (±5%) to 5V (±10%) Supply
Operating Temperature Range -40 °C to 85 °C
Soft-Start 1.25.A (@V IN = 3.3 V) P-FET Power Switch with discharge
Package
1.6 x 2.5 x 0.55 mm STQFN 14L package
Pb-Free / Halogen-Free / RoHS compliant

Applications

Power Sequencing with complex analog control
Power Plane component size reduction project
LED Driver
Haptic Motor Driver
System RESET with Power Switch Pin Configuration GND GPIO GPIO PWR_SW_ON GPIO GPIO GPI 1 14-pin STQFN (Top View) GND NC VIN 5 6 7 14 13 12 VOUT GPIO VDD GPIO 3-bit LUT3_4 or Pipe Delay Vref Programmable Delay RC Oscillator Pin 1 GPI Pin 2 GPIO Pin 3 GPIO Pin 4 PWR_SW Pin 14 VDD Pin 12 GPIO Pin 5 VIN Pin 7 VOUT Pin 9 GND Pin 8 GND Pin 11 GPIO Pin 10 GPIO ACMP0 ACMP1 Look Up Tables (LUTs) Counters/Delay Generators CNT0 CNT3 CNT1 2-bit LUT2_2 3-bit LUT3_3 2-bit LUT2_3 3-bit LUT3_2 Combination Function Macrocells 2-bit LUT2_0 or DFF0 2-bit LUT2_1 or DFF1 3-bit LUT3_1 or DFF3 3bit LUT3_0 or DFF2 4-bit LUT4_0 or CNT2 FILTER_0 Additional Logic Functions Pin 13 GPIO Pin 6 NC P-FET Power Switch

000-0046117-113 Page 1 of 89 SLG46117

1.0 Overview

The SLG46117 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Mem ory (NVM) to configure the interconnect logic, the I/O Pins and the macrocells of the SLG46117. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The SLG46117 includes the following:

Two Analog Comparators (ACMP)
Voltage References (Vref)
Four Combinatorial Look Up Tables (LUTs)
Two 2-bit LUTs
Two 3-bit LUTs
Seven Combination Function Macrocell
Two Selectable DFF/Latch or 2-bit LUTs
Two Selectable DFF/Latch or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
Pipe Delay – 8 stage / 2 output
One Selectable Counter/Delay or 4-bit LUT
One Programmable Delay/ Deglitch Filter
Three Counter / Delay Generators (CNT/DLY)
Three 8-bit counter/delays with external clock/reset
Four D Flip-Flop / Latches (DFF) (Part of Combinat ion Function Macrocell)
Pipe Delay – 8 stage/2 output (Part of Combination Function Macrocell)
Trimmed RC Oscillator (RC OSC)
Power On Reset (POR)
One Bandgap
Soft-Start P-FET Power Switch
Power Switch IDS: 1 A to 1.5 A
Slew Rate Control
VIN: 1.5 V to 5.5 V
Integrated Discharge Resistor
Low RDSON
28.5 m Ω @ 5.5 V
36.4 m Ω @ 3.3 V
44.3 m Ω @ 2.5 V
60.8 m Ω @ 1.8 V
77.6 m Ω @ 1.5 V

000-0046117-113 Page 2 of 89 SLG46117

2.0 Pin Description

2.1 Functional Pin Description

Pin # Pin Name Function

1 GPI General Purpose Input

2 GPIO General Purpose I/O or Analog Comparator 0 (+)

3 GPIO General Purpose I/O or Analog Comparator 0 (-)

4 PWR_SW_ON Input/Output

5 VIN P-FET Power Switch Input

6 NC No Connect

7 VOUT P-FET Power Switch Output

8 GND Ground

9 GND Ground

10 GPIO General Purpose I/O

11 GPIO General Purpose I/O or POR Output

12 GPIO General Purpose I/O with OE and Vref output

13 GPIO General Purpose I/O or External Clock Input

14 VDD Power Supply

3.0 User Programmability

will remain active on the device as long as it remains powered and can be re-written as needed to facilitate rapid design changes. Figure 1. Steps to create a custom GreenPAK device

000-0046117-113 Page 4 of 89 SLG46117

4.0 Ordering Information

SLG46117VTR STQFN 14L - Tape and Reel (3k units)

000-0046117-113 Page 5 of 89 SLG46117

5.0 Electrical Specifications

5.1 Absolute Maximum Conditions

5.2 Electrical Characteristics (1.8V ±5% V DD ) Parameter Condition Min. Max. Unit VIN -0.5 6 V VDD -0.5 7 V GPIO Voltage GND - 0.5 VDD + 0.5 V GPIO Output Current (Through pin) Push-Pull 1x -- 12 mA Push-Pull 2x -- 17 OD 1x -- 18 OD 2x -- 28 GPIO Input Current -1.0 1.0 mA Storage Temperature Range -65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1000 -- V Moisture Sensitivity Level 1 Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 1.71 1.80 1.89 V IQ Quiescent Current Static Inputs and Outputs -- 0.5 -- µA TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VAIR Analog Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.1 V VIH HIGH-Level Input Voltage Logic Input 1.100 -- V DD V Logic Input with Schmitt Trigger 1.270 -- V DD V Low-Level Logic Input 0.980 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 0.690 V Logic Input with Schmitt Trigger -- -- 0.440 V Low-Level Logic Input -- -- 0.520 V I IH HIGH-Level Input Current Logic Input Pins; V IN = 1.8 V -1.0 -- 1.0 µA IIL LOW-Level Input Current Logic Input Pins; V IN = 0 V -1.0 -- 1.0 µA VOH HIGH-Level Output Voltage Push-Pull 1X, Open Drain PMOS 1X, I OH = 100 µA 1.680 1.790 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 100 µA 1.702 1.800 -- V

000-0046117-113 Page 6 of 89 SLG46117 VOL LOW-Level Output Voltage Push-Pull 1X, I OL = 100 µA -- 0.020 0.030 V Push-Pull 2X, I OL = 100 µA -- 0.010 0.020 V Open Drain NMOS 1X, I OL = 100 µA -- 0.010 0.020 V Open Drain NMOS 2X, I OL = 100 µA -- 0.010 0.010 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, V OH = V DD - 0.2 1.040 1.400 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = V DD - 0.2 2.150 2.710 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, V OL = 0.15 V 0.760 1.340 -- mA Push-Pull 2X, V OL = 0.15 V 1.520 2.660 -- mA Open Drain NMOS 1X, V OL = 0.15 V 1.530 2.670 -- mA Open Drain NMOS 2X, V OL = 0.15 V 3.060 5.130 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T TSU Startup Time from VDD rising past 1.35 V -- 0.27 -- ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.182 1.346 1.505 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.752 0.918 1.110 V VIN Power Switch Input Voltage -40 °C to 85 °C 1.5 -- 5.5 V IIN Power Switch Current (PIN 5) when Off, V IN = 5.5 V -- 0.02 0.1 µA when PWR_SW_ON = V IN , No load -- 0.05 0.5 µA IDS_LKG Leakage Measured from PIN 5 to PIN 7 when Off, V IN = 5.5 V -- 0.05 1 µA ION_LKG PWR_SW_ON Pin Input Leakage -- -- 0.1 µA RDS ON Static Drain to Source ON Resistance @ T A 25°C @ V IN = 5.5 V -- 28.5 32.0 m Ω @ V IN = 3.3 V -- 36.4 40.0 m Ω @ V IN = 2.5 V -- 44.3 49.0 m Ω @ V IN = 1.8 V -- 60.8 65.0 m Ω @ V IN = 1.5 V -- 77.6 82.0 m Ω Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046117-113 Page 7 of 89 SLG46117 RDS ON Static Drain to Source ON Resistance @ T A 85°C @ V IN = 5.5 V -- 34.0 36.0 m Ω @ V IN = 3.3 V -- 43.8 46.0 m Ω @ V IN = 2.5 V -- 53.3 56.0 m Ω @ V IN = 1.8 V -- 72.2 76.0 m Ω @ V IN = 1.5 V -- 90.7 94.0 m Ω IDS Operating Current V IN = 1.5 V -- -- 1.0 A TOn_Delay PWR_SW_ON pin Delay Time 50% PWR_SW_ON to Ramp Begin, V IN = 5.0 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 12.0 15.0 18.5 µs 50% PWR_SW_ON to Ramp Begin, V IN = 3.3 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 17.0 22.0 30.0 µs 50% PWR_SW_ON to Ramp Begin, V IN = 1.5 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 44.0 55.0 76.0 µs TTotal_On Total Turn On Time 50% PWR_SW_ON to 90% VOUT, V IN = 5.0 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 114 122 134 µs 50% PWR_SW_ON to 90% VOUT, V IN = 3.3 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 146 156 176 µs 50% PWR_SW_ON to 90% VOUT, V IN = 1.5 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 292 332 399 µs TRISE Rise Time 10% VOUT to 90% VOUT, V IN = 5.0 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 92 97 107 µs 10% VOUT to 90% VOUT, V IN = 3.3 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 116 120 131 µs 10% VOUT to 90% VOUT, V IN = 1.5 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 228 253 296 µs RDIS Discharge Resistance VIN = 1.5 V to 5.5 V, V OUT = 0.4 V Input Bias 65 80 400 Ω PWR_SW _ON_V IH Initial Turn On Voltage 0.85 -- VIN or V DD V PWR_SW _ON_V IL Low Input Voltage on PWR_SW_ON pin -0.3 0 0.3 V T Delay_Off Off Delay Time 50% PWR_SW_ON to VOUT Fall, V IN = 5 V, R L =10 Ω 6.2 6.5 7.0 µs RPUP Pull Up Resistance

1 M Pull Up -- 1 -- M Ω

100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance

1 M Pull Down -- 1 -- M Ω

100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046117-113 Page 8 of 89 SLG46117 Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 1, 2 and 3 are connected to one side, pins 10, 11, 12 and 13 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046117-113 Page 9 of 89 SLG46117 5.3 Electrical Characteristics (3.3V ±10% V DD ) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3.0 3.3 3.6 V IQ Quiescent Current Static Inputs and Outputs -- 0.75 -- µA TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VAIR Analog Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 1.780 -- V DD V Logic Input with Schmitt Trigger 2.130 -- V DD V Low-Level Logic Input 1.130 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 1.210 V Logic Input with Schmitt Trigger -- -- 0.950 V Low-Level Logic Input -- -- 0.690 V I IH HIGH-Level Input Current Logic Input Pins; V IN = 3.3 V -1.0 -- 1.0 µA IIL LOW-Level Input Current Logic Input Pins; V IN = 0 V -1.0 -- 1.0 µA VOH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, I OH = 3 mA 2.710 3.090 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 3 mA 2.870 3.190 -- V VOL LOW-Level Output Voltage Push-Pull 1X, I OL = 3 mA -- 0.180 0.280 V Push-Pull 2X, I OL = 3 mA -- 0.090 0.130 V Open Drain NMOS 1X, I OL = 3 mA -- 0.090 0.130 V Open Drain NMOS 2X, I OL = 3 mA -- 0.050 0.070 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, V OH = 2.4 V 5.830 10.180 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = 2.4 V 11.264 19.660 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, V OL = 0.4 V 4.060 6.440 -- mA Push-Pull 2X, V OL = 0.4 V 8.130 12.360 -- mA Open Drain NMOS 1X, V OL = 0.4 V 8.130 12.410 -- mA Open Drain NMOS 2X, V OL = 0.4 V 16.260 22.900 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T TSU Startup Time from VDD rising past 1.35 V -- 0.27 - ms

000-0046117-113 Page 10 of 89 SLG46117 PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.182 1.346 1.505 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.752 0.918 1.110 V VIN Power Switch Input Voltage -40 °C to 85 °C 1.5 -- 5.5 V IIN Power Switch Current (PIN 5) when Off, V IN = 5.5 V -- 0.02 0.1 µA when PWR_SW_ON = V IN , No load -- 0.05 0.5 µA IDS_LKG Leakage Measured from PIN 5 to PIN 7 when Off, V IN = 5.5 V -- 0.05 1 µA ION_LKG PWR_SW_ON Pin Input Leakage -- -- 0.1 µA RDS ON Static Drain to Source ON Resistance @ T A 25°C @ V IN = 5.5 V -- 28.5 32.0 m Ω @ V IN = 3.3 V -- 36.4 40.0 m Ω @ V IN = 2.5 V -- 44.3 49.0 m Ω @ V IN = 1.8 V -- 60.8 65.0 m Ω @ V IN = 1.5 V -- 77.6 82.0 m Ω RDS ON Static Drain to Source ON Resistance @ T A 85°C @ V IN = 5.5 V -- 34.0 36.0 m Ω @ V IN = 3.3 V -- 43.8 46.0 m Ω @ V IN = 2.5 V -- 53.3 56.0 m Ω @ V IN = 1.8 V -- 72.2 76.0 m Ω @ V IN = 1.5 V -- 90.7 94.0 m Ω IDS Operating Current V IN = 1.5 V -- -- 1.0 A TOn_Delay PWR_SW_ON pin Delay Time 50% PWR_SW_ON to Ramp Begin, V IN = 5.0 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 12.0 15.0 18.5 µs 50% PWR_SW_ON to Ramp Begin, V IN = 3.3 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 17.0 22.0 30.0 µs 50% PWR_SW_ON to Ramp Begin, V IN = 1.5 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 44.0 55.0 76.0 µs TTotal_On Total Turn On Time 50% PWR_SW_ON to 90% VOUT, V IN = 5.0 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 114 122 134 µs 50% PWR_SW_ON to 90% VOUT, V IN = 3.3 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 146 156 176 µs 50% PWR_SW_ON to 90% VOUT, V IN = 1.5 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 292 332 399 µs TRISE Rise Time 10% VOUT to 90% VOUT V IN = 5.0 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 92 97 107 µs 10% VOUT to 90% VOUT V IN = 3.3 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 116 120 131 µs 10% VOUT to 90% VOUT V IN = 1.5 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 228 253 296 µs Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046117-113 Page 11 of 89 SLG46117 RDIS Discharge Resistance VIN = 1.5 V to 5.5 V, V OUT = 0.4 V Input Bias 65 80 400 Ω PWR_SW _ON_V IH Initial Turn On Voltage 0.85 -- VIN or V DD V PWR_SW _ON_V IL Low Input Voltage on PWR_SW_ON pin -0.3 0 0.3 V T Delay_Off Off Delay Time 50% PWR_SW_ON to VOUT Fall, V IN = 5 V, R L =10 Ω 6.2 6.5 7.0 µs RPUP Pull Up Resistance 100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance 100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 1, 2 and 3 are connected to one side, pins 10, 11, 12 and 13 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046117-113 Page 12 of 89 SLG46117

5.4 Electrical Characteristics (5V ±10% V DD )

Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V IQ Quiescent Current Static Inputs and Outputs -- 1.0 -- µA TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VAIR Analog Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 2.640 -- V DD V Logic Input with Schmitt Trigger 3.160 -- V DD V Low-Level Logic Input 1.230 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 1.840 V Logic Input with Schmitt Trigger -- -- 1.510 V Low-Level Logic Input -- -- 0.780 V I IH HIGH-Level Input Current Logic Input Pins; V IN = 5 V -1.0 -- 1.0 µA IIL LOW-Level Input Current Logic Input Pins; V IN = 0 V -1.0 -- 1.0 µA VOH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, I OH = 5 mA 4.150 4.730 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 5 mA 4.300 4.860 -- V VOL LOW-Level Output Voltage Push-Pull 1X, I OL = 5 mA -- 0.230 0.330 V Push-Pull 2X, I OL = 5 mA -- 0.120 0.160 V Open Drain NMOS 1X, I OL = 5 mA -- 0.120 0.160 V Open Drain NMOS 2X, I OL = 5 mA -- 0.070 0.090 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, V OH = 2.4 V 21.808 29.099 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = 2.4 V 40.598 56.078 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, V OL = 0.4 V 6.010 9.730 -- mA Push-Pull 2X, V OL = 0.4 V 11.585 19.460 -- mA Open Drain NMOS 1X, V OL = 0.4 V 11.756 19.460 -- mA Open Drain NMOS 2X, V OL = 0.4 V 19.120 35.621 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T TSU Startup Time from VDD rising past 1.35 V -- 0.27 - ms

000-0046117-113 Page 13 of 89 SLG46117 PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.182 1.346 1.505 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.752 0.918 1.110 V VIN Power Switch Input Voltage -40 °C to 85 °C 1.5 -- 5.5 V IIN Power Switch Current (PIN 5) when Off, V IN = 5.5 V -- 0.02 0.1 µA when PWR_SW_ON = V IN , No load -- 0.05 0.5 µA IDS_LKG Leakage Measured from PIN 5 to PIN 7 when Off, V IN = 5.5 V -- 0.05 1 µA ION_LKG PWR_SW_ON Pin Input Leakage -- -- 0.1 µA RDS ON Static Drain to Source ON Resistance @ T A 25°C @ V IN = 5.5 V -- 28.5 32.0 m Ω @ V IN = 3.3 V -- 36.4 40.0 m Ω @ V IN = 2.5 V -- 44.3 49.0 m Ω @ V IN = 1.8 V -- 60.8 65.0 m Ω @ V IN = 1.5 V -- 77.6 82.0 m Ω RDS ON Static Drain to Source ON Resistance @ T A 85°C @ V IN = 5.5 V -- 34.0 36.0 m Ω @ V IN = 3.3 V -- 43.8 46.0 m Ω @ V IN = 2.5 V -- 53.3 56.0 m Ω @ V IN = 1.8 V -- 72.2 76.0 m Ω @ V IN = 1.5 V -- 90.7 94.0 m Ω IDS Operating Current V IN = 1.5 V -- -- 1.0 A TOn_Delay PWR_SW_ON pin Delay Time 50% PWR_SW_ON to Ramp Begin V IN = 5 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 12.0 15.0 18.5 µs 50% PWR_SW_ON to Ramp Begin V IN = 3.3 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 17.0 22.0 30.0 µs 50% PWR_SW_ON to Ramp Begin V IN = 1.5 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 44.0 55.0 76.0 µs TTotal_On Total Turn On Time 50% PWR_SW_ON to 90% VOUT V IN = 5 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 114 122 134 µs 50% PWR_SW_ON to 90% VOUT V IN = 3.3 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 146 156 176 µs 50% PWR_SW_ON to 90% VOUT V IN = 1.5 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 292 332 399 µs TRISE Rise Time 10% VOUT to 90% VOUT V IN = 5.0 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 92 97 107 µs 10% VOUT to 90% VOUT V IN = 3.3 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 116 120 131 µs 10% VOUT to 90% VOUT V IN = 1.5 V, VOUT_Cap = 0.1 µF, RL = 10 Ω 228 253 296 µs Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046117-113 Page 14 of 89 SLG46117 RDIS Discharge Resistance VIN = 1.5 V to 5.5 V, V OUT = 0.4 V Input Bias 65 80 400 Ω PWR_SW _ON_V IH Initial Turn On Voltage 0.85 -- VIN or V DD V PWR_SW _ON_V IL Low Input Voltage on PWR_SW_ON pin -0.3 0 0.3 V T Delay_Off Off Delay Time 50% PWR_SW_ON to VOUT Fall, V IN = 5 V, R L =10 Ω 6.2 6.5 7.0 µs RPUP Pull Up Resistance 100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance 100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 1, 2 and 3 are connected to one side, pins 10, 11, 12 and 13 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

5.5 IDD Estimator

5.6 Timing Estimator

Table 1. Typical Current estimated for each macrocell. Table 2. Typical Delay estimated for each macrocell.

5.7 Typical Counter/Delay Offset Measurements

5.8 Expected Delays and Widths

Table 3. Typical Counter/Delay Offset Measurements. Table 4. Expected Delays and Widths for Programmable Delay (typical).

5.9 Typical Pulse Width Performance

Table 5. Typical Pulse Width Performance.

000-0046117-113 Page 18 of 89 SLG46117

5.11 TTotal_On , T On_Delay and Slew Rate Measurement

90% VOUT 50% PWR_SW_ON TOn_Delay TRISE PWR_SW_ON VOUT TTotal_On 10% VOUT 50% PWR_SW_ON 10% VOUT TDelay_Off TFALL 90% VOUT

000-0046117-113 Page 19 of 89 SLG46117

6.0 Summary of Macrocell Function

6.1 I/O Pins

Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
Open Drain Outputs
Push Pull Outputs
Analog I/O
10 k Ω /100 k Ω /1 M Ω pull-up/pull-down resistors

6.2 Connection Matrix

Digital matrix for circuit connections based on us er design

6.3 Analog Comparators (2 total)

Selectable hysteresis 0 mV/25 mV/50 mV/200 mV

6.4 Voltage Reference

Used for references on Analog Comparators
Can also be driven to external pins

6.5 Combinational Logic Look Up Tables (LUTs – 4 total)

Two 2-bit Lookup Tables
Two 3-bit Lookup Tables

6.6 Combination Function Macrocells (7 total)

Two Selectable DFF/Latch or 2-bit LUTs
Two Selectable DFF/Latch or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
One Selectable CNT/DLY or 4-bit LUT
One Programmable Delay/ Deglitch Filter

6.7 Delays/Counters (3 total)

Three 8-bit delays/counters with external clock/re set: Range 1-255 clock cycles

6.8 Pipe Delay (Part of Combination Function Macrocell)

8 stage / 2 output
Two 1-8 stage selectable outputs

6.9 Programmable Delay

125 ns/250 ns/375 ns/500 ns @ 3.3 V
Includes Edge Detection function

000-0046117-113 Page 20 of 89 SLG46117

6.10 RC Oscillator

25 kHz and 2 MHz selectable frequency
First stage divider (4): OSC/1, OSC/2, OSC/4, and OSC/8
Second stage divider (8): selectable (OSC/1, OSC/2 , OSC/3, OSC/4, OSC/8, OSC/12, OSC/24, or OSC/64)

6.11 Power On Reset (POR)

000-0046117-113 Page 21 of 89 SLG46117

7.0 I/O Pins

The SLG46117 has a total of 7 multi-function I/O pi ns which can function as either a user defined Inpu t or Output, as well as serving as a special function (such as outputting the voltage reference). Refer to Section 2.0 Pin Description for pin definitions. Of the 7 user defined I/O pins on the SLG46117, all but one of the pins (Pin 1) can serve as both digital input and digital output. Pin 1 can only serve as a digital input pin.

7.1 Input Modes

Each I/O pin can be configured as a digital input p in with/without buffered Schmitt trigger, or can al so be configured as a low voltage digital input. Pins 2 and 3 can also be configured to serve as analog inputs to the on-chip comparators.

7.2 Output Modes

Pins 2, 3, 10, 11, 12, and 13 can all be configured as digital output pins.

7.3 Pull Up/Down Resistors

All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors are 10 k Ω , 100 k Ω and 1 M Ω . In the case of Pin 1, the resistors are fixed to a pull-down configuration. In the case of all other I/O pins, the internal resistors can be configured as either pull-up or pull-downs.

7.4 I/O Register Settings

7.4.1 PIN 1 Register Settings

7.4.2 PIN 2 Register Settings

Table 6. PIN 1 Register Settings Table 7. PIN 2 Register Settings

7.4.3 PIN 3 Register Settings

7.4.4 PIN 10 Register Settings

Table 8. PIN 3 Register Settings Table 9. PIN 10 Register Settings

7.4.5 PIN 11 Register Settings

7.4.6 PIN 12 Register Settings

Table 10. PIN 11 Register Settings Table 11. PIN 12 Register Settings

7.4.7 PIN 13 Register Settings

Table 12. PIN 13 Register Settings

7.5 GPI IO Structure

7.5.1 GPI IO Structure (for Pin 1)

Figure 2. PIN 2 GPI IO Structure Diagram

7.6 Matrix OE IO Structure

7.6.1 Matrix OE IO Structure (for Pin 12)

Figure 3. Matrix OE IO Structure Diagram

7.7 Register OE IO Structure

7.7.1 Register OE IO Structure (for Pins 2, 3, 10, 11, 13)

Figure 4. Register OE IO Structure Diagram

8.0 Connection Matrix

macrocell uses a 5-bit register to select one of these 32 input lines. For a complete list of the SLG46117’s register table, see Section 19.0 Appendix A - SLG46117 Register Definition. Figure 5. Connection Matrix Figure 6. Connection Matrix Example

8.1 Matrix Input Table

Table 13. Matrix Input Table

0 VSS 0 0 0 0 0

1 PIN 1 digital Input 0 0 0 0 1

2 PIN 2 digital Input 0 0 0 1 0

3 PIN 3 digital Input 0 0 0 1 1

4 PIN 4 digital Input 0 0 1 0 0

5 LUT2_0 output (DFF/LATCH_0 output) 0 0 1 0 1

6 LUT2_1 output (DFF/LATCH_1 output) 0 0 1 1 0

7 LUT2_2 output 0 0 1 1 1

8 LUT2_3 output 0 1 0 0 0

9 LUT3_0 output (DFF/LATCH_2 output with resetb or s eb) 0 1 0 0 1

10 LUT3_1 output (DFF/LATCH_3 output with resetb or seb) 0 1 0 1 0

11 LUT3_2 output 0 1 0 1 1

12 LUT3_3 output 0 1 1 0 0

13 LUT3_4 output(pipe delay ouput0) 0 1 1 0 1

15 LUT4_0 output (CNT_DLY2 output (8 bit w/ ext CK,r eset)) 0 1 1 1 1

16 CNT_DLY0 output (8 bit w/ ext CK (shared bottom d elay/cnt),reset) 1 0 0 0 0

17 CNT_DLY1 output (8 bit w/ ext CK (from dedicated matrix out -

18 CNT_DLY3 (8 bit) output 1 0 0 1 0

19 ACMP_0 output 1 0 0 1 1

20 ACMP_1 output 1 0 1 0 0

21 Edge detect output 1 0 1 0 1

22 Programmable delay with edge detector output (Deglitch filter out -

25 Bandgap OK signal 1 1 0 0 1

26 Resetb_core as matrix input 1 1 0 1 0

27 PIN 10 digital Input 1 1 0 1 1

28 PIN 11 digital Input 1 1 1 0 0

29 PIN 12 digital Input 1 1 1 0 1

30 PIN 13 digital Input 1 1 1 1 0

31 VDD 1 1 1 1 1

8.2 Matrix Output Table

Table 14. Matrix Output Table

9.0 Combinatorial Logic

Combinatorial logic is supported via four Lookup Tables (LUTs) within the SLG46117. There are two 2-bit LUTs and two 3-bit LUTs. 10.0 Combination Function Macrocells. devices (AND, NAND, OR, NOR, XOR, XNOR). created within each of the two 2-bit LUT logic cells. Figure 7. 2-bit LUTs Table 17. 2-bit LUT2/LUT3 Standard Digital Functions. Table 15. 2-bit LUT2 Truth Table. Table 16. 2-bit LUT3 Truth Table.

Figure 8. 3-bit LUTs Table 18. 3-bit LUT2 Truth Table. Table 19. 3-bit LUT3 Truth Table.

created within each of the two 3-bit LUT logic cells. Table 20. 3-bit LUT2/LUT3 Standard Digital Functions.

10.0 Combination Function Macrocells

Two macrocells that can serve as either 2-bit LUTs or as D Flip-Flops.
Two macrocells that can serve as either 3-bit LUTs or as D Flip-Flops.
One macrocell that can serve as either 3-bit LUT o r as Pipe Delay
One macrocells that can serve as either 4-bit LUTs or as 8-Bit Counter / Delays Inputs/Outputs for the six combination function macrocells are configured from the connection matrix with specific logic functions being defined by the state of NVM bits. When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR). When used as a D Flip-Flop / Latch, the source and destination of the inputs and outputs for the DFF/Latches are configured from the connection matrix. All DFF/Latch macrocells have user selection for initial state, and all have th e option to connect both the Q and Q Bar outputs to the connection matrix. The m acrocells DFF2, DFF3 have an additional input from the matrix that can serve as a nSet or nReset function to the macrocell. The operation of the D Flip-Flop and Latch will follow the functional descriptions below: DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change Latch: if CLK = 0, then Q = D 10.1 2-Bit LUT or D Flip-Flop Macrocells There are two macrocells that can serve as either 2-bit LUTs or as D Flip-Flops. When used to implement LUT functions, the 2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the connection matrix. When used to implement D Flip-Flop function, the two input signals from the connection matrix go to the data (d) and clock (clk) inputs for the Flip-Flop, with the output going back to the connection matrix.

Figure 9. 2-bit LUT0 or DFF0

Figure 10. 2-bit LUT1 or DFF1 Table 21. 2-bit LUT0 Truth Table. Table 22. 2-bit LUT1 Truth Table.

Table 23. DFF0 Register Settings Table 24. DFF1Register Settings

Table 25. 3-bit LUT0 Truth Table. Table 26. 3-bit LUT1 Truth Table.

Table 27. DFF2 Register Settings Table 28. DFF3 Register Settings

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay. output, which goes back into the connection matrix. When used as an 8-stage pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK) and Reset (RST). reg <666:663> for OUT0 and reg <670:667> for OUT1. The 3-input mux is used to control the selection of the amount of delay. be the total time delay of the Pipe Delay logic cell. Figure 13. 3-bit LUT4 or Pipe Delay

8 Flip-Flops IN

Table 30. Pipe Delay Register Settings Table 29. 3-bit LUT4 Truth Table.

external clock (ext_clk) and reset (DLY_n/CNT_Reset) for the counter/delay, with the output going back to the connection matrix. Note: Counters initialize with counter data=0 after POR. Figure 14. 4-bit LUT0 or CNT/DLY2

Table 31. 4-bit LUT0 Truth Table.

Table 32. CNT/DLY2 Register Settings

11.0 Analog Comparators (ACMP)

a digital signal coming from the Connection Matrix. When ACMP is powered down, output is low. either created from an internal VREF or provided by way of the external sources. also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV or 200 mV. During powerup, the ACMP output will remain low, and then become valid 110 µs (max) after POR signal goes high, see Figure 15 . Note: Regulator and Charge Pump set to automatic ON/OFF. use Vref selection VDD/4 and VDD/3 to maintain this input range. Figure 15. Maximum Power On Delay vs. VDD. Table 33. Gain Divider Input Resistance (typ). Table 34. Gain Divider Accuracy.

reference/source. Internal Vref accuracy is optimized near 1000 mV selection. Note: Power supply control options have influence on the ACMP operation. Force BandGap option is set as Disabled).

Hysteresis: Input signal hysteresis options are Di sable, 25 mV, 50 mV, 200 mV.
Low Bandwidth: Enable, Disable;
IN+ Gain: 1X, 0.5X, 0.33X, 0.25X;
IN+ source:
ACMP0 IN+ options are PIN 3, VDD;
ACMP1 IN+ options are PIN 6, ACMP0 IN+;
IN- source:
ACMP0 IN- options are 24 internal reference sources (50 mV – 1200 mV) and VDD/3, VDD/4, PIN 4;
PWR UP=0 – ACMP is powered down; PWR UP=1 – ACMP is powered up. All ACMPs can have a common negative input. This can be achieved by configuring ACMP0 PIN 4 analog I/O connection.

11.1 ACMP0 Block Diagram

Figure 16. ACMP0 Block Diagram

11.2 ACMP0 Register Settings

Table 35. ACMP0 Register Settings

11.3 ACMP1 Block Diagram

Figure 17. ACMP1 Block Diagram

11.4 ACMP1 Register Settings

Table 36. ACMP1 Register Settings

11.5 Typical Performance Characteristics

Note: when VDD < 1.8V voltage reference should not exceed 1100 mV. Figure 18. Typical Input Voltage Offset vs. Voltage Reference at room temperature, LBW Mode – Disable, Vhys=0 mV, VDD=(1.7 – 5.5) V. Figure 19. Typical Input Threshold Variation (including Vref variation, ACMP offset) vs. Voltage reference at room temperature, LBW Mode – Disable, Vhys=0 mV.

11.6 Timing Characteristics

Figure 24. Maximum Propagation Delay Low-to-High Figure 25. Maximum Propagation Delay Low-to-High

1100 E (mV)

Figure 26. Maximum Propagation Delay High-to-Low Figure 27. Maximum Propagation Delay High-to-Low

Figure 28. Maximum Propagation Delay Low-to-High Figure 29. Maximum Propagation Delay Low-to-High Figure 30. Maximum Propagation Delay High-to-Low Figure 31. Maximum Propagation Delay High-to-Low

12.0 Counters/Delay Generators (CNT/DLY)

option to chain from the output of the previous (N-1) CNT/DLY macrocell, to implement longer count / delay circuits. more information please see Section 10.4 4-Bit LUT or 8- Bit Counter / Delay Macrocells. Note: Counters initialize with counter data=0 after POR. Figure 32. CNT/DLY0

12.1 CNT/DLY0 Register Settings

12.2 CNT/DLY1 Register Settings

Table 38. CNT/DLY0 Register Settings Table 39. CNT/DLY1 Register Settings

12.3 CNT/DLY3 Register Settings

Table 40. CNT/DLY3 Register Settings

13.0 Programmable Delay / Edge Detector

period. See the timing diagrams below for further information. Note : The input signal must be longer than the delay, otherwise it will be filtered out.

13.1 Programmable Delay Timing Diagram - Edge Detector Output

Figure 35. Programmable Delay Figure 36. Edge Detector Output

Note: For delays and widths refer to Table 4 . Figure 37. Delayed Edge Detector Output

13.2 Programmable Delay Register Settings

Table 41. Programmable Delay Register Settings

14.0 Additional Logic Functions

14.1 Deglitch Filter

Figure 38. Deglitch Filter

15.0 Voltage Reference (VREF)

15.1 Voltage Reference Overview

15.2 VREF Selection Table

Table 42. VREF Selection Table.

11001 VDD / 4 VDD / 4

11000 VDD / 3 VDD / 3

15.3 VREF Block Diagram

Figure 39. Voltage Reference Block Diagram

16.0 RC Oscillator (RC Osc)

16.1 RC Oscillator Overview

Note: RC OSC power setting: "Auto Power On”. Figure 40. Maximum Power On Delay vs. VDD, RC OSC = 2 MHz. Figure 41. Maximum Power On Delay vs. VDD, RC OSC = 25 kHz.

will be turned off. The PWR DOWN signal has the highest priority.

16.2 RC OSC Block Diagram

Figure 42. RC OSC Block Diagram

000-0046117-113 Page 69 of 89 SLG46117

17.0 Power On Rest (POR)

The SLG46117 has a power-on reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first ramping to the device, and also while the VDD is falling during power-down. To accomplish this goal, the POR drives a defined sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of the I/O pins. This application note is created to explain the whole process of POR operation and GreenPAK chip behavior during the time while it is powering up and powering down.

17.1 General Operation

The SLG46117 is guaranteed to be powered down and nonoperational when the VDD voltage (on PIN14) is less than 0.6 V, but not less than -0.6 V. Another essential condition for the chip to be powered down is that no voltage higher (see Note 1) than the VDD voltage is applied to any other PIN. For exampl e, if VDD voltage is 0.3V, applying a voltage higher than 0.3V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior. Note 1. There is a 0.6V margin due to forward drop voltage of the ESD protection diodes. To start the POR sequence in the SLG46117, the volt age applied on the VDD should be higher than the Po wer_ON threshold voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power_ON threshold. After the POR sequence has started, the SLG46117 will have a typical period of time to go through all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after the POR sequence is complete. Note 2. The Power_ON threshold can vary by PVT, but typically it is 1.6V. To power down the chip the VDD voltage should be lo wer than the operational and to guarantee that chip is powered down it should be less than 0.6V. All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step in the POR sequence releases the I/O structures from the high impedance state, at which time the device is operational. The pin configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.

17.2 POR Sequence

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 43 . environmental factors, such as: slew rate, VDD value, temperature and even will vary from chip to chip (process influence). Figure 43. POR sequence

17.3 Macrocells Output States During POR Sequence

states during the POR sequence ( Figure 44 describes the output signals states). last are output PINs that become active and determined by the input signals. Figure 44. Internal Macrocell States during POR sequence

18.0 Soft-Start P-FET Power Switch with Fixed Slew Rate Control and Integrated Discharge Resistor

allowing the user to generate integrated mixed-signal control circuits, or externally via PWR_SW_ON (PIN 4). When configured to be controlled internally, PWR_SW_ON (PIN 4) is configured as a Push-Pull output. as an input to other integrated components. Switch while the device is not powered. Note: To prevent glitches at the output, it is recommended to connect at least 0.1 µF capacitor from VOUT pin to the GND . Figure 45. P-FET Power Switch with Slew Rate Control

000-0046117-113 Page 73 of 89 SLG46117

19.0 Appendix A - SLG46117 Register Definition

Address Signal Function Register Bit Definition reg <4:0> Matrix Out: PIN 2 Digital Output Source reg <9:5> Matrix Out: PIN 3 Digital Output Source reg <14:10> Matrix Out: PIN 4 Digital Output Source reg <19:15> Matrix Out: Output Enable of PIN 4 and ON input of P-FET Power Switch reg <24:20> Matrix Out: In0 of LUT2_0 or Clock Input of DFF0 reg <29:25> Matrix Out: In1 of LUT2_0 or Data Input of DFF0 reg <34:30> Matrix Out: In0 of LUT2_1 or Clock Input of DFF1 reg <39:35> Matrix Out: In1 of LUT2_1 or Data Input of DFF1 reg <44:40> Matrix Out: In0 of LUT2_2 reg <49:45> Matrix Out: In1 of LUT2_2 reg <54:50> Matrix Out: In0 of LUT2_3 reg <59:55> Matrix Out: In1 of LUT2_3 reg <64:60> Matrix Out: In0 of LUT3_0 or Clock Input of DFF2 reg <69:65> Matrix Out: In1 of LUT3_0 or Data Input of DFF2 reg <74:70> Matrix Out: In2 of LUT3_0 or Resetb Inpu t of DFF2 reg <79:75> Matrix Out: In0 of LUT3_1 or Clock Input of DFF3 reg <84:80> Matrix Out: In1 of LUT3_1 or Data Input of DFF3 reg <89:85> Matrix Out: In2 of LUT3_1 or Resetb(Setb ) of DFF3 reg <94:90> Matrix Out: In0 of LUT3_2 reg <99:95> Matrix Out: In1 of LUT3_2 reg <104:100> Matrix Out: In2 of LUT3_2 reg <109:105> Matrix Out: In0 of LUT3_3 reg <114:110> Matrix Out: In1 of LUT3_3 reg <119:115> Matrix Out: In2 of LUT3_3 reg <124:120> Matrix Out: In0 of LUT3_4 or Input of Pipe delay reg <129:125> Matrix Out: In1 of LUT3_4 or Resetb of Pipe delay reg <134:130> Matrix Out: In2 of LUT3_4 or Clock of Pipe delay reg <139:135> Matrix Out: In0 of LUT4_0 or Input for delay2 (Counter2) external clock reg <144:140> Matrix Out: In1 of LUT4_0 or Input for delay2 data (counter2 reset) reg <149:145> Matrix Out: In2 of LUT4_0 reg <154:150> Matrix Out: In3 of LUT4_0 reg <159:155> Matrix Out: Input for delay0 data (cou nter0 reset) reg <164:160> Matrix Out: Input for delay1 data (cou nter1 reset) reg <169:165> Matrix Out: Input for delay0/1 (Counter0/1) external clock reg <174:170> Matrix Out: Input for delay3 (Counter3 ) external clock reg <179:175> Matrix Out: pdb(power down) for ACMP0 reg <184:180> Matrix Out: pdb(power down) for ACMP1 reg <189:185> Matrix Out: Input for programmable delay (deglitch filter input)

000-0046117-113 Page 74 of 89 SLG46117 reg <194:190> Matrix Out: Power down for osc reg <199:195> Matrix Out: PIN 10 Digital Output Sour ce reg <204:200> Matrix Out: PIN 11 Digital Output Sour ce reg <209:205> Matrix Out: PIN 12 Digital Output Sour ce reg <214:210> Matrix Out: Output Enable of PIN 12 reg <219:215> Matrix Out: PIN 13 Digital Output Sour ce reg <223:220> Reserved Reserved DFF0/Latch reg <227:224> reg <224> DFF0 or Latch select 0: DFF function 1: Latch function reg <225> DFF0 output select 0: Q output 1: nQ output reg <226> DFF0 initial polarity select 0: Low 1: High reg <227> Unused if DFF/Latch selected Unused DFF1/Latch reg <231:228> reg <228> DFF1 or Latch select 0: DFF function 1:Latch function reg <229> DFF1 output select 0: Q output 1: nQ output reg <230> DFF1 initial polarity select 0: Low 1:High reg <231> Unused if DFF/Latch selected Unused LUT2_0 data reg <235:232> LUT2_0 data LUT2_0 data LUT2_1 data reg <239:236> LUT2_1 data LUT2_1 data LUT2_0/DFF0 reg <240> LUT2_0 or DFF0 select 0: LUT2_0 1: DFF0 LUT2_1/DFF1 reg <241> LUT2_1 or DFF1 select 0: LUT2_1 1: DFF1 LUT3_0 or DFF2/Latch reg <249:242> reg <242> DFF2 or Latch select 0: DFF function 1: Latch function reg <243> DFF2 output select 0: Q output 1: nQ output reg <244> DFF2 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg <245> DFF2 initial polarity select 0: Low 1: High reg <249:246> Unused if DFF/Latch selected Unused Register Bit Address Signal Function Register Bit Definition

000-0046117-113 Page 75 of 89 SLG46117 DFF3/Latch reg <257:250> reg <250> DFF3 or Latch select 0: DFF function 1: Latch function reg <251> DFF3 output select 0: Q output 1: nQ output 0: Q output 1: nQ output reg <252> DFF3 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg <253> DFF3 initial polarity select 0: Low 1: High reg <257:254> Unused if DFF/Latch selected Unused LUT3_2 data reg <265:258> LUT3_2 data LUT3_2 data LUT3_3 data reg <273:266> LUT3_3 data LUT3_3 data LUT3_4 or pipe number select reg <281:274> reg <276:274>: OUT0 select data (pipe number) reg <279:277>: OUT1 select data (pipe number) reg <281:280>: Unused if Pipe Delay selected Unused LUT3/DFF Select reg <282> LUT3_0 or DFF2 select 0: LUT3_0 1: DFF2 reg <283> LUT3_1 or DFF3 select 0: LUT3_1 1: DFF3 reg <284> LUT3_4 or pipe delay output select 0: LUT3_4 1: pipe delay LUT4_0 or Counter/delay2 mode selection reg <300:285> reg <285> Counter/delay2 mode selection 0: Delay Mode 1: Counter Mode reg <288:286> Counter/delay2 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter1 Overflow reg <296:289> Counter/delay2 Control Data 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg <298:297> Delay2 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for delay & counter reset) 01: Delay on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: No delay on either falling or rising edges / high level reset for counter mode reg <300:299> Unused is Counter/Delay2 selected Unus ed reg <301> LUT4_0 or Counter2 select 0: LUT4_0, 1: Co unter2 0: LUT4_0 1: Counter2 Register Bit Address Signal Function Register Bit Definition

000-0046117-113 Page 76 of 89 SLG46117 reg <302> Force RC oscillator on 0: Auto Power on 1: Force Power on reg <303> RC Oscillator frequency control 0: 25k 1: 2M reg <305:304> Osc clock pre-divider 00: div1 01: div2 10: div4 11: div8 reg <308:306> Internal Oscillator frequency divider control 0 for Matrix Input 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 reg <311:309> Internal Oscillator frequency divider control 1 for Matrix Input 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 reg <312> External Clock Source Select 0: Internal Oscillator 1: External Clock from PIN 13 reg <313> Reserved Reserved Counter/Delay 0 reg <327:314> reg <314>Counter/delay0 mode selection 0: Delay Mode 1: Counter Mode reg <317:315> Counter/delay0 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter3 Overflow reg <325:318> Counter0 Control Data/Delay0 Time Control 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg <327:326> Delay0 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for delay & counter reset) 01: Delay on falling edge only (for delay & counter reset) 10: Delay on rising edge only (for delay & counter reset) 11: No delay on either falling or rising edges / high level reset for counter mode Register Bit Address Signal Function Register Bit Definition

000-0046117-113 Page 77 of 89 SLG46117 Counter/Delay 1 reg <341:328> reg <328> Counter/delay1 mode selection 0: Delay Mode 1: Counter Mode reg <331:329> Counter/delay1 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter0 Overflow reg <339:332> Counter1 Control Data/Delay1 Time Control 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg <341:340> Delay1 Mode Select or asynchronous counter reset 00: Delay on both falling and rising foresighted delay & counter reset) 01: Delay on falling edge only (for delay & counter reset) 10: Delay on rising edge only (for delay & counter reset) 11: No delay on either falling or rising edges / high level reset for counter mode Counter/Delay 3 reg <355:342> reg <342> Counter/delay3 mode selection 0: Delay Mode 1: Counter Mode reg <345:343> Counter/delay3 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter2 Overflow reg <353:346> Counter3 Control Data/Delay4 Time Control 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg <355:354> Delay3 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges Register Bit Address Signal Function Register Bit Definition

000-0046117-113 Page 78 of 89 SLG46117 ACMP0 reg <366:356> reg <360:356> ACMP0 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: EXT_VREF(PIN 3) reg <362:361> ACMP0 hysteresis Enable 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) reg <364:363> ACMP0 positive Input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x reg <365> ACMP0 low bandwidth (typ: Max.1Mhz) en - able. 0: off 1: on reg <366> ACMP0 positive input source select PIN 2 and VDD 0: PIN 2 1: VDD ACMP1 reg <378:367> reg <371:367> ACMP1 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: EXT_VREF(PIN 3) reg <373:372> ACMP1 hysteresis Enable 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) reg <375:374> ACMP1 positive Input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x reg <376> ACMP1 100uA current source option 0: disable 1: enable reg <377> ACMP1 low bandwidth (typ: Max.1 MHz) en - able. 0: off 1: on Reserved Register Bit Address Signal Function Register Bit Definition

000-0046117-113 Page 79 of 89 SLG46117 PIN 1 reg <382:379> reg <380:379> PIN 1 mode control 00: Digital Input without Schmitt trigger 01: Digital Input with Schmitt trigger 10: Low voltage digital input 11: Reserved reg <382:381> PIN 1 pull down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M PIN 2 reg <389:383> reg <385:383> PIN 2 mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Analog Input / Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input / Output & Open drain reg <387:386> PIN 2 pull up/down resistor value selec - tion 00: floating 01: 10K 10: 100K 11: 1M reg <388> PIN 2 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <389> PIN 2 driver strength selection 0: 1X 1: 2X PIN 3 reg <396:390> reg <392:390> PIN 3 mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Analog Input / Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input / Output & Open drain reg <394:393> PIN 3 pull up/down resistor value selec - tion 00: floating 01: 10K 10: 100K 11: 1M reg <395> PIN 3 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <396> PIN 3 driver strength selection 0: 1X 1: 2X Register Bit Address Signal Function Register Bit Definition

000-0046117-113 Page 80 of 89 SLG46117 PIN 4 reg <403:397> reg <398:397> PIN 4 mode control (sig_PIN 4_oe =0) 00: Digital Input without Schmitt trigger 01: Digital Input with Schmitt trigger 11: Low Voltage Digital Input 10: Analog Input / Output reg <400:399> PIN 4 mode control (sig_PIN 4_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg <402:401> PIN 4 pull up/down resistor value selec - tion 00: floating 01: 10K 10: 100K 11: 1M reg <403> PIN 4 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable PIN 10 reg <410:404> reg <406:404> PIN 10 mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Analog Input / Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input / Output & Open drain reg <408:407> PIN 10 pull up/down resistor value se- lection 00: floating 01: 10K 10: 100K 11: 1M reg <409> PIN 10 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <410> PIN 10 driver strength selection 0: 1X 1: 2X PIN 11 reg <417:411> reg <413:411> PIN 11 mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Analog Input / Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input / Output & Open drain reg <415:414> PIN 11 pull down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M reg <416> PIN 11 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <417> PIN 11 driver strength selection 0: 1X 1: 2X Register Bit Address Signal Function Register Bit Definition

000-0046117-113 Page 81 of 89 SLG46117 PIN 12 reg <424:418> reg <419:418> PIN 12 mode control (sig_PIN 12_oe =0) 00: Digital Input without Schmitt trigger 01: Digital Input with Schmitt trigger 11: Low Voltage Digital Input 10: Analog Input / Output reg <421:420> PIN 12 mode control (sig_PIN 12_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg <423:422> PIN 12 pull up/down resistor value se- lection 00: floating 01: 10K 10: 100K 11: 1M reg <424> PIN 12 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable PIN 13 reg <431:425> reg <427:425> PIN 13 mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Analog Input / Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input / Output & Open drain reg <429:428> PIN 13 pull up/down resistor value se- lection 00: floating 01: 10K 10: 100K 11: 1M reg <430> PIN 13 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <431> PIN 13 driver strength selection 0: 1X 1: 2X reg <432> Pipe delay OUT1 polarity select bit 0: non-inverting 1: inverting reg <440:433> 8-bit pattern id 8-bit pattern id reg <441> filter0 output polarity select 0: non-inverting 1: inverting reg <443:442> Reserved Reserved reg <444> GPIO quick charge enable 0: Disable 1: Enable reg <445> Force bandgap on 0: Auto-mode 1: Enable reg <446> VREF1 Output Active Buffer Control 0: Disabled 1: Enabled reg <449:447> VREF1 Output Source Select 000: ACMP0 reference voltage 001: ACMP1 reference voltage 100: VDD/2 101: VDD/3 110: VDD/4 101: Reserved 110: Reserved 111: Reserved Register Bit Address Signal Function Register Bit Definition

000-0046117-113 Page 82 of 89 SLG46117 reg <450> NVM data read disable 0: Disable (read enable) 1: Enable (read disable) reg <451> NVM power down (or NVM data programming di sable) 0: None (or programming enable) 1: Power Down (or programming disable) reg <452> Power Divider Power 0: Power down 1: Power On reg <453> POR Auto Power detect 0: Enable 1: Disable reg <454> Charge pump for analog macrocell enable (when VDD <= 2.7 V turn on) 0: Disable (automatic on/off control) 1: Enable (always on) reg <455> VDD bypass enable 0: Regulator auto on 1: Regulator off (VDD bypass) reg <471:456> Reserved Reserved reg <479:472> Reserved Reserved reg <481:480> Reserved Reserved reg <482> PIN 1 edge detect mode 0: rising edge 1: falling edge reg <483> Bypass the PIN 1 0: PIN 1 edge active 1: PIN 1 high active reg <484> PIN 1 reset enable 0: Disable 1: Enable reg <485> programmable delay or filter output selec t 0: programmable delay output 1: filter output reg <487:486> Select the edge mode of programmable delay & edge detector 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay reg <489:488> Delay value select for programmable delay & edge de- tector (VDD = 3.3 V, typical condition) 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns reg <490> Reserved Reserved reg <495:491> Reserved Reserved reg <501:496> Reserved Reserved reg <502> Reserved Reserved reg <503> Reserved Reserved reg <511:504> Reserved Reserved Register Bit Address Signal Function Register Bit Definition

000-0046117-113 Page 83 of 89 SLG46117

20.0 Package Top Marking System Definition

+ Serial Number Code ARR Assembly House Code + Revision Code

000-0046117-113 Page 84 of 89 SLG46117

21.0 Package Drawing and Dimensions

14 Lead STQFN Package 1.6 x 2.5 mm JEDEC MO-252 IC Net Weight: 0.059 g

000-0046117-113 Page 85 of 89 SLG46117

22.0 Tape and Reel Specifications

23.0 Carrier Tape Drawing and Dimensions Package Type # of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 14L 1.6x2.5mm FC 0.4P Green 14 1.6x2.5x0.55 3000 3000 178/60 100 400 100 400 8 4 Package Type Pocket BTM Length [mm] Pocket BTM Width [mm] Pocket Depth [mm] Index Hole Pitch [mm] Pocket Pitch [mm] Index Hole Diameter [mm] Index Hole to Tape Edge [mm] Index Hole to Pocket Center [mm] Tape Width [mm] A0 B0 K0 P0 P1 D0 E F W STQFN 14L 1.6x2.5mm FC 0.4P Green

000-0046117-113 Page 86 of 89 SLG46117

24.0 Recommended Landing Pattern

25.0 Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 2.2 mm 3 (nominal). More information can be found at www.jedec.org.

000-0046117-113 Page 87 of 89 SLG46117

26.0 Revision History

3/4/2022 1.13 Added R PUP and R PDWN in section Electrical Specifications Renesas rebranding 10/21/2021 1.12 Updated tables CNT/DLY Register Settings Corrected registers [296:289], [325:318], [339:332], [353:346] in Appendix A - SLG46117 Register Definition Added VIN to Abs Max table Updated Abs Max Table Parameters for clarity Updated IDS conditions and spec Updated SOA Graph accuracy 4/22/2021 1.11 Updated Package Drawing and Dimensions Added note for CNTs Corrected registers [353:343], [339:329], [325:315], [296:286] 10/29/2019 1.10 Updated last page with disclaimer and contacts Added pre front page Fixed typos 10/10/2017 1.09 Updated Electrical Spec Fixed typos Updated POR sequence 7/5/2017 1.08 Updated Electrical Spec 10/20/2016 1.07 Fixed typos Removed references to GPAK families 6/22/2016 1.06 Updated P-FET section 5/27/2016 1.05 Updated Silego Website & Support Updated Programmable Delay information Updated Programmable Delay information Added PON THR and POFF THR in Electrical Spec 12/1/2015 1.04 Corrected Appendix A 10/29/2015 1.03 Updated text for clarity Fixed typos Updated Absolute maximum conditions 6/17/2015 1.02 Increased to support 1.25 A 6/3/2015 1.01 Fixed 3.3 V Electrical Specifications 5/26/2015 1.0 Production Release 5/21/2015 0.62 Updated ACMP Diagrams and added Timing Characteristics Diagrams 4/28/2015 0.61 Updated RC Oscillator section 4/24/2015 0.60 Updated ACMP section 4/9/2015 0.59 Updated Tsu condition and value 3/10/2015 0.58 Added Connection Matrix Example 3/9/2015 0.57 Added POR section 2/10/2015 0.56 Updated General Description 1/14/2015 0.55 Added IDD Estimator, Timing Estimator, Expected Delays sections 12/3/2014 0.54 Updated Electrical Characteristics VIH /VIL/VOH/VOL values 10/14/2014 0.53 Updated ACMP1 Block to remove PIN 4 a s analog input 9/3/2014 0.52 Updated Electrical Characteristics VIH/ VIL/VOH/VOL values 7/29/2014 0.51 Fixed Programming Pin Descriptions and Pin 8 name 7/23/2014 0.5 Added ESD information Preliminary Release 7/18/2014 0.24 Added Soft-Start to describe P-FET

000-0046117-113 Page 88 of 89 SLG46117 6/19/2014 0.23 Added Load to P-FET Power Switch diagr am 6/2/2014 0.22 Updated P-FET Power Switch diagram 4/18/2014 0.21 Updated P-FET Power Switch section 4/15/2014 0.2 Added Electrical Characteristics and Fu nction Descriptions 2/3/2014 0.1 Initial release Date Version Change

000-0046117-113 Page 89 of 89 SLG46117 RoHS Compliance Renesas Electronics Corporation’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous sub stances in electrical and electronic equipment. RoH S certificates from our suppliers are available on request.

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) © 2021 Renesas Electronics Corporation. All rights reserved.

Selected Specification

Renesas Technology Corp SLG46117VTR overview.

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Summary

Programmable Mixed-signal Matrix with P-FET Power Switch with Discharge Revised March 4, 2022

Description

Programmable Mixed-signal Matrix with P-FET Power Switch with Discharge Revised March 4, 2022

Source title SLG46117VTR Datasheet(PDF) - Renesas Technology Corp

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