SLG46110VTR

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Programmable Mixed Signal Matrix March 9, 2023

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SLG46110 RENESAS

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 84

Technical content

Features

Logic & Mixed Signal Circuits
Highly Versatile Macrocells
1.8 V (±5%) to 5 V (±10%) Supply
Operating Temperature Range: -40°C to 85°C
RoHS Compliant / Halogen-Free
Pb-Free 12-pin STQFN: 1.6 x 1.6 x 0.55 mm, 0.4 mm pitch

Applications

Personal Computers and Servers
PC Peripherals
Consumer Electronics
Data Communications Equipment
Handheld and Portable Electronics Pin Configuration GND GPIO GPIO GPIO GPIO GPIO 4 7 GPI VDD 1 STQFN-12 (Top View) GPIO NC 5 6 GPIO NC 11 12 3-bit LUT3_4 or Pipe Delay Vref RC Oscillator Pin 1 VDD Pin 2 GPI Pin 3 GPIO Pin 4 GPIO Pin 12 GPIO Pin 11 NC Pin 5 NC Pin 6 GPIO Pin 8 GPIO Pin 7 GND Pin 10 GPIO Pin 9 GPIO ACMP0 ACMP1 Look Up Tables (LUTs) Counters/Delay Generators CNT0 CNT3 CNT1 2-bit LUT2_2 3-bit LUT3_3 2-bit LUT2_3 3-bit LUT3_2 Combination Function Macrocells 2-bit LUT2_0 or DFF0 2-bit LUT2_1 or DFF1 3-bit LUT3_1 or DFF3 3bit LUT3_0 or DFF2 4-bit LUT4_0 or CNT2 FILTER_0/Prog. Delay Additional Combination Functions POR Bandgap

1.0 Overview

The SLG46110 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Mem ory (NVM) to configure the interconnect logic, the I/O Pins and the macrocells of the SLG46110. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The macrocells in the device include the following:

Two Analog Comparators (ACMP)
Voltage References (Vref)
Four Combinatorial Look Up Tables (LUTs)
Two 2-bit LUTs
Two 3-bit LUTs
Seven Combination Function Macrocell
Two Selectable DFF/Latch or 2-bit LUTs
Two Selectable DFF/Latch or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
Pipe Delay – 8 stage / 2 output
One Selectable Counter/Delay or 4-bit LUT
One Programmable Delay / Deglitch Filter
Three Counter / Delay Generators (CNT/DLY)
Three 8-bit counter/delays with external clock/reset
Four D Flip-Flop / Latches (DFF) (Part of Combinat ion Function Macrocell)
Pipe Delay – 8 stage/2 output (Part of Combination Function Macrocell)
One Bandgap
RC Oscillator (RC OSC)
Power On Reset (POR)

2.0 Pin Description

2.1 Functional and Programming Pin Description

Pin # Pin Name Function Programming Function

1 VDD Power Supply Power Supply

2 GPI General Purpose Input VPP (Programming Voltage)

3 GPIO General Purpose I/O or Analog Comparator 0 (+) Programming ID Pin

4 GPIO General Purpose I/O or Analog Comparator 0 (-) N/A

5 NC No Connect N/A

6 GPIO General Purpose I/O or Analog Comparator 1 (+) with OE N/A

7 GND Ground N/A

8 GPIO General Purpose I/O Programming Mode Control

9 GPIO General Purpose I/O Programming SDIO Pin

10 GPIO General Purpose I/O with OE and Vref output P rogramming SRDWB Pin

11 NC No Connect N/A

12 GPIO General Purpose I/O or External Clock Input Pr ogramming SCL Pin

3.0 User Programmability

as it remains powered and can be re-written as needed to facilitate rapid design changes. Figure 1. Steps to create a custom GreenPAK device

4.0 Ordering Information

Note 1: Use SLG46110V to order. Shipments are automatically in Tape and Reel. Note 2: “TR” suffix is no longer used. It is a legacy naming convention shown here only for informational purposes. Part Number Type SLG46110V 12-pin STQFN SLG46110VTR 12-pin STQFN - Tape and Reel (3k units)

5.0 Electrical Specifications

5.1 Absolute Maximum Conditions

5.2 Electrical Characteristics (1.8V ±5% V DD ) Parameter Min. Max. Unit Supply voltage on VDD relative to GND -0.5 7 V DC Input voltage GND - 0.5 VDD + 0.5 V Maximum Average or DC Current (Through pin) Push-Pull 1x -- 12 mA Push-Pull 2x -- 17 OD 1x -- 18 OD 2x -- 28 Current at Input Pin -1.0 1.0 mA Storage Temperature Range -65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1000 -- V Moisture Sensitivity Level 1 Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 1.71 1.80 1.89 V IQ Quiescent Current Static Inputs and Outputs (when ACMP , Vref and OSC are powered down and non-operational) -- 0.5 -- µA T A Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VAIR Analog Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.1 V VIH HIGH-Level Input Voltage Logic Input 1.100 -- V DD V Logic Input with Schmitt Trigger 1.270 -- V DD V Low-Level Logic Input 0.980 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 0.690 V Logic Input with Schmitt Trigger -- -- 0.440 V Low-Level Logic Input -- -- 0.520 V I IH HIGH-Level Input Current Logic Input Pins; V IN = 1.8 V -1.0 -- 1.0 µA IIL LOW-Level Input Current Logic Input Pins; V IN = 0 V -1.0 -- 1.0 µA VOH HIGH-Level Output Voltage Push-Pull 1X, Open Drain PMOS 1X, I OH = 100 µA 1.680 1.790 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 100 µA 1.702 1.800 -- V

© 2023 Renesas Electronics Corporation Page 6 of 82 SLG46110 Revision 1.12 VOL LOW-Level Output Voltage Push-Pull 1X, I OL = 100 µA -- 0.020 0.030 V Push-Pull 2X, I OL = 100 µA -- 0.010 0.020 V Open Drain NMOS 1X, I OL = 100 µA -- 0.010 0.020 V Open Drain NMOS 2X, I OL = 100 µA -- 0.010 0.010 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, V OH = V DD - 0.2 1.040 1.400 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = V DD - 0.2 2.150 2.710 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, V OL = 0.15 V 0.760 1.340 -- mA Push-Pull 2X, V OL = 0.15 V 1.520 2.660 -- mA Open Drain NMOS 1X, V OL = 0.15 V 1.530 2.670 -- mA Open Drain NMOS 2X, V OL = 0.15 V 3.060 5.130 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T TSU Startup Time from VDD rising past 1.35 V -- 0.27 -- ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.182 1.346 1.505 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.752 0.918 1.110 V RPUP Pull Up Resistance

1 M Pull Up -- 1 -- M Ω

100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance

1 M Pull Down -- 1 -- M Ω

100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

© 2023 Renesas Electronics Corporation Page 7 of 82 SLG46110 Revision 1.12 5.3 Electrical Characteristics (3.3V ±10% V DD ) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3.0 3.3 3.6 V IQ Quiescent Current Static Inputs and Outputs (when ACMP , Vref and OSC are powered down and non-operational) -- 0.75 -- µA T A Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VAIR Analog Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 1.780 -- V DD V Logic Input with Schmitt Trigger 2.130 -- V DD V Low-Level Logic Input 1.130 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 1.210 V Logic Input with Schmitt Trigger -- -- 0.950 V Low-Level Logic Input -- -- 0.690 V I IH HIGH-Level Input Current Logic Input Pins; V IN = 3.3 V -1.0 -- 1.0 µA IIL LOW-Level Input Current Logic Input Pins; V IN = 0 V -1.0 -- 1.0 µA VOH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, I OH = 3 mA 2.710 3.090 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 3 mA 2.870 3.190 -- V VOL LOW-Level Output Voltage Push-Pull 1X, I OL = 3 mA -- 0.180 0.280 V Push-Pull 2X, I OL = 3 mA -- 0.090 0.130 V Open Drain NMOS 1X, I OL = 3 mA -- 0.090 0.130 V Open Drain NMOS 2X, I OL = 3 mA -- 0.050 0.070 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, V OH = 2.4 V 5.830 10.180 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = 2.4 V 11.264 19.660 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, V OL = 0.4 V 4.060 6.440 -- mA Push-Pull 2X, V OL = 0.4 V 8.130 12.360 -- mA Open Drain NMOS 1X, V OL = 0.4 V 8.130 12.410 -- mA Open Drain NMOS 2X, V OL = 0.4 V 16.260 22.900 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T

5.4 Electrical Characteristics (5V ±10% V DD )

TSU Startup Time from VDD rising past 1.35 V -- 0.27 -- ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.182 1.346 1.505 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.752 0.918 1.110 V RPUP Pull Up Resistance 100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance 100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V IQ Quiescent Current Static Inputs and Outputs (when ACMP , Vref and OSC are powered down and non-operational) -- 1.0 -- µA T A Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VAIR Analog Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 2.640 -- V DD V Logic Input with Schmitt Trigger 3.160 -- V DD V Low-Level Logic Input 1.230 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 1.840 V Logic Input with Schmitt Trigger -- -- 1.510 V Low-Level Logic Input -- -- 0.780 V I IH HIGH-Level Input Current Logic Input Pins; V IN = 5 V -1.0 -- 1.0 µA IIL LOW-Level Input Current Logic Input Pins; V IN = 0 V -1.0 -- 1.0 µA VOH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, I OH = 5 mA 4.150 4.730 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 5 mA 4.300 4.860 -- V VOL LOW-Level Output Voltage Push-Pull 1X, I OL = 5 mA -- 0.230 0.330 V Push-Pull 2X, I OL = 5 mA -- 0.120 0.160 V Open Drain NMOS 1X, I OL = 5 mA -- 0.120 0.160 V Open Drain NMOS 2X, I OL = 5 mA -- 0.070 0.090 V Symbol Parameter Condition/Note Min. Typ. Max. Unit

© 2023 Renesas Electronics Corporation Page 9 of 82 SLG46110 Revision 1.12 IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, V OH = 2.4 V 21.808 29.100 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = 2.4 V 40.598 56.080 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, V OL = 0.4 V 6.010 9.730 -- mA Push-Pull 2X, V OL = 0.4 V 11.590 19.460 -- mA Open Drain NMOS 1X, V OL = 0.4 V 11.760 19.460 -- mA Open Drain NMOS 2X, V OL = 0.4 V 19.120 35.621 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T TSU Startup Time from VDD rising past 1.35 V -- 0.27 -- ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.182 1.346 1.505 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.752 0.918 1.110 V RPUP Pull Up Resistance 100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance 100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

5.5 IDD Estimator

5.6 Timing Estimator

Table 1. Typical Current estimated for each macrocell. Table 2. Typical Delay estimated for each macrocell.

5.7 Typical Counter/Delay Offset Measurements

5.8 Expected Delays and Widths

Table 3. Typical Counter/Delay Offset Measurements. Table 4. Expected Delays and Widths for Programmable Delay (typical).

5.9 Typical Pulse Width Performance

Table 5. Typical Pulse Width Performance.

6.0 Summary of Macrocell Function

6.1 I/O Pins

Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
Open Drain Outputs
Push Pull Outputs
Analog I/O
10 k Ω /100 k Ω /1 M Ω pull-up/pull-down resistors

6.2 Connection Matrix

Digital matrix for circuit connections based on us er design

6.3 Analog Comparators (2 total)

Selectable hysteresis 0 mV/25 mV/50 mV/200 mV

6.4 Voltage Reference

Used for references on Analog Comparators
Can also be driven to external pin (Pin 10)

6.5 Combinational Logic Look Up Tables (LUTs – 4 total)

Two 2-bit Lookup Tables
Two 3-bit Lookup Tables

6.6 Combination Function Macrocells (7 total)

Two Selectable DFF/Latch or 2-bit LUTs
Two Selectable DFF/Latch or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
One Selectable CNT/DLY or 4-bit LUT
One Programmable Delay or Deglitch Filter

6.7 Delays/Counters (3 total)

Three 8-bit delays/counters with external clock/re set: Range 1-255 clock cycles

6.8 Pipe Delay (Part of Combination Function Macrocell)

8 stage / 2 output
Two 1-8 stage selectable outputs.

6.9 Programmable Delay

125 ns/250 ns/375 ns/500 ns @ 3.3 V
Includes Edge Detection function

6.10 Additional Logic Functions (Part of Combination Function Macrocell)

One Deglitch filter macrocell

6.11 RC Oscillator

25 kHz and 2 MHz selectable frequency
First Stage Clock pre=divider (4): OSC/1, OSC/2, O SC/4, and OSC/8
Second stage divider control with two outputs, OUT 0 and OUT1 (8): selectable (OSC/1, OSC/2, OSC/3, OSC/4, OSC/8, OSC/12, OSC/24, or OSC/64)

6.12 Power On Reset (POR)

7.0 I/O Pins

The SLG46110 has a total of 8 multi-function I/O pi ns which can function as either a user defined Inpu t or Output, as well as serving as a special function (such as outputting t he voltage reference), or serving as a signal for p rogramming of the on-chip Non Volatile Memory (NVM). Normal Mode pin definitions are as follows:

Pin 1: V DD Power Supply
Pin 2: General Purpose Input
Pin 3: General Purpose I/O or Analog Comparator 0 (+)
Pin 4: General Purpose I/O or Analog Comparator 0 (-)
Pin 5: No Connect
Pin 6: General Purpose I/O or Analog Comparator 1 (+) with OE
Pin 7: Ground
Pin 8: General Purpose I/O
Pin 9: General Purpose I/O
Pin 10: General Purpose I/O with OE and Vref Outpu t
Pin 11: No Connect
Pin 12: General Purpose I/O or External Clock Inpu t Programming Mode pin definitions are as follows:
Pin 1: V DD Power Supply
Pin 2: V PP Programming Voltage
Pin 3: Programming ID Pin
Pin 7: Ground
Pin 8: Programming Mode Control
Pin 9: Programming SDIO Pin
Pin 10: Programming SRDWB Pin
Pin 12: Programming SCL Pin Of the 8 user defined I/O pins on the SLG46110, all but one of the pins (Pin 2) can serve as both digital input and digital output. Pin 2 can only serve as a digital input pin.

7.1 Input Modes

Each I/O pin can be configured as a digital input p in with/without buffered Schmitt trigger, or can al so be configured as a low voltage digital input. Pins 3, 4, and 6 can also be configured to serve as analog inputs to the on-chip comparators.

7.2 Output Modes

Pins 3, 4, 6, 8, 9, 10, and 12 can all be configured as digital output pins.

7.3 Pull Up/Down Resistors

All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors are 10 k Ω , 100 k Ω and 1 M Ω . In the case of Pin 2, the resistors are fixed to a pull-down configuration. In the case of all other I/O pins, the internal resistors can be configured as either pull-up or pull-downs.

7.4 I/O Register Settings

7.4.1 PIN 2 Register Settings

7.4.2 PIN 3 Register Settings

Table 6. PIN 2 Register Settings Table 7. PIN 3 Register Settings

7.4.3 PIN 4 Register Settings

7.4.4 PIN 6 Register Settings

Table 8. PIN 4 Register Settings Table 9. PIN 6 Register Settings

7.4.5 PIN 8 Register Settings

7.4.6 PIN 9 Register Settings

Table 10. PIN 8 Register Settings Table 11. PIN 9 Register Settings

7.4.7 PIN 10 Register Settings

7.4.8 PIN 12 Register Settings

Table 12. PIN 10 Register Settings Table 13. PIN 12 Register Settings

7.5 GPI IO Structure

7.5.1 GPI IO Structure (for Pin 2)

Figure 2. PIN 2 GPI IO Structure Diagram

7.6 Matrix OE IO Structure

7.6.1 Matrix OE IO Structure (for Pin 6, 10)

Figure 3. Matrix OE IO Structure Diagram

7.7 Register OE IO Structure

7.7.1 Register OE IO Structure (for Pins 3, 4, 8, 9, 12)

Figure 4. Register OE IO Structure Diagram

8.0 Connection Matrix

macrocell uses a 5-bit register to select one of these 32 input lines. For a complete list of the SLG46110’s register table, see Section 16.0 Appendix A - SLG46110 Register Definition . Figure 5. Connection Matrix Figure 6. Connection Matrix Example

8.1 Matrix Input Table

Table 14. Matrix Input Table

0 VSS 0 0 0 0 0

5 LUT2_0 output (DFF/LATCH_0 output) 0 0 1 0 1

6 LUT2_1 output (DFF/LATCH_1 output) 0 0 1 1 0

7 LUT2_2 output 0 0 1 1 1

8 LUT2_3 output 0 1 0 0 0

9 LUT3_0 output (DFF/LATCH_2 output with resetb or s eb) 0 1 0 0 1

10 LUT3_1 output (DFF/LATCH_3 output with resetb or seb) 0 1 0 1 0

11 LUT3_2 output 0 1 0 1 1

12 LUT3_3 output 0 1 1 0 0

13 LUT3_4 output(pipe delay ouput0) 0 1 1 0 1

15 LUT4_0 output (CNT_DLY2 output (8 bit w/ ext CK,r eset)) 0 1 1 1 1

16 CNT_DLY0 output (8 bit w/ ext CK (shared bottom d elay/cnt),reset) 1 0 0 0 0

17 CNT_DLY1 output (8 bit w/ ext CK (from dedicated matrix out -

18 CNT_DLY3 (8 bit) output 1 0 0 1 0

19 ACMP_0 output 1 0 0 1 1

20 ACMP_1 output 1 0 1 0 0

21 Edge detect output 1 0 1 0 1

22 Programmable delay with edge detector output (Deglitch filter out -

25 Bandgap OK signal 1 1 0 0 1

26 POR output to matrix 1 1 0 1 0

31 VDD 1 1 1 1 1

8.2 Matrix Output Table

Table 15. Matrix Output Table

9.0 Combinatorial Logic

Combinatorial logic is supported via four Lookup Tables (LUTs) within the SLG46110. There are two 2-bit LUTs and two 3-bit LUTs. 10.0 Combination Function Macrocells. devices (AND, NAND, OR, NOR, XOR, XNOR). created within each of the two 2-bit LUT logic cells. Figure 7. 2-bit LUTs Table 18. 2-bit LUT Standard Digital Functions. Table 16. 2-bit LUT2 Truth Table. Table 17. 2-bit LUT3 Truth Table.

Figure 8. 3-bit LUTs Table 19. 3-bit LUT2 Truth Table. Table 20. 3-bit LUT3 Truth Table.

created within each of the two 3-bit LUT logic cells. Table 21. 3-bit LUT Standard Digital Functions.

10.0 Combination Function Macrocells

The SLG46110 has seven combination function macrocells that can serve more than one logic or timing function. In six of these cases, they can serve as a Look Up Table (LUT), or as another logic or timing function. In the last case, it can serve as either a programmable delay or deglitch filter. See the list below for the functions that can be implemented in these macrocells;

Two macrocells that can serve as either 2-bit LUTs or as D Flip Flops.
Two macrocells that can serve as either 3-bit LUTs or as D Flip Flops.
One macrocell that can serve as either 3-bit LUT o r as Pipe Delay
One macrocells that can serve as either 4-bit LUTs or as 8-Bit Counter / Delays
One macrocell that can serve as either a Programma ble Delay or as a Deglitch Filter Inputs/Outputs for the seven combination function macrocells are configured from the connection matrix with specific logic func - tions being defined by the state of NVM bits. When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR). When used as a D Flip Flop / Latch, the source and destination of the inputs and outputs for the DFF/Latches are configured from the connection matrix. All DFF/Latch macrocells have user selection for initial state, and all have th e option to connect both the Q and Q Bar outputs to the connection matrix. The m acrocells DFF2, DFF3 have an additional input from the matrix that can serve as a nSet or nReset function to the macrocell. The operation of the D Flip-Flop and Latch will follow the functional descriptions below: DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change Latch: if CLK = 0, then Q = D 10.1 2-Bit LUT or D Flip Flop Macrocells There are two macrocells that can serve as either 2-bit LUTs or as D Flip Flops. When used to implement LUT functions, the 2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the connection matrix. When used to implement D Flip Flop function, the two input signals from the connection matrix go to the data (d) and clock (clk) inputs for the Flip Flop, with the output going back to the connection matrix.

Table 24. DFF0 Register Settings Table 25. DFF1Register Settings Table 22. 2-bit LUT0 Truth Table. Table 23. 2-bit LUT1 Truth Table.

Table 26. 3-bit LUT0 Truth Table. Table 27. 3-bit LUT1 Truth Table.

Table 28. DFF2 Register Settings Table 29. DFF3 Register Settings

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay. output, which goes back into the connection matrix. When used as an 8-stage pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CK) and Reset (nReset). the selection of the amount of delay. be the total time delay of the Pipe Delay logic cell. Figure 13. 3-bit LUT4 or Pipe Delay

8 Flip-Flops IN

Table 31. Pipe Delay Register Settings Table 30. 3-bit LUT4 Truth Table.

external clock (ext_clk) and reset (DLY_n/CNT_Reset) for the counter/delay, with the output going back to the connection matrix. Note: Counters initialize with counter data=0 after POR. Figure 14. 4-bit LUT0 or CNT/DLY2

Table 33. 4-bit LUT Standard Digital Functions Table 32. 4-bit LUT0 Truth Table.

10.5 Programmable Delay / Edge Detector

period. See the timing diagrams below for further information. Note : The input signal must be longer than the delay, otherwise it will be filtered out. Table 34. CNT/DLY2 Register Settings Figure 15. Programmable Delay

10.6 Programmable Delay Timing Diagram - Edge Detector Output

Note: For delays and widths refer to Table 4 .

10.6.1 Programmable Delay Register Settings

Figure 16. Edge Detector Output Figure 17. Delayed Edge Detector Output Table 35. Programmable Delay Register Settings

10.7 Deglitch Filter

Figure 18. Deglitch Filter

11.0 Analog Comparators (ACMP)

a digital signal coming from the Connection Matrix. When ACMP is powered down, output is low. either created from an internal VREF or provided by way of the external sources. also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV or 200 mV. Note: Regulator and Charge Pump set to automatic ON/OFF. use Vref selection VDD/4 and VDD/3 to maintain this input range. Figure 19. Maximum Power On Delay vs. VDD. Table 36. Gain Divider Input Resistance (typ). Table 37. Gain Divider Accuracy.

reference/source. Internal Vref accuracy is optimized near 1000 mV selection. Note: Power supply control options have influence on the ACMP operation. Force BandGap option is set as Disabled).

Hysteresis: Input signal hysteresis options are Di sable, 25 mV, 50 mV, 200 mV.
Low Bandwidth: Enable, Disable;
IN+ Gain: 1X, 0.5X, 0.33X, 0.25X;
IN+ source:
ACMP0 IN+ options are PIN 3, VDD;
ACMP1 IN+ options are PIN 6, ACMP0 IN+;
IN- source:
ACMP0 IN- options are 24 internal reference sources (50 mV – 1200 mV) and VDD/3, VDD/4, PIN 4;
PWR UP=0 – ACMP is powered down; PWR UP=1 – ACMP is powered up. All ACMPs can have a common negative input. This can be achieved by configuring ACMP0 PIN 4 analog I/O connection.

11.1 ACMP0 Block Diagram

Figure 20. ACMP0 Block Diagram

11.2 A CMP0 Register Settings

Table 38. ACMP0 Register Settings

11.3 ACMP1 Block Diagram

Figure 21. ACMP1 Block Diagram

11.4 ACMP1 Register Settings

Table 39. ACMP1 Register Settings

11.5 Typical Performance Characteristics

Note: when VDD < 1.8V voltage reference should not exceed 1100 mV. Figure 22. Typical Input Voltage Offset vs. Voltage Reference at room temperature, LBW Mode – Disable, Vhys=0 mV, VDD=(1.7 – 5.5) V. Figure 23. Typical Input Threshold Variation (including Vref variation, ACMP offset) vs. Voltage reference at room temperature, LBW Mode – Disable, Vhys=0 mV.

11.6 Timing Characteristics

Figure 28. Maximum Propagation Delay Low-to-High Figure 29. Maximum Propagation Delay Low-to-High

1100 E (mV)

Figure 30. Maximum Propagation Delay High-to-Low Figure 31. Maximum Propagation Delay High-to-Low

Figure 32. Maximum Propagation Delay Low-to-High Figure 33. Maximum Propagation Delay Low-to-High Figure 34. Maximum Propagation Delay High-to-Low Figure 35. Maximum Propagation Delay High-to-Low

12.0 Counters/Delay Generators (CNT/DLY)

option to chain from the output of the previous (N-1) CNT/DLY macrocell, to implement longer count / delay circuits. more information please see Section 10.4 4-Bit LUT or 8- Bit Counter / Delay Macrocells. Note: Counters initialize with counter data=0 after POR. Figure 36. CNT/DLY0

12.1 CNT/DLY0 Register Settings

12.2 CNT/DLY1 Register Settings

Table 41. CNT/DLY0 Register Settings Table 42. CNT/DLY1 Register Settings

12.3 CNT/DLY3 Register Settings

Table 43. CNT/DLY3 Register Settings

13.0 Voltage Reference (VREF)

13.1 Voltage Reference Overview

for the available selections for each analog comparator. Also see Figure 39. below, which shows the reference output structure.

13.2 VREF Selection Table

Table 44. VREF Selection Table.

11001 VDD / 4 VDD / 4

11000 VDD / 3 VDD / 3

13.3 VREF Block Diagram

Figure 39. Voltage Reference Block Diagram

14.0 RC Oscillator (RC OSC)

14.1 RC Oscillator Overview

Note: RC OSC power setting: "Auto Power On”. Figure 40. Maximum Power On Delay vs. VDD, RC OSC = 2 MHz. Figure 41. Maximum Power On Delay vs. VDD, RC OSC = 25 kHz.

lines <23>, and <24>. See Figure 42. below for details of the frequencies for each of these two Connection Matrix Inputs. will be turned off. The PWR DOWN signal has the highest priority.

14.2 RC OSC Block Diagram

Figure 42. RC OSC Block Diagram

15.0 Power On Reset (POR)

The SLG46110 has a power-on reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first ramping to the device, and also while the VDD is falling during power-down. To accomplish this goal, the POR drives a defined sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of the I/O pins. This application note is created to explain the whole process of POR operation and GreenPAK chip behavior during the time while it is powering up and powering down.

15.1 General Operation

The SLG46110 is guaranteed to be powered down and nonoperational when the VDD voltage (voltage on PIN1) is less than 0.6V, but not less than -0.6V. Another essential condition for the chip to be powered down is that no voltag e higher (see Note 1) than the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3V, applying a voltage higher than 0.3V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior. Note 1. There is a 0.6V margin due to forward drop voltage of the ESD protection diodes. To start the POR sequence in the SLG46110, the volt age applied on the VDD should be higher than the Po wer_ON threshold voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power_ON threshold. After the POR sequence has started, the SLG46110 will have a typical period of time to go through all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after the POR sequence is complete. Note 2. The Power_ON threshold can vary by PVT, but typically it is 1.6V. To power down the chip the VDD voltage should be lo wer than the operational and to guarantee that chip is powered down it should be less than 0.6V. All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step in the POR sequence releases the I/O structures from the high impedance state, at which time the device is operational. The pin configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.

15.2 POR Sequence

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 43. . environmental factors, such as: slew rate, VDD value, temperature and even will vary from chip to chip (process influence). Figure 43. POR sequence

15.3 Macrocells Output States During POR Sequence

states during the POR sequence ( Figure 44. describes the output signals states). last are output PINs that become active and determined by the input signals. Figure 44. Internal Macrocell States during POR sequence

16.0 Appendix A - SLG46110 Register Definition

Address Signal Function Register Bit Definition reg <4:0> Matrix Out: PIN3 Digital Output Source reg <9:5> Matrix Out: PIN4 Digital Output Source reg <14:10> Matrix Out: PIN6 Digital Output Source reg <19:15> Matrix Out: Output Enable of PIN6 reg <24:20> Matrix Out: In0 of LUT2_0 or Clock Input of DFF0 reg <29:25> Matrix Out: In1 of LUT2_0 or Data Input of DFF0 reg <34:30> Matrix Out: In0 of LUT2_1 or Clock Input of DFF1 reg <39:35> Matrix Out: In1 of LUT2_1 or Data Input of DFF1 reg <44:40> Matrix Out: In0 of LUT2_2 reg <49:45> Matrix Out: In1 of LUT2_2 reg <54:50> Matrix Out: In0 of LUT2_3 reg <59:55> Matrix Out: In1 of LUT2_3 reg <64:60> Matrix Out: In0 of LUT3_0 or Clock Input of DFF2 reg <69:65> Matrix Out: In1 of LUT3_0 or Data Input of DFF2 reg <74:70> Matrix Out: In2 of LUT3_0 or Resetb Inpu t of DFF2 reg <79:75> Matrix Out: In0 of LUT3_1 or Clock Input of DFF3 reg <84:80> Matrix Out: In1 of LUT3_1 or Data Input of DFF3 reg <89:85> Matrix Out: In2 of LUT3_1 or Resetb(Setb ) of DFF3 reg <94:90> Matrix Out: In0 of LUT3_2 reg <99:95> Matrix Out: In1 of LUT3_2 reg <104:100> Matrix Out: In2 of LUT3_2 reg <109:105> Matrix Out: In0 of LUT3_3 reg <114:110> Matrix Out: In1 of LUT3_3 reg <119:115> Matrix Out: In2 of LUT3_3 reg <124:120> Matrix Out: In0 of LUT3_4 or Input of Pipe delay reg <129:125> Matrix Out: In1 of LUT3_4 or Resetb of Pipe delay reg <134:130> Matrix Out: In2 of LUT3_4 or Clock of Pipe delay reg <139:135> Matrix Out: In0 of LUT4_0 or Input for delay2 (Counter2) external clock reg <144:140> Matrix Out: In1 of LUT4_0 or Input for delay2 data (counter2 reset) reg <149:145> Matrix Out: In2 of LUT4_0 reg <154:150> Matrix Out: In3 of LUT4_0 reg <159:155> Matrix Out: Input for delay0 data (cou nter0 reset) reg <164:160> Matrix Out: Input for delay1 data (cou nter1 reset) reg <169:165> Matrix Out: Input for delay0/1 (Counter0/1) external clock reg <174:170> Matrix Out: Input for delay3 (Counter3 ) external clock reg <179:175> Matrix Out: pdb (power down) for ACMP0 reg <184:180> Matrix Out: pdb (power down) for ACMP1 reg <189:185> Matrix Out: Input for programmable delay (deglitch filter input)

© 2023 Renesas Electronics Corporation Page 66 of 82 SLG46110 Revision 1.12 reg <194:190> Matrix Out: Power down for osc reg <199:195> Matrix Out: PIN8 Digital Output Source reg <204:200> Matrix Out: PIN9 Digital Output Source reg <209:205> Matrix Out: PIN10 Digital Output Sourc e reg <214:210> Matrix Out: Output Enable of PIN10 reg <219:215> Matrix Out: PIN12 Digital Output Sourc e reg <223:220> Reserved Reserved DFF0/Latch or LUT2_0 data reg <227:224> reg <224> DFF0 or Latch select 0: DFF function 1: Latch function reg <225> DFF0 output select 0: Q output 1: nQ output reg <226> DFF0 initial polarity select 0: Low 1: High reg <227> Unused if DFF/Latch selected Unused DFF1/Latch or LUT2_1 data reg <231:228> reg <228> DFF1 or Latch select 0: DFF function 1:Latch function reg <229> DFF1 output select 0: Q output 1: nQ output reg <230> DFF1 initial polarity select 0: Low 1:High reg <231> Unused if DFF/Latch selected Unused LUT2_2 data reg <235:232> LUT2_2 data LUT2_2 data LUT2_3 data reg <239:236> LUT2_3 data LUT2_3 data LUT2_0/DFF0 reg <240> LUT2_0 or DFF0 select 0: LUT2_0 1: DFF0 LUT2_1/DFF1 reg <241> LUT2_1 or DFF1 select 0: LUT2_1 1: DFF1 DFF2/Latch or LUT3_0 data reg <249:242> reg <242> DFF2 or Latch select 0: DFF function 1: Latch function reg <243> DFF2 output select 0: Q output 1: nQ output reg <244> DFF2 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg <245> DFF2 initial polarity select 0: Low 1: High reg <249:246> Unused if DFF/Latch selected Unused Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 67 of 82 SLG46110 Revision 1.12 DFF3/Latch or LUT3_1 data reg <257:250> reg <250> DFF3 or Latch select 0: DFF function 1: Latch function reg <251> DFF3 output select 0: Q output 1: nQ output 0: Q output 1: nQ output reg <252> DFF3 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg <253> DFF3 initial polarity select 0: Low 1: High reg <257:254> Unused if DFF/Latch selected Unused LUT3_2 data reg <265:258> LUT3_2 data LUT3_2 data LUT3_3 data reg <273:266> LUT3_3 data LUT3_3 data Pipe number select or LUT3_4 data reg <281:274> reg <276:274>: OUT0 select data (pipe number) reg <279:277>: OUT1 select data (pipe number) reg <281:280>: Unused if Pipe Delay selected Unused LUT3/DFF Select reg <282> LUT3_0 or DFF2 select 0: LUT3_0 1: DFF2 reg <283> LUT3_1 or DFF3 select 0: LUT3_1 1: DFF3 reg <284> LUT3_4 or pipe delay output select 0: LUT3_4 1: pipe delay LUT4_0 or Counter/delay2 mode selection reg <300:285> reg <285> Counter/delay2 mode selection 0: Delay Mode 1: Counter Mode reg <288:286> Counter/delay2 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter1 Overflow reg <296:289> Counter/delay2 Control Data 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg <298:297> Delay2 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for delay & counter reset) 01: Delay on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: No delay on either falling or rising edges / high level reset for counter mode reg <300:299> Unused is Counter/Delay2 selected Unus ed reg <301> LUT4_0 or Counter2 select 0: LUT4_0, 1: Co unter2 0: LUT4_0 1: Counter2 Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 68 of 82 SLG46110 Revision 1.12 reg <302> Force RC oscillator on 0: Auto Power on 1: Force Power on reg <303> RC Oscillator frequency control 0: 25k 1: 2M reg <305:304> Osc clock pre-divider 00: div1 01: div2 10: div4 11: div8 reg <308:306> Internal Oscillator frequency divider control 0 for Matrix Input 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 reg <311:309> Internal Oscillator frequency divider control 1 for Matrix Input 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 reg <312> External Clock Source Select 0: Internal Oscillator 1: External Clock from PIN12 reg <313> Reserved Reserved Counter/Delay 0 reg <327:314> reg <314>Counter/delay0 mode selection 0: Delay Mode 1: Counter Mode reg <317:315> Counter/delay0 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter3 Overflow reg <325:318> Counter0 Control Data/Delay0 Time Control 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg <327:326> Delay0 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for delay & counter reset) 01: Delay on falling edge only (for delay & counter reset) 10: Delay on rising edge only (for delay & counter reset) 11: No delay on either falling or rising edges / high level reset for counter mode Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 69 of 82 SLG46110 Revision 1.12 Counter/Delay 1 reg <341:328> reg <328> Counter/delay1 mode selection 0: Delay Mode 1: Counter Mode reg <331:329> Counter/delay1 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter0 Overflow reg <339:332> Counter1 Control Data/Delay1 Time Control 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg <341:340> Delay1 Mode Select or asynchronous counter reset 00: Delay on both falling and rising edges (for delay & counter reset) 01: Delay on falling edge only (for delay & counter reset) 10: Delay on rising edge only (for delay & counter reset) 11: No delay on either falling or rising edges / high level reset for counter mode Counter/Delay 3 reg <355:342> reg <342> Counter/delay3 mode selection 0: Delay Mode 1: Counter Mode reg <345:343> Counter/delay3 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter2 Overflow reg <353:346> Counter3 Control Data/Delay4 Time Control 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg <355:354> Delay3 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 70 of 82 SLG46110 Revision 1.12 ACMP0 reg <366:356> reg <360:356> ACMP0 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: EXT_VREF(PIN4) reg <362:361> ACMP0 hysteresis Enable 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) reg <364:363> ACMP0 positive Input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x reg <365> ACMP0 low bandwidth (typ: Max.1Mhz) en - able. 0: off 1: on reg <366> ACMP0 positive input source select PIN3 and VDD 0: PIN3 1: VDD Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 71 of 82 SLG46110 Revision 1.12 ACMP1 reg <378:367> reg <371:367> ACMP1 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: EXT_VREF(PIN4) reg <373:372> ACMP1 hysteresis Enable 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) reg <375:374> ACMP1 positive Input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x reg <376> ACMP1 100uA current source option 0: disable 1: enable reg <377> ACMP1 low bandwidth (typ: Max.1 MHz) en - able. 0: off 1: on reg <378> ACMP1 positive input source select PIN6 and PIN3 0: PIN6 1: PIN3 PIN 2 reg <382:379> reg <380:379> PIN2 mode control 00: Digital Input without Schmitt trigger 01: Digital Input with Schmitt trigger 10: Low voltage digital input 11: Reserved reg <382:381> PIN2 pull down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 72 of 82 SLG46110 Revision 1.12 PIN 3 reg <389:383> reg <385:383> PIN3 mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Analog Input / Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input / Output & Open drain reg <387:386> PIN3 pull up/down resistor value selec - tion 00: floating 01: 10K 10: 100K 11: 1M reg <388> PIN3 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <389> PIN3 driver strength selection 0: 1X 1: 2X PIN 4 reg <396:390> reg <392:390> PIN4 mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Analog Input / Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input / Output & Open drain reg <394:393> PIN4 pull up/down resistor value selec - tion 00: floating 01: 10K 10: 100K 11: 1M reg <395> PIN4 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <396> PIN4 driver strength selection 0: 1X 1: 2X PIN6 reg <403:397> reg <398:397> PIN6 mode control (sig_PIN6_oe =0) 00: Digital Input without Schmitt trigger 01: Digital Input with Schmitt trigger 11: Low Voltage Digital Input 10: Analog Input / Output reg <400:399> PIN6 mode control (sig_PIN6_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg <402:401> PIN6 pull up/down resistor value selec - tion 00: floating 01: 10K 10: 100K 11: 1M reg <403> PIN6 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 73 of 82 SLG46110 Revision 1.12 PIN8 reg <410:404> reg <406:404> PIN8 mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Analog Input / Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input / Output & Open drain reg <408:407> PIN8 pull up/down resistor value selec - tion 00: floating 01: 10K 10: 100K 11: 1M reg <409> PIN8 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <410> PIN8 driver strength selection 0: 1X 1: 2X PIN9 reg <417:411> reg <413:411> PIN9 mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Analog Input / Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input / Output & Open drain reg <415:414> PIN9 pull down resistor value selection 00: floating 01: 10K 10: 100K 11: 1M reg <416> PIN9 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <417> PIN9 driver strength selection 0: 1X 1: 2X PIN10 reg <424:418> reg <419:418> PIN10 mode control (sig_PIN10_oe =0) 00: Digital Input without Schmitt trigger 01: Digital Input with Schmitt trigger 10: Low Voltage Digital Input 11: Analog Input / Output reg <421:420> PIN10 mode control (sig_PIN10_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg <423:422> PIN10 pull up/down resistor value selec - tion 00: floating 01: 10K 10: 100K 11: 1M reg <424> PIN10 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 74 of 82 SLG46110 Revision 1.12 PIN12 reg <431:425> reg <427:425> PIN12 mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Analog Input / Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input / Output & Open drain reg <429:428> PIN12 pull up/down resistor value selec - tion 00: floating 01: 10K 10: 100K 11: 1M reg <430> PIN12 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg <431> PIN12 driver strength selection 0: 1X 1: 2X reg <432> Pipe delay OUT1 polarity select bit 0: non-inverting 1: inverting reg <440:433> 8-bit pattern id 8-bit pattern id reg <441> filter0 output polarity select 0: non-inverting 1: inverting reg <443:442> Reserved Reserved reg <444> GPIO quick charge enable 0: Disable 1: Enable reg <445> Force bandgap on 0: Auto-mode 1: Enable reg <446> VREF1 Output Active Buffer Control 0: Disabled 1: Enabled reg <449:447> VREF1 Output Source Select 000: ACMP0 reference voltage 001: ACMP1 reference voltage 100: VDD/2 101: VDD/3 110: VDD/4 101: Reserved 110: Reserved 111: Reserved reg <450> NVM data read disable 0: Disable (read enable) 1: Enable (read disable) reg <451> NVM power down (or NVM data programming di sable) 0: None (or programming enable) 1: Power Down (or programming disable) reg <452> Power Divider Power 0: Power down 1: Power On reg <453> POR Auto Power detect 0: Enable 1: Disable reg <454> Charge pump for analog macrocell enable (when VDD <= 2.7 V turn on) 0: Disable (automatic on/off control) 1: Enable (always on) reg <455> VDD bypass enable 0: Regulator auto on 1: Regulator off (VDD bypass) reg <471:456> Reserved Reserved reg <479:472> Reserved Reserved Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 75 of 82 SLG46110 Revision 1.12 reg <481:480> Reserved Reserved reg <482> PIN2 edge detect mode 0: rising edge 1: falling edge reg <483> Bypass the PIN2 0: PIN2 edge active 1: PIN2 high active reg <484> PIN2 reset enable 0: Disable 1: Enable reg <485> programmable delay or filter output selec t 0: programmable delay output 1: filter output reg <487:486> Select the edge mode of programmable delay & edge detector 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay reg <489:488> Delay value select for programmable delay & edge de- tector (VDD = 3.3 V, typical condition) 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns reg <490> Reserved Reserved reg <495:491> Reserved Reserved reg <501:496> Reserved Reserved reg <502> Reserved Reserved reg <503> Reserved Reserved reg <511:504> Reserved Reserved Register Bit Address Signal Function Register Bit Definition

17.0 Package Top Marking System Definition

17.1 Before February 1, 2021

17.2 After February 1, 2021

P P A Part Code + Assembly Code Pin 1 Identifier WWR Date Code + Revision Code NN Serial Number Code P P P Part Code Pin 1 Identifier WWR Date Code + Revision Code NN Serial Number Code

18.0 Package Drawing and Dimensions

12 Lead STQFN FC Package 1.6 x 1.6 mm IC net weight: 0.0028 g

19.0 Tape and Reel Specifications

19.1 Carrier Tape Drawing and Dimensions

# of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 12L FC 0.4P Green 12 1.6x1.6x0.55 3000 3000 178/60 100 400 100 400 8 4 Package Type Pocket BTM Length [mm] Pocket BTM Width [mm] Pocket Depth [mm] Index Hole Pitch [mm] Pocket Pitch [mm] Index Hole Diameter [mm] Index Hole to Tape Edge [mm] Index Hole to Pocket Center [mm] Tape Width [mm] A0 B0 K0 P0 P1 D0 E F W STQFN 12L FC 0.4P Green

20.0 Recommended Land Pattern

21.0 Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 1.408 mm 3 (nominal). More information can be found at www.jedec.org. Units: µm

22.0 Revision History

3/9/2023 1.12 Added notes to section Ordering Informa tion 3/4/2022 1.11 Added R PUP and R PDWN in section Electrical Specifications Renesas rebranding 9/3/2021 1.10 Updated tables CNT/DLY Register Settings Corrected registers [296:289], [325:318], [339:332], [353:346] in Appendix A - SLG46110 Register Definition 2/2/2021 1.09 Updated section Package Top Marking System Definition Added note for CNTs Updated registers for LUT2_0 data, LUT2_1 data, and LUT2_3 data Corrected registers [353:343], [339:329], [325:315], [296:285] 10/29/2019 1.08 Updated disclaimer 11/14/2018 1.07 Updated to Dialog style 10/10/2017 1.06 Updated Electrical Spec Fixed typos Updated POR sequence 7/7/2017 1.05 Fixed typos Removed references to GPAK families Updated Silego Website & Support Updated Section Programmable Delay / Edge Detector Updated Electrical Spec 5/27/2016 1.04 Updated Programmable Delay information Added PON THR and POFF THR in Electrical Spec 4/4/2016 1.03 Corrected section 6.0 10/28/2015 1.02 Updated Absolute maximum conditions 9/29/2015 1.01 Fixed typos 5/26/2016 1.0 Production Release 5/21/2015 0.66 Updated ACMP Diagrams and added Timing Characteristics Diagrams 4/23/2015 0.65 Updated ACMP section 4/9/2015 0.64 Updated Tsu condition and value 3/27/2015 0.63 Updated ACMP section Updated RC Oscillator section 3/16/2015 0.62 Updated Register table (typos) 3/10/2015 0.61 Added Connection Matrix Example 3/9/2015 0.60 Added POR section 1/14/2015 0.59 Added IDD Estimator, Timing Estimator, Expected Delays sections 12/3/2014 0.58 Updated Electrical Characteristics VIH /VIL/VOH/VOL values (formatting/rounding) 9/3/2014 0.57 Updated Electrical Characteristics VIH/ VIL/VOH/VOL values 8/25/2014 0.56 Added Recommended Land Pattern 7/23/2014 0.55 Fixed ESD information 6/20/2014 0.54 Fixed typo on Electrical Spec 5/21/2014 0.53 Updated block diagram Fixed typos Moved Programmable Delay and Deglitch Filter to Combination Macrocells section 4/29/2014 0.52 Added ESD Ratings and MSL to Absolute Maximum Conditions 3/28/2014 0.5 Fixed typos Preliminary Release 3/18/2014 0.42 Updated block diagrams and timing diag rams for clarity

© 2023 Renesas Electronics Corporation Page 81 of 82 SLG46110 Revision 1.12 2/12/2014 0.41 Fixed typos 12/2/2013 0.40 Updated VIH/VIL in Electrical Characteristics Fixed typos Added IC net weight to Package Specification 11/25/2013 0.31 Added Block Diagram 11/11/2013 0.30 Added Diagrams 9/30/2013 0.20 Updated Electrical Characteristics Added Register Table and Descriptions 9/16/2013 0.10 Initial release Date Version Change

© 2023 Renesas Electronics Corporation Page 82 of 82 SLG46110 Revision 1.12 RoHS Compliance Renesas Electronics Corporation’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous sub stances in electrical and electronic equipment. RoH S certificates from our suppliers are available on request.

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Selected Specification

Renesas Technology Corp SLG46110VTR overview.

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Summary

Programmable Mixed Signal Matrix March 9, 2023

Description

Programmable Mixed Signal Matrix March 9, 2023

Source title SLG46110VTR Datasheet(PDF) - Renesas Technology Corp

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