SLG46108 Datasheet | DigiCamel IC Datasheet

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SLG46108 RENESAS

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 72

Technical content

Features

Logic & Mixed Signal Circuits
Highly Versatile Macrocells
1.8 V (±5%) to 5 V (±10%) Supply
Operating Temperature Range: -40°C to 85°C
RoHS Compliant / Halogen-Free
Pb-Free 8-pin STQFN: 1.0 x 1.2 x 0.55 mm, 0.4 mm pitch

Applications

Personal Computers and Servers
PC Peripherals
Consumer Electronics
Data Communications Equipment
Handheld and Portable Electronics Pin Configuration GND GPIO GPIO GPIO GPIO GPIO GPI VDD 1 STQFN-8 (Top View) 3-bit LUT3_4 or Pipe Delay Pin 1 VDD Pin 2 GPI Pin 3 GPIO Pin 4 GPIO Pin 6 GPIO Pin 5 GND Pin 8 GPIO Pin 7 GPIO CNT0 CNT3 CNT1 2-bit LUT2_2 3-bit LUT3_3 2-bit LUT2_3 3-bit LUT3_2 2-bit LUT2_0 or DFF0 2-bit LUT2_1 or DFF1 3-bit LUT3_1 or DFF3 3bit LUT3_0 or DFF2 4-bit LUT4_0 or CNT2 FILTER_0/Prog. Delay Additional Combination Functions Counters/Delay Generators RC Oscillator POR Combination Function Macrocells Look Up Tables (LUTs)

1.0 Overview

The SLG46108 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Mem ory (NVM) to configure the interconnect logic, the I/O Pins and the macrocells of the SLG46108. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The macrocells in the device include the following:

Four Combinatorial Look Up Tables (LUTs)
Two 2-bit LUTs
Two 3-bit LUTs
Seven Combination Function Macrocell
Two Selectable D Flip-Flop / Latches (DFF) or 2-bit LUTs
Two Selectable D Flip-Flop / Latches (DFF) or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
Pipe Delay – 8 stage / 2 output
One Selectable Counter/Delay (CNT/DLY) or 4-bit LUT
One Programmable Delay / Deglitch Filter
Three 8-bit Counter / Delay Generators (CNT/DLY) w ith external clock/reset
RC Oscillator (RC OSC)
Power On Reset (POR)

2.0 Pin Description

2.1 Functional Pin Description

Pin # Pin Name Function

1 VDD Power Supply

2 GPI General Purpose Input

3 GPIO General Purpose I/O

4 GPIO General Purpose I/O

5 GND GND

6 GPIO General Purpose I/O

7 GPIO General Purpose I/O

8 GPIO General Purpose I/O

3.0 User Programmability

as it remains powered and can be re-written as needed to facilitate rapid design changes. Figure 1. Steps to create a custom GreenPAK device

4.0 Ordering Information

Note 1: Use SLG46108V to order. Shipments are automatically in Tape and Reel. Note 2: “TR” suffix is no longer used. It is a legacy naming convention shown here only for informational purposes. Part Number Type SLG46108V 8-pin STQFN SLG46108VTR 8-pin STQFN - Tape and Reel (3k units)

5.0 Electrical Specifications

5.1 Absolute Maximum Conditions

5.2 Electrical Characteristics (1.8 V ±5% V DD ) Parameter Min. Max. Unit Supply voltage on VDD relative to GND -0.5 7 V DC Input voltage GND - 0.5 VDD + 0.5 V Maximum Average or DC Current (Through pin) Push-Pull 1x -- 8 mA Push-Pull 2x -- 10 OD 1x -- 8 OD 2x -- 12 Current at Input Pin -1.0 1.0 mA Storage Temperature Range -65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1300 -- V Moisture Sensitivity Level 1 Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 1.71 1.80 1.89 V IQ Quiescent Current Static Inputs and Outputs (when OSC is powered down and non-operational) -- 0.28 -- µA T A Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VIH HIGH-Level Input Voltage Logic Input 1.071 -- V DD V Logic Input with Schmitt Trigger 1.276 -- V DD V Low-Level Logic Input 0.936 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 0.730 V Logic Input with Schmitt Trigger -- -- 0.475 V Low-Level Logic Input -- -- 0.517 V V HYS Schmitt Trigger Hysteresis Voltage Logic Input with Schmitt Trigger 0.26 0.47 0.60 V I LKG Input leakage (Absolute Value) -- 0.001 1 µA V OH HIGH-Level Output Voltage Push-Pull 1X, Open Drain PMOS 1X, I OH = 100 µA 1.692 1.788 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 100 µA 1.700 1.794 -- V

© 2023 Renesas Electronics Corporation Page 6 of 70 SLG46108 Revision 1.14 VOL LOW-Level Output Voltage Push-Pull 1X, I OL = 100 µA -- 0.01 0.016 V Push-Pull 2X, I OL = 100 µA -- 0.005 0.007 V Open Drain NMOS 1X, I OL = 100 µA -- 0.005 0.006 V Open Drain NMOS 2X, I OL = 100 µA -- 0.003 0.003 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, V OH = V DD - 0.2 1.045 1.506 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = V DD - 0.2 2.097 2.982 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, V OL = 0.15 V 0.984 1.363 -- mA Push-Pull 2X, V OL = 0.15 V 2.011 2.743 -- mA Open Drain NMOS 1X, V OL = 0.15 V 2.029 2.763 -- mA Open Drain NMOS 2X, V OL = 0.15 V 4.020 5.471 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T VO Maximal Voltage Applied to any PIN in High-Impedance State -- -- VDD V T SU Startup Time From VDD rising past PON THR -- -- 0.54 ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.302 1.505 1.707 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.681 0.902 1.170 V RPUP Pull Up Resistance

1 M Pull Up -- 1 -- M Ω

100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance

1 M Pull Down -- 1 -- M Ω

100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3 and 4 are connected to one side, pins 6, 7 and 8 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

© 2023 Renesas Electronics Corporation Page 7 of 70 SLG46108 Revision 1.14 5.3 Electrical Characteristics (3.3 V ±10% V DD ) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3.0 3.3 3.6 V IQ Quiescent Current Static Inputs and Outputs (when OSC is powered down and non-operational) -- 0.52 -- µA T A Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VIH HIGH-Level Input Voltage Logic Input 1.840 -- V DD V Logic Input with Schmitt Trigger 2.170 -- V DD V Low-Level Logic Input 1.086 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 1.255 V Logic Input with Schmitt Trigger -- -- 0.934 V Low-Level Logic Input -- -- 0.669 V V HYS Schmitt Trigger Hysteresis Voltage Logic Input with Schmitt Trigger 0.56 0.71 0.86 V I LKG Input leakage (Absolute Value) -- 0.001 1 µA V OH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, I OH = 3 mA 2.721 3.108 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 3 mA 2.864 3.204 -- V VOL LOW-Level Output Voltage Push-Pull 1X, I OL = 3 mA -- 0.175 0.257 V Push-Pull 2X, I OL = 3 mA -- 0.086 0.122 V Open Drain NMOS 1X, I OL = 3 mA -- 0.085 0.121 V Open Drain NMOS 2X, I OL = 3 mA -- 0.043 0.061 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, V OH = 2.4 V 5.774 11.066 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = 2.4 V 11.351 21.730 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, V OL = 0.4 V 4.491 6.438 -- mA Push-Pull 2X, V OL = 0.4 V 9.124 12.884 -- mA Open Drain NMOS 1X, V OL = 0.4 V 9.227 12.995 -- mA Open Drain NMOS 2X, V OL = 0.4 V 17.995 25.459 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T

© 2023 Renesas Electronics Corporation Page 8 of 70 SLG46108 Revision 1.14 VO Maximal Voltage Applied to any PIN in High-Impedance State -- -- VDD V T SU Startup Time From VDD rising past PON THR -- -- 0.52 ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.303 1.506 1.707 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.718 0.901 1.173 V RPUP Pull Up Resistance 100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance 100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3 and 4 are connected to one side, pins 6, 7 and 8 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

5.4 Electrical Characteristics (5 V ±10% V DD )

Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V IQ Quiescent Current Static Inputs and Outputs (when OSC is powered down and non-operational) -- 0.81 -- µA T A Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VIH HIGH-Level Input Voltage Logic Input 2.744 -- V DD V Logic Input with Schmitt Trigger 3.190 -- V DD V Low-Level Logic Input 1.185 -- V DD V VIL LOW-Level Input Voltage Logic Input -- -- 1.877 V Logic Input with Schmitt Trigger -- -- 1.488 V Low-Level Logic Input -- -- 0.765 V V HYS Schmitt Trigger Hysteresis Voltage Logic Input with Schmitt Trigger 0.77 0.94 1.14 V I LKG Input leakage (Absolute Value) -- 0.001 1 µA V OH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, I OH = 5 mA 4.171 4.761 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 5 mA 4.336 4.879 -- V VOL LOW-Level Output Voltage Push-Pull 1X, I OL = 5 mA -- 0.225 0.325 V Push-Pull 2X, I OL = 5 mA -- 0.111 0.156 V Open Drain NMOS 1X, I OL = 5 mA -- 0.110 0.155 V Open Drain NMOS 2X, I OL = 5 mA -- 0.057 0.080 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, V OH = 2.4 V 20.656 30.203 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = 2.4 V 40.170 56.319 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, V OL = 0.4 V 6.087 8.611 -- mA Push-Pull 2X, V OL = 0.4 V 12.321 17.147 -- mA Open Drain NMOS 1X, V OL = 0.4 V 12.444 17.282 -- mA Open Drain NMOS 2X, V OL = 0.4 V 24.032 33.581 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T

© 2023 Renesas Electronics Corporation Page 10 of 70 SLG46108 Revision 1.14 VO Maximal Voltage Applied to any PIN in High-Impedance State VDD V T SU Startup Time From VDD rising past PON THR 0.51 ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.303 1.506 1.707 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.675 0.901 1.174 V RPUP Pull Up Resistance 100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance 100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3 and 4 are connected to one side, pins 6, 7 and 8 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

5.5 IDD Estimator

5.6 Timing Estimator

Table 1. Typical Current estimated for each macrocel l Table 2. Typical Delay estimated for each macrocell

5.7 Typical Counter/Delay Offset Measurements

5.8 Expected Delays and Widths

5.9 Typical Pulse Width Performance

Table 3. Typical Counter/Delay Offset Measurements Table 4. Expected Delays and Widths (typical) Table 5. Typical Pulse Width Performance.

5.10 OSC Specifications

Table 6. 25 kHz RC OSC frequency limits Table 7. 25 kHz RC OSC frequency error (error calcul ated relative to nominal value)

5.10.3 OSC Power On Delay

Table 8. 2 MHz RC OSC frequency limits Table 9. 2 MHz RC OSC frequency error (error calcula ted relative to nominal value) Table 10. Oscillators Power On delay at room tempera ture, RC OSC power setting, "Auto Power On"

2 MHz 2 MHz Fast start-up mode 25 kHz 25 kHz Fast start-up mode

6.0 Summary of Macrocell Function

6.1 I/O Pins

Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
Open Drain Outputs (NMOS and PMOS, 1X and 2X)
Push Pull Outputs (1X and 2X)
10 k Ω /100 k Ω /1 M Ω pull-up/pull-down resistors
Pins 4 and 8 can be configured as bidirectional IO

6.2 Connection Matrix

Digital matrix for circuit connections based on us er design

6.3 Combinational Logic Look Up Tables (LUTs – 4 total)

Two 2-bit Lookup Tables
Two 3-bit Lookup Tables

6.4 Combination Function Macrocells (7 total)

Two Selectable DFF/Latch or 2-bit LUTs
Two Selectable DFF/Latch or 3-bit LUTs
One Selectable Pipe Delay or 3-bit LUT
One Selectable CNT/DLY or 4-bit LUT
One Programmable Delay or Deglitch Filter

6.5 Delays/Counters (3 total)

Three 8-bit delays/counters with external clock/re set: Range 1-255 clock cycles

6.6 Pipe Delay (Part of Combination Function Macrocell)

8 stage / 2 output
Two 1 to 8 stage selectable outputs

6.7 Programmable Delay

140 ns/280 ns/420 ns/560 ns @ VDD = 3.3 V
Includes Edge Detection function

6.8 Additional Logic Functions (Part of Combination Function Macrocell)

One Deglitch filter macrocell

6.9 RC Oscillator

25 kHz or 2 MHz selectable frequency
First Stage Clock pre-divider: OSC/1, OSC/2, OSC/4 , and OSC/8
Second stage divider control with two outputs, OUT0 and OUT1: selectable (OSC/1, OSC/2, OSC/3, OSC/4, OSC/8, OSC/12, OSC/24, or OSC/64)

6.10 Power On Reset (POR)

7.0 I/O Pins

The SLG46108 has a total of multi-function I/O pins which can function as either a user defined Input. Refer to Section 2.0 Pin Description for pin definitions. Of the 6 user defined I/O pins on the SLG46108, all but one of the pins (Pin 2) can serve as both digital input and digital output. Pin 2 can only serve as a digital input pin.

7.1 Input Modes

Each I/O pin can be configured as a digital input p in with/without buffered Schmitt trigger, or can al so be configured as a low voltage digital input.

7.2 Output Modes

Pins 3, 4, 6, 7, and 8 can all be configured as digital output pins.

7.3 Pull Up/Down Resistors

All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors are 10 k Ω , 100 k Ω and 1 M Ω . In the case of Pin 2, the resistors are fixed to a pull-down configuration. In the case of all other I/O pins, the internal resistors can be configured as either pull-up or pull-downs.

7.4 I/O Register Settings

7.4.1 PIN 2 Register Settings

7.4.2 PIN 3 Register Settings

Table 11. PIN 2 Register Settings Table 12. PIN 3 Register Settings

7.4.3 PIN 4 Register Settings

7.4.4 PIN 6 Register Settings

Table 13. PIN 4 Register Settings Table 14. PIN 6 Register Settings

7.4.5 PIN 7 Register Settings

7.4.6 PIN 8 Register Settings

Table 15. PIN 7 Register Settings Table 16. PIN 8 Register Settings

7.5 GPI IO Structure

7.5.1 GPI IO Structure (for Pin 2)

Figure 2. PIN 2 GPI IO Structure Diagram

7.6 Matrix OE IO Structure

7.6.1 Matrix OE IO Structure (for Pin 4, 8)

Figure 3. Matrix OE IO Structure Diagram

7.7 Register OE IO Structure

7.7.1 Register OE IO Structure (for Pins 3, 6, 7)

Figure 4. Register OE IO Structure Diagram

8.0 Connection Matrix

register to select one of these 32 input lines. For a complete list of the SLG46108’s register table, see Section 14.0 Appendix A - SLG46108 Register Definition . Figure 5. Connection Matrix Figure 6. Connection Matrix Example

8.1 Matrix Input Table

Table 17. Matrix Input Table

0 GND 0 0 0 0 0

1 Pin2 digital Input 0 0 0 0 1

2 Pin3 digital Input 0 0 0 1 0

3 Pin4 digital Input 0 0 0 1 1

4 LUT2_0 output (DFF/LATCH_0 output) 0 0 1 0 0

5 LUT2_1 output (DFF/LATCH_1 output) 0 0 1 0 1

6 LUT2_2 output 0 0 1 1 0

7 LUT2_3 output 0 0 1 1 1

8 LUT3_0 output (DFF/LATCH_2 output with nRST or nSE T) 0 1 0 0 0

9 LUT3_1 output (DFF/LATCH_3 output with nRST or nSE T) 0 1 0 0 1

10 LUT3_2 output 0 1 0 1 0

11 LUT3_3 output 0 1 0 1 1

12 LUT3_4 output (pipe delay ouput0) 0 1 1 0 0

13 Pipe delay ouput1 0 1 1 0 1

14 LUT4_0 output (CNT_DLY2 output (8 bit w/ ext CK, reset)) 0 1 1 1 0

15 CNT_DLY0 output (8 bit w/ ext CK (shared with CNT_DLY1 ext

16 CNT_DLY1 output (8 bit w/ ext CK (shared with CNT_DLY0 ext

17 CNT_DLY3(8 bit) output 1 0 0 0 1

18 CNT_DLY3(8 bit) Edge detect output 1 0 0 1 0

19 Programmable delay with edge detector output (deglitch filter out -

22 GND 1 0 1 1 0

23 Resetb_core POR as matrix input 1 0 1 1 1

24 Pin6 digital Input 1 1 0 0 0

25 Pin7 digital Input 1 1 0 0 1

26 Pin8 digital Input 1 1 0 1 0

27 DFF0 nQ output 1 1 0 1 1

28 DFF1 nQ output 1 1 1 0 0

29 DFF2 nQ output 1 1 1 0 1

30 DFF3 nQ output 1 1 1 1 0

31 VDD 1 1 1 1 1

8.2 Matrix Output Table

Table 18. Matrix Output Table

9.0 Combinatorial Logic

Section 10.0 Combination Function Macrocells . devices (AND, NAND, OR, NOR, XOR, XNOR). created within each of the two 2-bit LUT logic cells. Figure 7. 2-bit LUTs Table 21. 2-bit LUT Standard Digital Functions. Table 19. 2-bit LUT2 Truth Table Table 20. 2-bit LUT3 Truth Table

Figure 8. 3-bit LUTs Table 22. 3-bit LUT2 Truth Table Table 23. 3-bit LUT3 Truth Table

created within each of the two 3-bit LUT logic cells. Table 24. 3-bit LUT Standard Digital Functions

10.0 Combination Function Macrocells

The SLG46108 has seven combination function macrocells that can serve more than one logic or timing function. In six of these cases, they can serve as a Look Up Table (LUT), or as another logic or timing function. In the last case, it can serve as either a programmable delay or deglitch filter. See the list below for the functions that can be implemented in these macrocells:

Two macrocells that can serve as either 2-bit LUTs or as DFF/Latch;
Two macrocells that can serve as either 3-bit LUTs or as DFF/Latch;
One macrocell that can serve as either 3-bit LUT o r as Pipe Delay;
One macrocells that can serve as either 4-bit LUTs or as 8-Bit Counter/Delay;
One macrocell that can serve as either a Programma ble Delay or as a Deglitch Filter. Inputs/Outputs for the seven combination function macrocells are configured from the connection matrix with specific logic func - tions being defined by the state of NVM bits. When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR). When used as a D Flip Flop/Latch, the source and destination of the inputs and outputs for the DFF/Latches are configured from the connection matrix. All DFF/Latch macrocells have user selection for initial state, and all have th e option to connect both the Q and nQ outputs to the connection matrix. The macrocells DFF2, DFF3 have an additional input from the matrix that can serve as a nSet or nReset function to the macrocell. The operation of the D Flip-Flop and Latch will follow the functional descriptions below: DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change Latch: if CLK = 1, then Q latches D value 10.1 2-Bit LUT or D Flip Flop Macrocells There are two macrocells that can serve as either 2-bit LUTs or as D Flip Flops. When used to implement LUT functions, the 2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the connection matrix. When used to implement D Flip Flop function, the two input signals from the connection matrix go to the data (D) and clock (CLK) inputs for the Flip Flop, with the output going back to the connection matrix.

Table 27. DFF0 Register Settings Table 28. DFF1 Register Settings Table 25. 2-bit LUT0 Truth Table Table 26. 2-bit LUT1 Truth Table

Table 29. 3-bit LUT0 Truth Table Table 30. 3-bit LUT1 Truth Table

Table 31. DFF2 Register Settings Table 32. DFF3 Register Settings

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay. output, which goes back into the connection matrix. When used as an 8-stage pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CK) and Reset (nRST). set of the OUT0 and OUT1 outputs to a 3-input mux that is controlled by reg <260:258> for OUT0 and reg <263:261> for OUT1. The 3-input MUX is used to control the selection of the amount of delay. be the total time delay of the Pipe Delay logic cell. Figure 13. 3-bit LUT4 or Pipe Delay

8 Flip-Flops IN

Table 34. Pipe Delay Register Settings Table 33. 3-bit LUT4 Truth Table

Note: Counters initialize with counter data after POR. Figure 14. 4-bit LUT1 or CNT/DLY2/FSM0

10.4.1 Counter Mode

Figure 15. Timing (reset rising edge mode, oscillator is forced on) for count data = 3 Figure 16. Timing (reset falling edge mode, oscillator is forced on) for count data = 3 Figure 17. Timing (reset high level mode, oscillator is auto powered on (controlled by reset)) for count data = 3

10.4.2 FSM Mode

Figure 18. Timing (reset rising edge mode, oscillator is forced on, UP = 0) for count data = 3 Figure 19. Timing (set rising edge mode, oscillator is forced on, UP = 0) for count data = 3

Table 36. 4-bit LUT Standard Digital Functions Table 35. 4-bit LUT0 Truth Table.

10.5 Programmable Delay / Edge Detector (PDLY/ Edge Detector)

below for further information. Note : The input signal must be longer than the delay, otherwise it will be filtered out. Table 37. CNT/DLY2 Register Settings Figure 22. Programmable Delay

10.5.1 Programmable Delay Timing Diagram - Edge Detector Output

10.5.2 Programmable Delay Register Settings

Figure 23. Edge Detector Output Table 38. Programmable Delay Register Settings

10.6 Deglitch Filter

one deglitch filter.The typical filtered pulse width is shown in Table 5. Typical Pulse Width Performance . Figure 24. Deglitch Filter

11.0 Counters/Delay Generators (CNT/DLY)

option to chain from the output of the previous (N-1) CNT/DLY macrocell, to implement longer count / delay circuits. more information please see Section 10.4 4-Bit LUT or 8-Bit Counter / Delay Macrocells. Note: Counters initialize with counter data after POR. Figure 25. CNT/DLY0

11.1 CNT/DLY0 Register Settings

11.2 CNT/DLY1 Register Settings

Table 39. CNT/DLY0 Register Settings Table 40. CNT/DLY1 Register Settings

11.3 CNT/DLY3 Register Settings

Table 41. CNT/DLY3 Register Settings

12.0 RC Oscillator (RC OSC)

12.1 RC Oscillator Overview

Note: RC OSC power setting: "Auto Power On”. Figure 28. Maximum Power On Delay vs. VDD, RC OSC = 2 MHz. Figure 29. Maximum Power On Delay vs. VDD, RC OSC = 25 kHz.

Figure 30. below for details of the frequencies for each of these five Connection Matrix Inputs. will be turned off. The PWR DOWN signal has the highest priority.

12.2 RC OSC Block Diagram

Figure 30. RC OSC Block Diagram

12.3 Oscillator Accuracy

Figure 31. RC Oscillator Frequency vs. Temperature, RC OSC = 2 MHz Figure 32. RC Oscillator Frequency vs. Temperature, RC OSC = 25 kHz

13.0 Power On Reset (POR)

The SLG46108 has a power-on reset (POR) macrocell t o ensure correct device initialization and operatio n of all macrocells in the device. The purpose of the POR circuit is to ha ve consistent behavior and predictable results when the VDD power is first ramping to the device, and also while the VDD is fa lling during power-down. To accomplish this goal, the POR drives a defined sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of the I/O pins.

13.1 General Operation

To start the POR sequence in the SLG46108, the volt age applied on the VDD should be higher than the Po wer_ON threshold VDD voltage must ramp up to the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power_ON threshold. After the POR sequ ence has started, the SLG46108 will have a typical period of time to go through all the steps in the sequence (noted in the datasheet for that device), and will be ready and completely operational after the POR sequence is complete. The SLG46108 is guaranteed to be powered down and non-operational when the VDD voltage (voltage on PIN1) is less than 0.6 V, but not less than -0.6 V. Another essential condition for the chip to be powered down is that no voltage higher (see Note 1) than the VDD voltage is applied to any other PIN. For ex ample, if VDD voltage is 0.3 V, applying a voltage higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior. Note 1. There is a 0.5 V margin due to forward drop voltage of the ESD protection diodes. Note 2. The Power_ON threshold can vary by PVT, but typically it is 1.6 V. To power down the chip the VDD voltage should be lo wer than the operational and to guarantee that chip is powered down it should be less than 0.6 V. All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step in the POR sequence releases the I/O structures from the high impedance state, at which time the device is operational. The pin configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.

13.2 POR Sequence

The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 33. . environmental factors, such as: slew rate, VDD value, temperature and even will vary from chip to chip (process influence). Figure 33. POR sequence

13.3 Macrocells Output States During POR Sequence

states during the POR sequence ( Figure 34. describes the output signals states). last are output PINs that become active and determined by the input signals. Figure 34. Internal Macrocell States during POR sequence

14.0 Appendix A - SLG46108 Register Definition

Address Signal Function Register Bit Definition reg <4:0> Pin3 digital out source reg <9:5> Pin4 digital out source reg <14:10> Pin4 output enable reg <19:15> in0 of LUT2_0 (Clock Input of DFF0) reg <24:20> in1 of LUT2_0 (Data Input of DFF0) reg <29:25> in0 of LUT2_1 (Clock Input of DFF1) reg <34:30> in1 of LUT2_1 (Data Input of DFF1) reg <39:35> in0 of LUT2_2 reg <44:40> in1 of LUT2_2 reg <49:45> in0 of LUT2_3 reg <54:50> in1 of LUT2_3 reg <59:55> in0 of LUT3_0 (Clock Input of DFF2 with nReset/nSet) reg <64:60> in1 of LUT3_0 (Data input of DFF2 with n Reset/nSet) reg <69:65> in2 of LUT3_0 (Resetb or Setb of DFF2 with nRe - set/nSet) reg <74:70> in0 of LUT3_1 (Clock Input of DFF3 with nReset/nSet) reg <79:75> in1 of LUT3_1 (Data input of DFF3 with n Reset/nSet) reg <84:80> in2 of LUT3_1 (Resetb or Setb of DFF3 with nRe - set/nSet) reg <89:85> in0 of LUT3_2 reg <94:90> in1 of LUT3_2 reg <99:95> in2 of LUT3_2 reg <104:100> in0 of LUT3_3 reg <109:105> in1 of LUT3_3 reg <114:110> in2 of LUT3_3 reg <119:115> in0 of LUT3_4 (Input of pipe delay) reg <124:120> in1 of LUT3_4 (Resetb of pipe delay) reg <129:125> in2 of LUT3_4 (Clock of pipe delay) reg <134:130> in0 of LUT4_0 (Input for Delay2 ext. clock or Counter2 external Clock) reg <139:135> in1 of LUT4_0 (Input for delay2 or cou nter2 reset input) reg <144:140> in2 of LUT4_0 (Input for counter2 FSM keep signal) reg <149:145> in3 of LUT4_0 (Input for counter2 FSM up signal) reg <154:150> Input for delay0 or counter0 reset inp ut reg <159:155> Input for delay1 or counter1 reset inp ut reg <164:160> Input for Delay 0/1(Counter 0/1) exter nal clock reg <169:165> Input for delay3 or counter3 reset inp ut reg <174:170> Input for programmable delay (deglitch filter input) reg <179:175> Power down for osc. (higher priority) (high = power down). reg <184:180> Pin6 digital out source reg <189:185> Pin7 digital out source

© 2023 Renesas Electronics Corporation Page 58 of 70 SLG46108 Revision 1.14 reg <194:190> Pin8 digital out source reg <199:195> Pin8 output enable reg <207:200> Reserved LUT2 reg <208> DFF0 or Latch select / LUT 2_0 <0> 0: DFF function 1: Latch function reg <210> DFF0 initial polarity select / LUT 2_0 <2> 0: Low 1: High reg <212> DFF1 or Latch select / LUT 2_1 <0> 0: DFF function 1: Latch function reg <214> DFF1 initial polarity select / LUT 2_1 <2> 0: Low 1: High reg <219:216> LUT2_2 data reg <223:220> LUT2_3 data reg <224> LUT2_0 or DFF/Latch_0 select 0: LUT2_0 1: DFF4 reg <225> LUT2_1 or DFF/Latch_1 select 0: LUT2_1 1: DFF5 LUT3 reg <226> DFF2 or Latch select / LUT 3_0 <1> 0: DFF function 1: Latch function reg <228> DFF2 rstb/setb select / LUT 3_0 <3> 0:resetb from matrix output 1:setb from matrix output reg <229> DFF2 initial polarity select / LUT 3_0 <4> 0: Low 1: High reg <234> DFF3 or Latch select / LUT 3_1 <1> 0: DFF function 1: Latch function reg <236> DFF3 rstb/setb select / LUT 3_1 <3> 0: resetb from matrix output 1: setb from matrix output reg <237> DFF3 initial polarity select / LUT 3_1 <4> 0: Low 1: High reg <249:242> LUT3_2 data reg <257:250> LUT3_3 data reg <265:258> LUT3_4 data or pipe number select reg<260:258>: OUT0 select reg<263:261>: OUT1 select reg <266> LUT3_0 or DFF/Latch_2 (with nReset/nSet) s elect 0:LUT3_0 1:DFF2 reg <267> LUT3_1 or DFF/Latch_3 (with nReset/nSet) s elect 0: LUT3_1 1: DFF3 Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 59 of 70 SLG46108 Revision 1.14 reg <268> LUT3_4 or Pipe delay select 0: LUT3_4 1: Pipe delay LUT4 reg <284:269> LUT4_0 data or: reg <269> Counter/delay2 mode selection 0: Delay Mode 1: Counter Mode reg <272:270> Counter/delay2 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter1 Overflow reg <280:273> Counter/delay2 Control Data 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg <282:281> Delay2 Mode Select or asynchronous cou nter reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset for counter mode reg <283> Counter2/FSM2’s Q are set to Data or Reset to 0s se- lection 0: reset to 0 1: set to data reg <285> LUT4_0 or counter_2 select 0: LUT4_0 1: Counter2 OSC reg <286> Force oscillator on 0: Auto Power on 1: Force Power on reg <287> Oscillator frequency control 0: 25 k 1: 2 M reg <289:288> Osc clock pre-divider 00: div1 01: div2 10: div4 11: div8 reg <292:290> internal oscillator divider frequency control 1 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 reg <295:293> internal oscillator divider frequency control 2 000: OSC/1 001: OSC/2 010: OSC/3 011: OSC/4 100: OSC/8 101: OSC/12 110: OSC/24 111: OSC/64 reg <296> External Clock Source Select 0: Internal Oscillator 1: External Clock from Pin8 Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 60 of 70 SLG46108 Revision 1.14 reg <297> Reserved reg <298> OSC Clock 25KHz/2MHz to matrix input <20> enable reg <299> OSC Clock 25KHz/2MHz to matrix input <21> enable reg <300> OSC Fast Start-Up Enable for 25KHz/2MHz CNT/DLY reg <301> Counter/Delay0 (8bits) mode select 0: Delay mode 1: Counter mode reg <302> Reserved reg <305:303> Counter/delay0 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter3 Overflow reg <313:306> Counter0 Control Data/Delay0 Time Cont rol 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg <315:314> Delay0 Mode Select or asynchronous cou nter reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset for counter mode reg <317:316> Reserved reg <318> Counter/Delay1 (8bits) mode select 0: Delay mode 1: Counter mode reg <319> Reserved reg <322:320> Counter/delay1 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter0 Overflow reg <330:323> Counter1 Control Data/Delay1 Time Cont rol 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg <332:331> Delay1 Mode Select or asynchronous cou nter reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset for counter mode reg <334:333> Reserved reg <335> Counter/Delay3 (8bits) mode select 0: Delay mode 1: Counter mode Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 61 of 70 SLG46108 Revision 1.14 reg <338:336> Counter/delay3 Clock Source select (external clock is only for counter mode) 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: Reserved 111: Counter2 Overflow reg <346:339> Counter3 Control Data/Delay3 Time Cont rol 1-255: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg <348:347> Delay3 Mode Select 00: Delay on both falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges PIN 2 reg <350:349> Pin2 Mode control 00: Digital Input without Schmitt trigger 01: Digital Input with Schmitt trigger 10: Low voltage digital input 11: Reserved reg <352:351> Pin2 Pull down resistor value selectio n. 00: Floating 01: 10 K 10: 100 K 11: 1 M PIN 3 reg <355:353> Pin3 Mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved reg <357:356> Pin3 Pull up/down resistor value selec tion. 00: Floating 01: 10 K 10: 100 K 11: 1 M reg <358> Pin3 Pull up/down resistor enable. 0: Pull down resistor enable 1: Pull up resistor enable reg <359> Pin3 Driver strength selection 0: 1X 1: 2X PIN 4 reg <361:360> Pin4 Mode control (sig_pin4_oe = 0) 00: Digital Input without Schmitt trigger 01: Digital Input with Schmitt trigger 10: Low voltage digital input 11: Reserved reg <363:362> Pin4 Mode control (sig_pin4_oe = 1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg <365:364> Pin4 Pull up/down resistor value selec tion. 00: Floating 01: 10 K 10: 100 K 11: 1 M Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 62 of 70 SLG46108 Revision 1.14 reg <366> Pin4 Pull up/down resistor enable. 0: Pull down resistor enable 1: Pull up resistor enable reg <367> Reserved PIN 6 reg <370:368> Pin6 Mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved reg <372:371> Pin6 Pull up/down resistor value selec tion. 00: Floating 01: 10 K 10: 100 K 11: 1 M reg <373> Pin6 Pull up/down resistor enable. 0: Pull down resistor enable 1: Pull up resistor enable reg <374> Pin6 Driver strength selection 0: 1X 1: 2X PIN 7 reg <377:375> Pin7 Mode control 000: Digital Input without Schmitt trigger 001: Digital Input with Schmitt trigger 010: Low voltage digital input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Reserved reg <379:378> Pin7 Pull up/down resistor value selec tion. 00: Floating 01: 10 K 10: 100 K 11: 1 M reg <380> Pin7 Pull up/down resistor enable. 0: Pull down resistor enable 1: Pull up resistor enable reg <381> Pin7 Driver strength selection 0: 1X 1: 2X PIN 8 reg <383:382> Pin8 Mode control (sig_pin8_oe = 0) 00: Digital Input without Schmitt trigger 01: Digital Input with Schmitt trigger 10: Low voltage digital input 11: Reserved reg <385:384> Pin8 Mode control (sig_pin8_oe = 1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg <387:386> Pin8 Pull up/down resistor value selec tion. 00: Floating 01: 10 K 10: 100 K 11: 1 M reg <388> Pin8 Pull up/down resistor enable. 0: Pull down resistor enable 1: Pull up resistor enable reg <390:389> Reserved Register Bit Address Signal Function Register Bit Definition

© 2023 Renesas Electronics Corporation Page 63 of 70 SLG46108 Revision 1.14 Quick Charge reg <391> GPIO quick charge enable 0: Disable 1: Enable Pipe Delay reg <392> Pipe delay OUT1 polarity select bit 0: Non-inverted 1: Inverted Pattern ID reg <400:393> 8-bit pattern id Deglitch Filter reg <401> Deglitch filter out polarity selection 0: Non-inverted 1: Inverted Misc. reg <402> NVM data read disable 0: Disable (read enable) 1: Enable (read disable) reg <403> NVM power down (or NVM data programming di sable) 0: None (or programming enable) 1: Power Down (or programming disable) reg <405:404> Reserved reg <406> Reserved reg <407> Reserved PGM Delay and Edge Detector reg <408> Pin2 Edge Detect Mode 0: Rising edge 1: Falling edge reg <409> Pin2 Bypass the pin2 0: PIN2 edge active 1: PIN2 high active reg <410> PIN2 Reset enable 0: Disable 1: Enable reg <411> Programmable delay or filter output select 0: Programmable delay output 1: Filter output reg <413:412> Select the edge mode of programmable delay with edge detector 00: Rising edge detector 01: Falling edge detector 10: Both edge detector 11: Both edge delay reg <415:414> Delay value select for programmable delay & edge de- tector (VDD = 3.3 V, typical condition) 00: 135 ns 01: 270 ns 10: 405 ns 11: 540 ns reg <423:416> Reserved reg <431:424> Reserved reg <437:432> Reserved reg <439:438> Reserved reg <445:440> Reserved reg <447:446> Reserved reg <448> Reserved reg <449> Reserved reg <450> Reserved reg <451> Reserved reg <455:452> Reserved Register Bit Address Signal Function Register Bit Definition

15.0 Package Top Marking System Definition

Note: The SN Code (Line 1 and Line 2) is generated during production, and encodes information includin g part number, programming code number, date code and lot code. This same information is provided in plain text form on a label placed on the reel. If you need assistance in decoding the SN Code, please contact Renesas Electronics Corporation. Pin 1 Identifier NN Serial Number Code Line 1 Serial Number or Part Code Line 2* PPNN * PP may consist of the special characters +, -, and = for a total of 9 different combinations, or may consist of two character alphanumeric Part Code (A-Z and 0-9), depending on time of marking.

16.0 Package Drawing and Dimensions

8 Lead STQFN Package 1.0 x 1.2 mm IC net weight: 0.0017 g

17.0 Tape and Reel Specifications

17.1 Carrier Tape Drawing and Dimensions

# of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 8L 0.4P FC Green 8 1.0x1.2x0.55 3000 3000 178/60 100 400 100 400 8 4 Package Type Pocket BTM Length [mm] Pocket BTM Width [mm] Pocket Depth [mm] Index Hole Pitch [mm] Pocket Pitch [mm] Index Hole Diameter [mm] Index Hole to Tape Edge [mm] Index Hole to Pocket Center [mm] Tape Width [mm] A0 B0 K0 P0 P1 D0 E F W STQFN 8L 0.4P FC Green

18.0 Recommended Land Pattern

19.0 Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 0.66 mm 3 (nominal). More information can be found at www.jedec.org.

20.0 Revision History

Renesas Electronics Corporation’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous sub stances in electrical and electronic equipment. RoH S certificates from our suppliers are available on request. Date Version Change 3/9/2023 1.14 Added notes to section Ordering Informa tion 3/4/2022 1.13 Updated R PUP and R PDWN in section Electrical Specifications Renesas rebranding Updated tables CNT/DLY Register Settings Corrected registers [280:273], [313:306], [330:323], [346:339] in Appendix A - SLG46108 Register Definition 8/25/2020 1.12 Updated figure Internal Macrocell States during POR sequence Added note for CNTs Corrected registers [346:336], [330:320], [313:303], [280:270] 7/11/2019 1.11 Corrected Absolute Maximum Conditions Corrected Appendix A Fixed typos 11/13/2018 1.10 Updated to Dialog style Updated Marking Spec Fixed typos 5/10/2018 1.09 Fixed typos 10/27/2017 1.08 Updated OSC Electrical Spec 10/9/2017 1.07 Updated Electrical Spec Fixed typos 8/10/2017 1.06 Fixed typos 7/28/2017 1.05 Corrected Pin Structure Diagrams Fixed typos 7/5/2017 1.04 Fixed typos Updated Silego Website & Support Updated Section Programmable Delay / Edge Detector Updated Landing Pattern Updated Electrical Spec 8/31/2016 1.03 Updated OSC Specifications 7/27/2016 1.02 Updated Programmable Delay for clarification Clarified Electrical Characteristics Table conditions Simplified IDD Estimator table Fixed RC Oscillator descriptions Added Note to Package Marking 7/1/2016 1.01 Final clean up 6/15/2016 1.00 Production Release 5/19/2016 0.50 Preliminary Release

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Selected Specification

Renesas Technology Corp SLG46108 overview.

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Summary

Ultra-small Programmable Mixed-signal Matrix March 9, 2023

Description

Ultra-small Programmable Mixed-signal Matrix March 9, 2023

Source title SLG46108 Datasheet(PDF) - Renesas Technology Corp

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