SL74HC166 SLS
Document overview
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Technical content
8-Bit Serial or Parallel -Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS The SL74HC166 is identical in pinout to the LS/ALS166. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device is a parallel -in or serial-in, serial-out shift register with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel -in or serial -in mode. When high, this input enables the serial data input and couples the eight flip -flops for serial shifting with each clock pulse. Synchronous loading occurs on the next clock pulse whe n this is low and the parallel data inputs are enabled. Serial data flow is inhibited during parallel loading. Clocking is done on the low -to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with th e other clock input. A change from low -to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, andsets all flip -flop to zero.
- Outputs Directly Interface to CMOS, NMOS, and TTL
- Operating Voltage Range: 2.0 to 6.0 V
- Low Input Current: 1.0 µA
- High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16 =VCC PIN 8 = GND
MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ 750 500 mW Tstg Storage Temperature -65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260 °C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types -55 +125 °C tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high -impedance circuit. For proper operation, V IN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter Test Conditions V 25 °C to -55°C ≤85 ≤125 Unit VIH Minimum High-Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 8.0 80 160 µA FUNCTION TABLE Inputs Internal Outputs Output Clear Shift/Load Clock Inhibit Clock SA Parallel A...H QA QB QH L X X X X X L L L H X X X X No change H L L X a...h a b h H H L H X H QAn QGn H H L L X L QAn QGn H X H X X X No change X = don’t care a...h = the level of steady state input voltage at input A trough H respectively
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit fmax Minimum Clock Frequency (50% Duty Cycle) (Figures 2 and 4) 2.0 4.5 6.0 6.0 5.0 4.2 MHz tPLH, tPHL Maximum Propagation Delay, Clock (or Clock Inhibit) to QH (Figures 2,3 and 4) 2.0 4.5 6.0 140 175 210 ns tPHL Maximum Propagation Delay , Clear to QH (Figures 1 and 4) 2.0 4.5 6.0 150 200 230 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 4.5 6.0 110 ns CIN Maximum Input Capacitance - 10 10 10 pF Power Dissipation Capacitance (Per Package) Typical @25°C,VCC=5.0 V CPD Used to determine the no -load dynamic power consumption: PD=CPDVCC 2f+ICCVCC 140 pF TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns) VCC Guaranteed Limit Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit tsu Minimum Setup Time, Shift/Load to Clock (Figure 3) 2.0 4.5 6.0 100 120 ns tsu Minimum Setup Time, Data before Clock (or Clock Inhibit) (Figure 3) 2.0 4.5 6.0 100 120 ns tw Minimum Pulse Width, Clock (or Clock Inhibit) (Figure 2) 2.0 4.5 6.0 100 120 ns