SL4502B SLS

Document overview

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Technical content

Strobed Hex Inverter/Buffer High-Voltage Silicon-Gate CMOS The SL4502B consists of six inverter/buffers with 3-state outputs. A logic “1” on the OUTPUT ENABLE input produces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A logic “1” on the DIRECTION input switches all six outputs to logic “0” if the OUTPUT ENABLE input is a logic “0”.

  • Operating Voltage Range: 3.0 to 18 V
  • Maximum input current of 1 µA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply

ORDERING INFORMATION

TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN 16=VCC PIN 8= GND PIN ASSIGNMENT FUNCTION TABLE Inputs Output Output Enable Direction A Y L L L H L L H L L H X L H X X Z Z = high impedance X = don’t care

MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin ±10 mA PD Power Dissipation in Still Air, Plastic DIP+ 750 500 mW PD Power Dissipation per Output Transistor 100 mW Tstg Storage Temperature -65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260 °C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 3.0 18 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types -55 +125 °C This device c ontains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high -impedance circuit. For proper opera tion, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125 Unit VIH Minimum High-Level Input Voltage VOUT=0.5 V VOUT=1 V VOUT=1.5 5.0 3.5 3.5 3.5 V VIL Maximum Low -Level Input Voltage VOUT= VCC - 0.5V VOUT= VCC - 1.0 V VOUT= VCC - 1.5V 5.0 1.5 1.5 1.5 V VOH Minimum High-Level Output Voltage VIN=GND 5.0 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 V VOL Maximum Low-Level Output Voltage VIN= VCC 5.0 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V IIN Maximum Input Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 120 600 µA IOL Minimum Output Low (Sink) Current VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V 5.0 3.84 9.6 25.2 3.06 7.8 20.4 2.16 5.4 14.4 mA IOH Minimum Output High (Source) Current VIN= GND or VCC UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 5.0 5.0 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 mA IOZ Maximum Tree-State Leakage Current Output in High-Impedance State VIN= GND or VCC VOUT= GND or VCC

AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200kΩ unless otherwise specified, Input tr=tf=20 ns) VCC Guaranteed Limit Symbol Parameter V ≥-55°C 25°C ≤125°C Unit tPHL Maximum Propagation Delay, Input A or Direction to Output Y (Figure 1) 5.0 270 120 270 120 540 240 160 ns tPLH Maximum Propagation Delay, Input A or Direction to Output Y (Figure 1) 5.0 380 180 130 380 180 130 760 360 260 ns tPHZ Maximum Propagation Delay, Output Enable to Output Y (Figure 2) RL = 1 kΩ 5.0 120 120 240 160 120 ns tPZH Maximum Propagation Delay, Output Enable to Output Y (Figure 2) RL = 1 kΩ 5.0 220 100 220 100 440 200 160 ns tPLZ Maximum Propagation Delay, Output Enable to Output Y (Figure 2) RL = 1 kΩ 5.0 250 130 110 250 130 110 500 260 220 ns tPZL Maximum Propagation Delay, Output Enable to Output Y (Figure 2) RL = 1 kΩ 5.0 250 110 250 110 500 220 160 ns tTLH Maximum Output Transition Time, Any Output (Figure 1) 5.0 200 100 200 100 400 200 160 ns tTHL Maximum Output Transition Time, Any Output (Figure 1) 5.0 120 120 240 120 ns CIN Maximum Input Capacitance - 7.5 pF COUT Maximum Tree-State Output Capacitance (Output in High-Impedance State) - 15 pF

Figure 1. Switching Waveforms Figure 2. Switching Waveforms