SL4013B SLS

Document overview

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Technical content

High-Voltage Silicon-Gate CMOS The SL4013B consists of two identical, independent data-type flip- flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively.

  • Operating Voltage Range: 3.0 to 18 V
  • Maximum input current of 1 µA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply

ORDERING INFORMATION

TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN 14 =VCC PIN 7 = GND PIN ASSIGNMENT FUNCTION TABLE Inputs Outputs Clock Data Reset Set Q Q L L L L H H L L H L X L L Q Q X X H L L H X X L H H L X X H H H H X = don’t care

MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin ±10 mA PD Power Dissipation in Still Air, Plastic DIP+ 750 500 mW PD Power Dissipation per Output Transistor 100 mW Tstg Storage Temperature -65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260 °C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 3.0 18 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types -55 +125 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125 Unit VIH Minimum High-Level Input Voltage VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V 5.0 3.5 3.5 3.5 V VIL Maximum Low -Level Input Voltage VOUT=0.5 V or VCC - 0.5 V VOUT=1.0 V or VCC - 1.0 V VOUT=1.5 V or VCC - 1.5 V 5.0 1.5 1.5 1.5 V VOH Minimum High-Level Output Voltage VIN=GND or VCC 5.0 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 V VOL Maximum Low-Level Output Voltage VIN=GND or VCC 5.0 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 V IIN Maximum Input Leakage Current VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN= GND or VCC 5.0 120 600 µA IOL Minimum Output Low (Sink) Current VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V 5.0 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 Ma IOH Minimum Output High (Source) Current VIN= GND or VCC UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V 5.0 5.0 -2.0 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 Ma

AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200 kΩ , Input tr=tf=20 ns) VCC Guaranteed Limit Symbol Parameter V ≥-55°C 25°C ≤125°C Unit fmax Maximum Clock Frequency (Figure 1) 5.0 3.5 3.5 1.75 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q or Q (Figure 1) 5.0 300 130 300 130 600 260 180 ns tPLH Maximum Propagation Delay, Set to Q or Reset to Q (Figure 2) 5.0 300 130 300 130 600 260 180 ns tPHL Maximum Propagation Delay, Set to Q or Reset to Q (Figure 2) 5.0 400 170 120 400 170 120 800 340 240 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figure 1) 5.0 200 100 200 100 400 200 160 ns CIN Maximum Input Capacitance - 7.5 pF TIMING REQUIREMENTS(CL=50pF, RL=200 kΩ , Input tr=tf=20 ns) VCC Guaranteed Limit Symbol Parameter V ≥-55°C 25°C ≤125°C Unit tw Minimum Pulse Width, Clock (Figure 1) 5.0 140 140 280 120 ns tw Minimum Pulse Width, Set or Reset (Figure 2) 5.0 180 180 360 160 100 ns tsu Minimum Setup Time, Data to Clock (Figure 3) 5.0 ns th Minimum Hold Time, Clock to Data (Figure 3) 5.0 ns tr, tf Maximum Input Rise or Fall Time, Clock (Figure 5.0 500 500 1000 µs