SL1461MPAS

SL1461 ETC2

Document overview

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Technical content

D.S. 3754 1.6 SL1461 WIDEBAND PLL FM DEMODULATOR The SL1461 is a wideband PLL FM demodulator, intended primarily for application in satellite tuners. The device contains all elements necessary, with the exception of external oscillator sustaining network and loop feedback components, to form a complete PLL system operating at frequencies up to 800MHz. An AFC with window adjust is provided, whose output signal can be used to correct for any frequency drift at the head end local oscillator.

FEATURES

Single chip PLL system for wideband FM demodulation Simple low component count application Allows for application of threshold extension Fully balanced low radiation design High operating input sensitivity AGC detect and bias adjust 75 video output drive with low distortion levels Dynamic self biasing analog AFC Full ESD protection * * Normal ESD handling procedures should be observed 1611 6 7 10 AFC PUMP AFC WINDOW ADJUST V EE OSCILLATOR + OSCILLATOR – AGC BIAS AGC OUTPUT RF INPUT AFC OUTPUT V CC VIDEO FEEDBACK + VIDEO – VIDEO + VIDEO FEEDBACK – VIDEO OUTPUT RF INPUT MP16 Fig. 1 Pin connections top view SL1461S

APPLICATIONS

Satellite receiver systems Data communications systems ORDERING INFORMA TION SL1461S/KG/MPAS AGC BIAS RF INPUTS AGC OUTPUT LOCAL OSCILLATOR AFC WINDOW ADJUST VIDEO FEEDBACK + VIDEO + VIDEO – FEEDBACK – VIDEO OUTPUT AFC PUMP AFC OUTPUT Fig. 2 SL1461 block diagram VIDEO

ELECTRICAL CHARACTERISTICS

Tamb =–20°C to 80°C, VCC =4.5V to 5.5V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristics Value Units ConditionsCharacteristics Min Typ Max Units Conditions Supply current 36 40 mA Operating frequency 300 800 MHz Input sensitivity –40 dBm Preamp limiting Input overload 0 dBm VCO sensitivity (dF/dV) 25 32 39 MHz/V Refer to application in Fig. 3a VCO linearity .25 % Refer to application in Fig. 3a; with 13.5MHz p–p deviation Phase detector gain 0.5 0.25 V/rad V/rad Differential loop filter Single ended loop filter Loop amplifier input impedance 450 570 700 /C0087Single ended Loop amplifier output impedance 25 /C0087Single ended Loop amplifier open loop gain 38 dB Single ended Loop amplifier gain bandwidth product

240 MHz Single ended

Loop amplifier output swing 1.2 Vp–p Single ended Video drive output impedance 55 75 95 /C0087 Video drive; Luminance nonlinearity 1.9 5 % /C0049/C0075/C0087 load, See note 3 & 4 – differential gain 0.5 2.5 % 75/C0087 load, See note 3 & 4 – differential phase 1.0 3 Degree 75/C0087 load, See note 3 & 4 – intermodulation –40 dB See notes 1+3 & 4 – Signal/noise 66 72 dB /C0049/C0075/C0087 load, See note 2 & 4 –Tilt 0.3 3 % /C0049/C0075/C0087 load, See note 3 & 4 – baseline distortion 0.4 2 % /C0049/C0075/C0087 load, See note 3 & 4 AGC output current 10 400 /C0109A Maximum load voltage drop 2V AGC bias current 0 250 /C0109A AFC window current 0 400 /C0109A 400 /C0109A gives 1.5V deadband window AFC charge pump current 50 /C0109A AFC leakage current 10 /C0109A With charge pump disabled AFC output saturation voltage 0.4 V AFC output enabled Note 1.Product of input modulation f1 at 4.43MHz, 13.5MHz p–p deviation and f2 at 6MHz p–p deviation, (PAL chroma and sound subcarriers). Note 2.Ratio of output video signal with input modulation at 1MHz, 13.5MHz p–p deviation, to output rms noise in 6MHz bandwidth with no input modulation. Note 3 Input test signal pre–emphasised video 13.5MHz p–p deviation. Output voltage 600mV pk–pk. Note 4 See page 3

TEST CONFIGURA TION BASE BAND VIDEO 1V p–p VIDEO GENERATOR ROHDE & SCHW ARZ SGPF TV SAT TEST TX ROHDE & SCHW ARZ SFZ RF CARRIER FREQ 479.5MHz FM MODULA TION 13.5MHz P–P PRE–EMPHASISED VIDEO MONTFORD TEST OVEN SL1461 TEST APPLICATION BOARD See Fig. 3a for details PRE EMPHASISED BASE BAND VIDEO VIDEO AMPLIFIER/ DE EMPHASISED NETWORK DE EMPHASISED BASE BAND VIDEO 1V p–p VIDEO ANALYSER ROHDE & SCHW ARZ UAF The video drive characteristics measurements were made using the above test configuration. The maximum figures recorded in the Electrical Characteristics Table coincide with high temperatures and extremes of supply voltage. No adjustment to the recorded figures has been made to compensate for the effects of temperature on the external components of the application test board, in particular the varactor diodes. If operation of the device at high ambient temperatures is envisaged then attention to temperature compensation of the external circuitry will result in performance figures closer to the stated typical figures. Note 4. ABSOLUTE MAXIMUM RA TINGS All voltages are referred to VEE at 0V. Characteristic Min Max Units Conditions Supply voltage –0.3 7 V RF input voltage 2.5 V p–p RF input DC offset –0.3 VCC +0.3 V Oscillator +&–DC offset –0.3 VCC +0.3 V Video +&–DC offset –0.3 VCC +0.3 V Video feedback +&–DC offset –0.3 VCC +0.3 V Video output DC offset –0.3 VCC +0.3 V AFC pump DC offset –0.3 VCC +0.3 V AFC disable DC offset –0.3 VCC +0.3 V AFC deadband DC offset –0.3 VCC +0.3 V AGC bias DC offset –0.3 VCC +0.3 V AGC output DC offset –0.3 VCC +0.3 V Storage temperature –55 125 °C Junction temperature 150 °C MP16 package thermal resistance, chip to ambient 111 °C/W

ABSOLUTE MAXIMUM RA TINGS cont. All voltages are referred to VEE at 0V. MP16 package thermal resistance chip to case 41 °C/W Power consumption at 5.5V 250 mW ESD protection – pins 1 to 15 2 kV Mil–std –883 method 3015 class1 ESD protection – pin 16 1.7 kV Mil–std –883 method 3015 class1 1611 6 7 10 SL1461S AGC BIAS AFC WINDOW ADJUST 50K 27K 100nF 47/C0109F V 47nF 100nF BB833 22pF 22pF 5K1 4n7 4K7 1nF RF INPUT 1nF 47/C0109F 1K2 120pF 1K2 120pF Fig.3. Standard application circuit with oscillator referenced to ground 4K7 BB833 CC VIDEO OUTPUT 1611 6 7 10 SL1461S AGC BIAS AFC WINDOW ADJUST 50K 27K 100nF 47/C0109F V 47nF 100nF BB833 5K1 4n7 4K7 1nF RF INPUT 1nF 47/C0109F 1K2 1K2 82pF 4K7 BB833 CC VIDEO OUTPUT 220R Fig.3a Application circuit used for video drive characterisation measurements 82pF 620R

The SL1461 is a wideband PLL FM demodulator, optimised for application in satellite receiver systems and requiring a minimum external component count. It contains all the elements required for construction of a phase locked loop circuit, with the exception of tuning components for the local oscillator, and an AFC detector circuit for generation of error signal to correct for any frequency drift in the outdoor unit local oscillator. A block diagram is contained in Fig. 2 and the typical application in Fig. 3. The internal pin connections are contained in Fig.6/6a. In normal applications the second satellite IF frequency of typically 402 or 479.5MHz is fed to the RF preamplifier, which has a working sensitivity of typically –40 dBm, depending on application and layout. The preamplifier contains an RF level detect circuit, which generates an AGC signal that can be used for controlling the gain of the IF amplifier stages, so maintaining a fixed level to the RF input of the SL1461, for optimum threshold performance. The bias point of the AGC circuit can be adjusted to cater for variation in AGC line voltage requirement and device input power. The typical AGC curves are shown in Fig. 9. The output of the preamplifier is fed to the mixer section which is of balanced design for low radiation. In this stage the RF signal is mixed with the local oscillator frequency, which is generated by an on–board oscillator. The oscillator block uses an external varactor tuned sustaining network and is optimised for high linearity over the normal deviation range. A typical frequency versus voltage characteristic for the oscillator is contained in Fig. 7. The loop output is designed to compensate for first order temperature variation effects; the typical stability is shown in Fig. 8 The output of the mixer is then fed to the loop amplifier around which feedback is applied to determine loop transfer characteristic . Feedback can be applied either in differential or single ended mode; if the appropriate phase detector gains are assumed in calculating loop filters, both modes should give the same loop response. The loop amplifier drives a 75 output impedance buffer amplifier, which can either be connected to a 75 load or used to drive a high input impedance stage giving greater linearity and approximately 6dB higher demodulated signal output level. DESIGN OF PLL LOOP PARAMETERS Fig. 4 VCO R2 C1 BASEBAND OUTPUTR1RF INPUT GAIN = K0 RAD SEC/VOL T GAIN = KD VOLT/RAD The SL1461 is normally used as a type 1 second order loop and can be represented by the above diagram. For such a system the following parameters apply; /C01161 /C0043/C0067/C0082 /C01162 /C0043/C0067/C0082 /C01161 /C0043K 0K D /C01192 n /C01162 /C00432/C0122 /C0119n and where: K0 is the VCO gain in radian seconds per volt KD is the phase detector gain in volts per radian /C0119n is the natural loop bandwidth /C0122 is the loop damping factor R1 is loop amplifier input impedance Note: KO is dependant on sensitivity of VCO used. KD = 0.25V/rad single ended, 0.5V/rad differential From these factors the loop 3dB bandwidth can be determined from the following expression; /C0119 /C0043/C0119 /C0122 /C0041 /C0034/C0119 /C0041 /C0041/C0504 /C0119 /C0043/C0119/C0122/C0043 /C0504 /C0099

The SL1461 contains an analog frequency error detect circuit, which generates DC voltage proportional to the integral of frequency error. If the incident RF is high then the AFC voltage increases, if low then the voltage decreases. The AFC voltage can then be converted by an ADC to be read by the micro controller for frequency fine tuning; if used in an I2C system it is recommended the device is used with either the SP5055 or SP5056 frequency synthesiser which contains an internal ADC readable via the I2C bus. The voltage corresponding to frequency alignment is arbitrary and user defined; if used with the SP5055 it is suggested the aligned voltage is 0.375 VCC , corresponding to the centre code of the ADC on port 6. The AFC detect circuit contains a deadband centred around the aligned frequency. The deadband can be adjusted from zero window to approximately 25MHz width assuming an oscillator dF/dV of 15MHz/V. If the incident RF is within this window the AFC voltage does not integrate, except by component leakage. With reference to Fig.5; in normal operation the demodulated video is fed to a dual comparator where it is compared with two reference voltages, corresponding to the extremes of the deadband, or window. These voltages are variable and set by the window adjust input. The comparators produce two digital outputs corresponding to voltages above or below the voltage window, or frequency above or below deadband. These digital control signals are used to control a complimentary current source pump. The current signals are then fed to the input of an amplifier which is arranged as an integrator, so integrating the pulses into a DC voltage. If the frequency is correctly aligned both the current source and sink are disabled, therefore the DC output voltage remains constant. There will be a small drift due to component leakage; the maximum drift can be calculated from; /C0100/C0086 /C0100/C0116/C0043/C0073 /C0050/C0053/C0048/C0048/C0046/C0067/C0119/C0104/C0101/C0114/C0101/C0258/C0258/C0258/C0073/C0043/C0086/C0067/C0067 /C0082/C0069/C0088/C0084 /C0258/C0044/C0258/C0258 /C0067/C0043/C0067/C0069/C0088/C0084 WINDOW ADJUST HIV LOV V ALIGN FREQ BASEBAND VIDEO VCC VCC VEE C EXT EXTR V AFC Fig. 5 AFC system block diagram

VREF; 2.7V AGC output VREF; 2V AGC BIAS AGC bias adjust AFC window adjustRF inputs VREF; 3V 2x1500 RF INPUTS VREF; 1.6V AFC WINDOW Fig.6 SL1461 I/O port internal circuitry AFC output stage VCC AFC PUMP AFC OUTPUT Video amp outputs VIDEO + VIDEO –330 330 2mA 2mA 10K

FEEDBACK – 2 x 5k VREF; 2.5V OSCILLAT OR + OSCILLAT OR – Video output drive VCC OUTPUT 105 4mA Fig. 6a SL1461 I/O port internal circuitry VIDEO 520 500 480 460 440 420 400 360 1 1.5 2 2.5 3 3.5 4 4.5 5 Fig. 7 Typical VCO frequency vs DC control voltage Fig. 8 SL1461 VCO centre frequency uncompensated temperature stability. 482 481 480 479 478 –20 20 80 FREQ MHz DC VOL TAGE FREQ MHz TEMP/ °C FROM PHASE DETECT OR

2.0 1.5 1.0 0.5 V CC VOLTAGE RF INPUT LEVEL (dBm) UNMODULA TED Fig.9 SL1461 AGC output voltage for differing values of AGC bias resistor OUTPUT AGC BIAS RESISTOR 5.1K AGC BIAS CURRENT 297 /C0109A AGC LOAD RESIST OR 3.9K AGC BIAS RESIST OR 10.5K AGC BIAS CURRENT 150 /C0109A AGC LOAD RESIST OR 4.7K AGC BIAS RESIST OR 32K AGC BIAS CURRENT 52 /C0109A AGC LOAD RESIST OR 10K = 5.0 VOLTS APPLICATION NOTES Capture range Under conditions when there is no RF input signal present, the SL1461 may react to spurious radiation from the free running oscillator coupling into the RF inputs. Because of the constant phase error between the VCO input to the phase detector and the spuriously coupled signal via the RF input, the phase comparator will drive the control voltage to either the bottom or the top of the range. In such a case, the capture range will be asymmetrical about the VCO free running frequency, since any control voltage will only be able to tune the VCO in one direction if the tuning voltage is already at the max or min. This effect can be avoided by driving the RF input differentially or achieving good common mode rejection to the VCO signal. The lock range is independant of the above effects and will be symmetric about the centre of the phase detector S–curve provided the VCO is correctly aligned. EXAMPLE Loop out of lock Tuning voltage =4.3V (maximum) frequency =520MHz (maximum It is only possible to capture signals below this frequency since the VCO is already at its maximum frequency. Testing of capture range should be done with the device operating under normal conditions. An input signal of between –35dBm to –10dBm is suitable for such a measurement. Lock range Lock range should be symmetric about the centre of the S–curve. When the oscillator is sitting in the centre of the S–curve, the two video outputs will be at the same DC voltage. RF oscillator design The standard application circuit for the SL1461 is shown in Fig.3 The layout of the VCO tank should follow normal good RF techniques – ie as compact as possible. This will minimise parasitics, thus giving improved VCO linearity and stability. The PCB layout used for testing purpose is shown in Fig. 11. Setting up of oscillator The VCO should be set up so that the desired input RF frequency is at the centre of the lock range. This will coincide with the centre of the S–curve and the point at which the AFC toggles when set to zero deadband. The easiest way to centralise the VCO is to input an RF carrier which is being modulated by a low frequency squarewave. The tuning coil(s) should be adjusted until the AFC voltage toggles between 0.2V and VCC–0.7V. The smaller the FM deviation of the squarewave used, the more accurate the setting will be. A pre–emphasised video input containing black to white transitions can also be used for this setting, since the DC content in a pre–emphased video is much less than that in non pre–emphasised video. This is important as any dc content in the input waveform will introduce an offset in the AFC transition point. The setting can be confirmed by measuring the DC voltage on the two video outputs, the voltages should be the same when the oscillator is centred around the incoming frequency. This DC measurement must be carried out with an unmodulated carrier of the required frequency. Modulation must not be present, since by definition, the dc voltages would be changing, thus making accurate measurement difficult.

shown in Fig. 3. TP1=VIDEO – TP2=VIDEO + TP3=AGC O/P TP4=AFC O/P All surface mount components mounted on underside of board Fig. 11 Layout of demo board with oscillator referenced to GND

Dimensions are shown thus: mm (in). For further package information please contact your local Customer Service Centre. 0.35/0.49 9.80/10.01 0.69 (0.027) MAX 3.80/4.00 1.27 (0.050) NOM 0.41/1.27 0.10/0.25 1.35/1.91 5.80/6.20 0.25/0.51 0.19/0.25/C0056

16 LEAD MINIATURE PLASTIC MP16

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