SE555

xx555 Precision Timers datasheet (Rev. K)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SLFS022,K]
• PDF pages: 39

Technical content

1 Features

• Timing from microseconds to hours
• Astable or monostable operation
• Adjustable duty cycle
• TTL-compatible output can sink or source up to 200mA
• On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

2 Applications

• Pulse-shaping circuits
• Missing-pulse detectors
• Pulse-width modulators
• Pulse-position modulators
• Sequential timers
• Pulse generators
• Frequency dividers
• Industrial controls S R TRIG THRES VCC CONT RESET OUT DISCH GND Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Simplified Schematic

3 Description

The Nx555 and Sx555 devices are precision timing circuits capable of producing accurate time delays or oscillation. In time-delay or monostable operating modes, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle are controlled independently with two external resistors and a single external capacitor. Each timer has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage pin (CONT). When the trigger input (TRIG) is less than the trigger level, the flip-flop is set and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) overrides all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low- impedance path is provided between the discharge pin (DISCH) and the ground pin (GND). Tie all unused inputs to an appropriate logic level to prevent false triggering The output circuit is capable of sinking or sourcing current up to 200mA. Operation is specified for supplies of 5V to 15V. With a 5V supply, output levels are compatible with TTL inputs. Device Information PART NUMBER OPERATING TEMPERATURE PACKAGE(1) NA555 TA = –40°C to +105°C D (SOIC, 8) P (PDIP, 8) NE555 TA = 0°C to 70°C D (SOIC, 8) P (PDIP, 8) PS (SO, 8) PW (TSSOP, 8) SA555 TA = –40°C to +85°C D (SOIC, 8) P (PDIP, 8) SE555 TA = –55°C to +125°C D (SOIC, 8) FK (LCCC, 20) JG (CDIP, 8) P (PDIP, 8) (1) For more information, see Section 10. NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

V CC NC NC RESET NC NC – No internal connection NA555...D OR P PACKAGE NE555...D, P, PS, OR PW PACKAGE SA555...D OR P PACKAGE SE555...D, JG, OR P PACKAGE (TOP VIEW) SE555...FK PACKAGE (TOP VIEW) Table 4-1. Pin Functions PIN TYPE DESCRIPTION NAME NO. D (SOIC), P (PDIP), PS (SO), PW (TSSOP), JG (CDIP) FK (LCCC) CONT 5 12 Input/output Controls comparator thresholds, Outputs 2/3 × VCC, allows bypass capacitor connection DISCH 7 17 Output Open collector output to discharge timing capacitor GND 1 2 — Ground NC — 1, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 19 — No internal connection OUT 3 7 Output High current timer output signal RESET 4 10 Input Active low reset input forces output and discharge low. THRES 6 15 Input End of timing input. THRES > CONT sets output low and discharge low TRIG 2 5 Input Start of timing input. TRIG < ½ CONT sets output high and discharge open VCC 8 20 — Input supply voltage, 4.5V to 16V. SE555 maximum is 18V. www.ti.com NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: NA555 NE555 SA555 SE555

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage(2) 18 V VI Input voltage CONT, RESET, THRES, TRIG VCC V IO Output current ±225 mA TJ Operating virtual junction temperature 150 °C Case temperature for 60 seconds FK package 260 °C Lead temperature 1.6mm (1/16 inch) from case JG package, 60 seconds 300 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltage values are with respect to GND.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±500 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002 (2) ±1500 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage NA555, NE555, SA555 4.5 16 V SE555 4.5 18 IO Output current ±200 mA TA Operating free-air temperature NA555 –40 105 NE555 0 70 SA555 –40 85 SE555 –55 125 NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 www.ti.com

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5.4 Thermal Information

(1) NA556, NE556, SA555, SE555 SE555 NA555, NE555 NE555 UNIT D (SOIC) FK (LCCC) JG (CDIP) P (PDIP) PS (SO) PW (TSSOP)

8 PINS 20 PINS 8 PINS 8 PINS 8 PINS 8 PINS

ψJT Junction-to-top characterization ψJB Junction-to-board characterization RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 14.2 29.3 N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report.

5.5 Electrical Characteristics

at VCC = 5V to 15V and TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THRES voltage level VCC = 15V NA555, NE555, SA555 8.8 10 11.2 V SE555 9.4 10 10.6 VCC = 5V NA555, NE555, SA555 2.4 3.3 4.2 SE555 2.7 3.3 4 THRES current(1) 30 250 nA TRIG voltage level VCC = 15V NA555, NE555, SA555 4.5 5 5.6 V SE555 4.8 5 5.2 VCC = 15V, TA = –55°C to +125°C SE555 3 6 VCC = 5V NA555, NE555, SA555 1.1 1.67 2.2 SE555 1.45 1.67 1.9 VCC = 5V, TA = –55°C to +125°C SE555 1.9 TRIG current TRIG at 0V NA555, NE555, SA555 0.5 2 μA SE555 0.5 0.9 RESET voltage level 0.3 0.7 1 V TA = –55°C to +125°C SE555 1.1 RESET current RESET at VCC 0.1 0.4 mA RESET at 0V NA555, NE555, SA555 –0.4 –1.5 SE555 –0.4 –1 DISCH switch off-state current 20 100 nA DISCH switch on-state voltage VCC = 5V, IO = 8mA NA555, NE555, SA555 0.15 0.4 V www.ti.com NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: NA555 NE555 SA555 SE555

5.5 Electrical Characteristics (continued)

at VCC = 5V to 15V and TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CONT voltage (open circuit) VCC = 15V NA555, NE555, SA555 9 10 11 V SE555 9.6 10 10.4 VCC = 15V, TA = –55°C to +125°C SE555 9.6 10.4 VCC = 5V NA555, NE555, SA555 2.6 3.3 4 SE555 2.9 3.3 3.8 VCC = 5V, TA = –55°C to +125°C SE555 2.9 3.8 Low-level output voltage VCC = 15V, IOL = 10mA NA555, NE555, SA555 0.1 0.25 V SE555 0.1 0.15 VCC = 15V, IOL = 10mA, TA = –55°C to +125°C SE555 0.2 VCC = 15V, IOL = 50mA NA555, NE555, SA555 0.4 0.75 SE555 0.4 0.5 VCC = 15V, IOL = 50mA, TA = –55°C to +125°C SE555 1 VCC = 15V, IOL = 100mA NA555, NE555, SA555 2 2.5 SE555 2 2.2 VCC = 15V, IOL = 100mA, TA = –55°C to +125°C SE555 2.7 VCC = 15V, IOL = 200mA 2.5 VCC = 5V, IOL = 3.5mA, TA = –55°C to +125°C SE555 0.35 VCC = 5V, IOL = 5mA NA555, NE555, SA555 0.1 0.35 SE555 0.1 0.2 VCC = 5V, IOL = 5mA, TA = –55°C to +125°C SE555 0.8 VCC = 5V, IOL = 8mA NA555, NE555, SA555 0.15 0.4 SE555 0.15 0.25 High-level output voltage VCC = 15V, IOH = –100mA NA555, NE555, SA555 12.75 13.3 V SE555 13 13.3 VCC = 15V, IOH = –100mA, TA = –55°C to +125°C SE555 12 VCC = 15V, IOH = –200mA 12.5 VCC = 5V, IOH = –100mA NA555, NE555, SA555 2.75 3.3 SE555 3 3.3 VCC = 5V, IOH = –100mA, TA = –55°C to +125°C SE555 2 Supply current Output low, no load, VCC = 15V NA555, NE555, SA555 10 15 mA SE555 10 12 Output low, no load, VCC = 5V NA555, NE555, SA555 3 6 SE555 3 5 Output high, no load, VCC = 15V NA555, NE555, SA555 9 13 SE555 9 10 Output high, no load, VCC = 5V NA555, NE555, SA555 2 5 SE555 2 4 (1) This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 6-5. For example, when VCC = 5V, the maximum value is R = RA + RB ≅ 3.4MΩ, and for VCC = 15V, the maximum value is RA + RB ≅ 10MΩ. NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 www.ti.com

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5.6 Switching Characteristics

VCC = 5V to 15V and TA = 25°C (unless otherwise noted); characteristic values are specified by design, characterization, or both, and are not production tested PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT Temperature coefficient of timing interval Each timer, monostable(2), TA = MIN to MAX NA555, NE555, SA555 50 ppm/°C SE555 30 100 Each timer, astable(3), TA = MIN to MAX NA555, NE555, SA555 150 SE555 90 Supply-voltage sensitivity of timing interval Each timer, monostable(2) NA555, NE555, SA555 0.1 0.5 %/V SE555 0.05 0.2 Each timer, astable(3) NA555, NE555, SA555 0.3 SE555 0.15 tr Output-pulse rise time CL = 15pF, TA = 25°C, 20% to 80% NA555, NE555, SA555 100 300 ns SE555 100 200 tf Output-pulse fall time CL = 15pF, TA = 25°C, 80% to 20% NA555, NE555, SA555 100 300 ns SE555 100 200 (1) For conditions shown as MIN or MAX, use the appropriate value specified under Recommended Operating Conditions. (2) Values specified are for a device in a monostable circuit similar to Figure 6-2, with the following component values: RA = 2kΩ to 100kΩ, C = 0.1μF. (3) Values specified are for a device in an astable circuit similar to Figure 6-5, with the following component values: RA = 1kΩ to 100kΩ, C = 0.1μF. www.ti.com NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: NA555 NE555 SA555 SE555

5.7 Typical Characteristics

Data for temperatures less than –40°C and greater than 105°C are applicable for SE555 circuits only. I O L - L o w - L e v e l O u t p u t C u r r e n t ( m A ) VOL- Low-Level Output Voltage (V) 1 2 3 4 5 6 7 8 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 0 . 0 0 1 0 . 0 0 2 0 . 0 0 5 0 . 0 1 0 . 0 2 0 . 0 5 0 . 1 0 . 2 0 . 5 1 0 V C C = 5 V- 5 5 ° C 2 5 ° C 1 2 5 ° C Figure 5-1. Low-Level Output Voltage vs Low-Level Output Current I O L - L o w - L e v e l O u t p u t C u r r e n t ( m A ) VOL- Low-Level Output Voltage (V) 1 2 3 4 5 6 7 8 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 0 . 0 0 1 0 . 0 0 2 0 . 0 0 5 0 . 0 1 0 . 0 2 0 . 0 5 0 . 1 0 . 2 0 . 5 1 0 V C C = 1 0 V- 5 5 ° C 2 5 ° C 1 2 5 ° C Figure 5-2. Low-Level Output Voltage vs Low-Level Output Current I O L - L o w - L e v e l O u t p u t C u r r e n t ( m A ) VOL- Low-Level Output Voltage (V) 1 2 3 4 5 6 7 8 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 0 . 0 0 1 0 . 0 0 2 0 . 0 0 5 0 . 0 1 0 . 0 2 0 . 0 5 0 . 1 0 . 2 0 . 5 1 0 V C C = 1 5 V- 5 5 ° C 2 5 ° C 1 2 5 ° C Figure 5-3. Low-Level Output Voltage vs Low-Level Output Current I O H - H i g h - L e v e l O u t p u t C u r r e n t ( m A ) (VCC- VOH) - Voltage Drop (V) 1 2 3 4 5 6 7 8 1 0 2 0 3 0 4 0 5 0 7 0 1 0 0 0 . 5 0 . 7 0 . 9 1 . 1 1 . 3 1 . 5 1 . 7 1 . 9 2 . 1 2 . 3 2 . 5 V C C = 5 V t o 1 5 V- 5 5 ° C 2 5 ° C 1 2 5 ° C Figure 5-4. Drop Between Supply Voltage and Output vs High-Level Output Current V C C - S u p p l y V o l t a g e ( V ) ICC- Supply Current (mA) 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 0 O u t p u t L o w , N o L o a d - 5 5 ° C 2 5 ° C 1 2 5 ° C Figure 5-5. Supply Current vs Supply Voltage V C C - S u p p l y V o l t a g e ( V ) Pulse Duration Relative to Value at VCC= 10V 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 0 . 9 2 0 . 9 4 0 . 9 6 0 . 9 8 1 . 0 2 1 . 0 4 1 . 0 6 1 . 0 8 1 . 1 1 . 1 2 Figure 5-6. Normalized Output Pulse Duration (Monostable Operation) vs Supply Voltage NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 www.ti.com

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5.7 Typical Characteristics (continued)

Data for temperatures less than –40°C and greater than 105°C are applicable for SE555 circuits only. T A - F r e e - A i r T e m p e r a t u r e ( ° C ) Pulse Duration Relative to Value at TA= 25°C - 7 5 - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 0 . 9 8 4 0 . 9 8 7 0 . 9 9 0 . 9 9 3 0 . 9 9 6 0 . 9 9 9 1 . 0 0 2 1 . 0 0 5 1 . 0 0 8 1 . 0 1 1 1 . 0 1 4 1 . 0 1 7 V C C = 1 0 V Figure 5-7. Normalized Output Pulse Duration (Monostable Operation) vs Free-Air Temperature L o w e s t L e v e l o f T r i g g e r P u l s e ( × V C C ) tPD- Propagation Delay Time (ns) 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 - 5 5 ° C 0 ° C 2 5 ° C 7 0 ° C 1 2 5 ° C Figure 5-8. Propagation Delay Time vs Lowest Voltage Level of Trigger Pulse www.ti.com NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: NA555 NE555 SA555 SE555

6 Detailed Description

6.1 Overview

The Nx555 or Sx555 is a precision timing device for general-purpose timing applications from 10µs to hours or from < 1mHz to 100kHz. In the time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. Maximum output sink and discharge sink current are greater for higher VCC and less for lower VCC. S R TRIG THRES VCC CONT RESET OUT DISCH GND Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Note: Pin numbers shown are for the D, JG, P, PS, and PW packages. Note: RESET can override TRIG, which can override THRES. Figure 6-1. Simplified Schematic

6.2 Functional Block Diagram

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6.3 Feature Description

6.3.1 Monostable Operation

For monostable operation, Figure 6-2 shows how to connect any of these timers. If the output is low, application of a negative-going pulse to the trigger (TRIG) sets the flip-flop ( Q goes low), drives the output high, and turns off Q1. Capacitor C is then charged through R A until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold comparator resets the flip-flop ( Q goes high), drives the output low, and discharges C through Q1. RA Output GND OUT CONT RESET DISCH THRES TRIGInput VCC VCC C Figure 6-2. Circuit for Monostable Operation Monostable operation is initiated when the TRIG voltage is less than the trigger threshold. After being initiated, the sequence ends only if TRIG is high for at least 10µs before the end of the timing interval. When the trigger is grounded, the comparator storage time can be as long as 10µs, which limits the minimum monostable pulse width to 10µs. As a result of the threshold level and saturation voltage of Q1, the output pulse duration is approximately t w = 1.1 × R AC. Figure 6-4 is a plot of the time constant for various values of R A and C. The threshold levels and charge rates both are directly proportional to the supply voltage, V CC. The timing interval is, therefore, independent of the supply voltage, as long as the supply voltage is constant during the time interval. Voltage − 2 V/div Time − 0.1 ms/div ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ Capacitor Voltage Output Voltage Input Voltage ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ RA = 9.1 kΩ CL = 0.01 µ F RL = 1 kΩ See Figure 9 Figure 6-3. Typical Monostable Waveforms − Output Pulse Duration − s C − Capacitance − µ F 10−1 10−2 10−3 10−4 1001010.10.01 10−5 0.001 tw RA = 10 MΩ RA = 10 kΩ RA = 1 kΩ RA = 100 kΩ RA = 1 MΩ Figure 6-4. Output Pulse Duration vs Capacitance Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low for as long as the reset pulse is low. To prevent false triggering, when RESET is not used, connect RESET to VCC. www.ti.com NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: NA555 NE555 SA555 SE555

6.3.2 Astable Operation

Figure 6-5 shows that adding a second resistor, R B, to the circuit of Figure 6-2 and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multivibrator. Capacitor C charges through R A and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and RB. GND OUT VCCCONT RESET DISCH THRES TRIG C RB RA Output RL 0.01 µ F VCC (5 V to 15 V) (see Note A) Î Î Î NOTE A: Decoupling CONT voltage to ground with a capacitor can improve operation. This should be evaluated for individual applications. Open 5 8 Pin numbers shown are for the D, JG, P, PS, and PW packages. Figure 6-5. Circuit for Astable Operation Voltage − 1 V/div Time − 0.5 ms/div tH Capacitor Voltage Output VoltagetL ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ RA = 5 k/C0087 RL = 1 k/C0087 RB = 3 k/C0087 See Figure 12 C = 0.15 µ F Figure 6-6. Typical Astable Waveforms This astable connection results in capacitor C charging and discharging between the threshold-voltage level (≅ 0.67 × V CC) and the trigger-voltage level ( ≅ 0.33 × V CC). As in the mono-stable circuit, charge and discharge times (and, therefore, the frequency and duty cycle) are independent of the supply voltage. To reduce distortion, use at maximum frequency of 100kHz or below. If higher-frequency operation is required, consider using the TLC555 CMOS Timer instead. Figure 6-6 shows typical waveforms generated during astable operation. The output high-level duration t H and low-level duration tLare calculated as follows: t H ≅ 0.693 × R A + R B × C (1) t L ≅ 0.693 × R B × C (2) Other useful relationships for period, frequency, and driver-referred and waveform-referred duty cycle are calculated as follows: T = t H + t L ≅ 0.693 × R A + 2R B × C (3) f = 1 T ≅ 1.44 R A + 2R B × C (4) Ou t pu t d riv e r dut y cy cle = t L T ≅ R B R A + 2 R B (5) Ou t pu t wav ef or m dut y cy cle = t H T ≅ 1 − R B R A + 2R B = R A + R B R A + 2R B (6) NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 www.ti.com

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f − Free-Running Frequency − Hz C − Capacitance − µ F 100 k 10 k 1 k 100 1001010.10.01 0.1 0.001 RA + 2 RB = 10 MΩ RA + 2 RB = 1 MΩ RA + 2 RB = 100 kΩ RA + 2 RB = 10 kΩ RA + 2 RB = 1 kΩ Figure 6-7. Free-Running Frequency

6.3.3 Frequency Divider

By adjusting the length of the timing cycle, the basic circuit of Figure 6-2 can be made to operate as a frequency divider. Figure 6-8 shows a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle. Voltage − 2 V/div Time − 0.1 ms/div Capacitor Voltage Output Voltage Input Voltage VCC = 5V RA = 1250Ω C = 0.2µF See Figure 6-2 Figure 6-8. Divide-by-Three Circuit Waveforms

6.4 Device Functional Modes

Table 6-1 shows the device truth table. For a valid reset voltage condition, use an external pullup resistor to V CC (if using the RESET functionality), or short the RESET pin directly to VCC (if the RESET functionality is not used). Table 6-1. Function Table RESET VOLTAGE(1) TRIGGER VOLTAGE(1) THRESHOLD VOLTAGE(1) OUTPUT DISCHARGE SWITCH LOW Irrelevant Irrelevant Low On > MAX < 1/3 × VCC Irrelevant(2) High Off > MAX > 1/3 × VCC > 2/3 × VCC Low On > MAX > 1/3 × VCC < 2/3 × VCC As previously established (1) Voltage levels shown are nominal. (2) CONT pin open or 2/3 × VCC. www.ti.com NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: NA555 NE555 SA555 SE555

7 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Application Information

The Nx555 and Sx555 precision timers use resistor and capacitor charging delay to provide a programmable time delay or operating frequency. This section presents a simplified discussion of the design process.

7.2 Typical Applications

7.2.1 Missing-Pulse Detector

The circuit shown in Figure 7-1 can be used to detect a missing pulse or abnormally long spacing between consecutive pulses in a train of pulses. The timing interval of the monostable circuit is re-triggered continuously by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing, missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse as shown in Figure 7-2. VCC (5 V to 15 V) DISCH OUT VCCRESET RL RA A5T3644 C THRES GND CONT TRIG Input 0.01 µ F ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Output 4 8 Pin numbers shown are shown for the D, JG, P, PS, and PW packages. Figure 7-1. Circuit for Missing-Pulse Detector

7.2.1.1 Design Requirements

Input fault (missing pulses) must be input high. Input stuck low cannot be detected because the timing capacitor (C) remains discharged.

7.2.1.2 Detailed Design Procedure

Choose RA and C so that R A× C > [maximum normal input high time]. R L improves VOH, but is not required for TTL compatibility. NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 www.ti.com

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7.2.1.3 Application Curve

Time − 0.1 ms/div Voltage − 2 V/div ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ VCC = 5 V RA = 1 kΩ C = 0.1 µ F See Figure 15 Capacitor Voltage ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Output Voltage Input Voltage Figure 7-2. Completed Timing Waveforms for Missing-Pulse Detector

7.2.2 Pulse-Width Modulation

The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is accomplished by applying an external voltage (or current) to CONT. Figure 7-3 shows a circuit for pulse-width modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the threshold voltage. Figure 7-4 shows the resulting output pulse-width modulation. While a sine-wave modulation signal is shown, any wave shape can be used. THRES GND C RARL VCC (5 V to 15 V) Output DISCH OUT VCCRESET TRIG CONT Modulation Input (see Note A) Clock Input NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the effects of modulation source voltage and impedance on the bias of the timer should be considered. 4 8 Pin numbers shown are for the D, JG, P, PS, and PW packages. Figure 7-3. Circuit for Pulse-Width Modulation

7.2.2.1 Design Requirements

Clock input must have V OL and V OH levels that are less than and greater than 1/3 × V CC. Modulation input can vary from ground to V CC. The application must be tolerant of a nonlinear transfer function; the relationship between modulation input and pulse width is not linear because the capacitor charge is RC-based with an negative exponential curve. www.ti.com NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: NA555 NE555 SA555 SE555

7.2.2.2 Detailed Design Procedure

Choose R A and C so that R A × C = 1/4 [clock input period]. R L improves V OH, but is not required for TTL compatibility.

7.2.2.3 Application Curve

Voltage − 2 V/div Time − 0.5 ms/div ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ Capacitor Voltage ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ Output Voltage ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ Clock Input Voltage ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ RA = 3 kΩ C = 0.02 µ F RL = 1 kΩ See Figure 18 ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ Modulation Input Voltage Figure 7-4. Pulse-Width-Modulation Waveforms

7.2.3 Pulse-Position Modulation

As shown in Figure 7-5 , any of these timers can be used as a pulse-position modulator. This application modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure 7-6 shows a triangular-wave modulation signal for such a circuit; however, any wave shape can be used. RB Modulation Input (see Note A) CONT TRIG RESET V CC OUT DISCH VCC (5 V to 15 V) RL RA C GND THRES NOTE A: The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, the ef fects of modulation source voltage and impedance on the bias of the timer should be considered. Pin numbers shown are for the D, JG, P, PS, and PW packages. 4 8 Output Figure 7-5. Circuit for Pulse-Position Modulation

7.2.3.1 Design Requirements

Both dc- and ac-coupled modulation input changes the upper and lower voltage thresholds for the timing capacitor. Both frequency and duty cycle vary with the modulation voltage. NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 www.ti.com

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Product Folder Links: NA555 NE555 SA555 SE555

7.2.3.2 Detailed Design Procedure

The nominal output frequency and duty cycle are determined using the formulas in Section 6.3.2. RL improves VOH, but RL is not required for TTL compatibility.

7.2.3.3 Application Curve

Voltage − 2 V/div ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ RA = 3 kΩ RB = 500 Ω RL = 1 kΩ See Figure 20 ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Capacitor Voltage ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Output Voltage ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ Modulation Input Voltage Time − 0.1 ms/div Figure 7-6. Pulse-Position-Modulation Waveforms

7.2.4 Sequential Timer

Many applications, such as computers, require signals for initializing conditions during start-up. Other applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be connected to provide such sequential control. The timers can be used in various combinations of astable or monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 7-7 shows a sequencer circuit with possible applications in many systems, and Figure 7-8 shows the output waveforms. S VCC RESET V CC OUT DISCH GND CONT TRIG 4 8 THRES RC CC 0.01 CC = 14.7 µ F RC = 100 kΩ Output C RESET V CC OUT DISCH GND CONT TRIG 4 8 THRES RB 33 kΩ 0.001 0.01 µ F CB = 4.7 µ F RB = 100 kΩ Output BOutput ARA = 100 kΩ CA = 10 µ F µ F 0.01 µ F 0.001 33 kΩRA THRES TRIG CONT GND DISCH OUT VCCRESET µ F µ F CBCA Pin numbers shown are for the D, JG, P, PS, and PW packages. NOTE A: S closes momentarily at t = 0. Figure 7-7. Sequential Timer Circuit

7.2.4.1 Design Requirements

The sequential timer application chains together multiple mono-stable timers. The joining components are the 33kΩ resistors and 0.001µF capacitors. The output high to low edge passes a 10µs start pulse to the next monostable. www.ti.com NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: NA555 NE555 SA555 SE555

7.2.4.2 Detailed Design Procedure

The timing resistors and capacitors can be chosen using this formula. tw = 1.1 × R × C.

7.2.4.3 Application Curve

Voltage − 5 V/div t − T ime − 1 s/div ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ See Figure 22 ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ Output A ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ Output B ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ Output C ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ t = 0 ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ twC = 1.1 RCCC ÏÏ ÏÏ ÏÏ twC ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ twB = 1.1 RBCB ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ twA = 1.1 RACA ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ twA ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ twB Figure 7-8. Sequential Timer Waveforms

7.3 Power Supply Recommendations

The Nx555 and Sx555 precision timers are designed to operate from an input voltage supply range between 4.5V and 16V (18V for SE555). A bypass capacitor is highly recommended from V CC to the ground pin; a ceramic 0.1µF capacitor is sufficient. NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 www.ti.com

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8 Device and Documentation Support

8.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

8.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision J (February 2025) to Revision K (March 2026) Page Changes from Revision I (September 2014) to Revision J (February 2025) Page

• Deleted package thermal impedance specifications from Absolute Maximum Ratings and added Thermal
• Changed Operating Characteristics title to Switching Characteristics, and clarified that values are specified by
• Deleted initial error of timing interval specification in Switching Characteristics and clarified that output rise www.ti.com NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: NA555 NE555 SA555 SE555

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-side navigation. NA555, NE555, SA555, SE555 SLFS022K – SEPTEMBER 1973 – REVISED MARCH 2026 www.ti.com

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www.ti.com 15-Jul-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) JM38510/10901BPA Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510 /10901BPA JM38510/10901BPA.A Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510 /10901BPA NA555D Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 105 NA555 NA555DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555P Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU | SN N/A for Pkg Type -40 to 105 NA555P NA555P.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 105 NA555P NA555PE4 Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 105 NA555P NA555PE4.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 105 NA555P NE555D Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 NE555 NE555DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM 0 to 70 NE555 NE555DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DR1G4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DR1G4.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DRG4 Obsolete Production SOIC (D) | 8 - - Call TI Call TI 0 to 70 NE555 NE555P Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU | SN N/A for Pkg Type 0 to 70 NE555P NE555P.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 NE555P NE555PE4 Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 NE555P NE555PE4.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type 0 to 70 NE555P NE555PS Active Production SO (PS) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM - N555 NE555PS.A Active Production SO (PS) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PSR Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PSR.A Active Production SO (PS) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PW Obsolete Production TSSOP (PW) | 8 - - Call TI Call TI 0 to 70 N555 NE555PWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWR.A Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM 0 to 70 N555 SA555D Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 SA555 SA555DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 SA555 Addendum-Page 1

www.ti.com 15-Jul-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) SA555DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555DRG4 Obsolete Production SOIC (D) | 8 - - Call TI Call TI -40 to 85 SA555 SA555P Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SA555P SA555P.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SA555P SE555DG4 Obsolete Production SOIC (D) | 8 - - Call TI Call TI -55 to 125 SE555 SE555DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555DRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555DRG4.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555FKB Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 SE555FKB SE555FKB.A Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 SE555FKB SE555JG Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 SE555JG SE555JG.A Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 SE555JG SE555JGB Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 SE555JGB SE555JGB.A Active Production CDIP (JG) | 8 50 | TUBE No SNPB N/A for Pkg Type -55 to 125 SE555JGB SE555P Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 SE555P SE555P.A Active Production PDIP (P) | 8 50 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 SE555P (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. Addendum-Page 2

www.ti.com 15-Jul-2026 (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SE555, SE555M :

• Catalog : SE555
• Military : SE555M
• Space : SE555-SP , SE555-SP NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 20-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) NA555DR SOIC D 8 2500 353.0 353.0 32.0 NE555DR SOIC D 8 2500 353.0 353.0 32.0 NE555DR1G4 SOIC D 8 2500 353.0 353.0 32.0 NE555PSR SO PS 8 2000 353.0 353.0 32.0 NE555PWR TSSOP PW 8 2000 353.0 353.0 32.0 SA555DR SOIC D 8 2500 353.0 353.0 32.0 SE555DR SOIC D 8 2500 350.0 350.0 43.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) NA555P P PDIP 8 50 506.1 9 600 5.4 NA555P P PDIP 8 50 506 13.97 11230 4.32 NA555P.A P PDIP 8 50 506 13.97 11230 4.32 NA555P.A P PDIP 8 50 506.1 9 600 5.4 NA555PE4 P PDIP 8 50 506 13.97 11230 4.32 NA555PE4.A P PDIP 8 50 506 13.97 11230 4.32 NE555P P PDIP 8 50 506 13.97 11230 4.32 NE555P P PDIP 8 50 506.1 9 600 5.4 NE555P.A P PDIP 8 50 506 13.97 11230 4.32 NE555P.A P PDIP 8 50 506.1 9 600 5.4 NE555PE4 P PDIP 8 50 506 13.97 11230 4.32 NE555PE4.A P PDIP 8 50 506 13.97 11230 4.32 NE555PS PS SOP 8 80 530 10.5 4000 4.1 NE555PS.A PS SOP 8 80 530 10.5 4000 4.1 SA555P P PDIP 8 50 506 13.97 11230 4.32 SA555P.A P PDIP 8 50 506 13.97 11230 4.32 SE555FKB FK LCCC 20 55 506.98 12.06 2030 NA SE555FKB.A FK LCCC 20 55 506.98 12.06 2030 NA SE555P P PDIP 8 50 506 13.97 11230 4.32 SE555P.A P PDIP 8 50 506 13.97 11230 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE 10.16 9.00 7.11 6.22 1.60 0.38 6X 2.54 8X 0.58 0.38 4X 1.65 1.14 0.51 MIN 3.30 MIN

5.08 MAX

7.87 7.37 0.36

0.20 TYP

4X (0.94) CDIP - 5.08 mm max heightJG0008A CERAMIC DUAL IN-LINE PACKAGE 4230036/A 09/2023 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package can be hermetically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification. 5. Falls within MIL STD 1835 GDIP1-T8 SEATING PLANE

0.25 C A B

A B C

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

(7.62) 6X (2.54) 8X ( 1) THRU 7X ( 1.6) (1.6) (R0.05) TYP CDIP - 5.08 mm max heightJG0008A CERAMIC DUAL IN-LINE PACKAGE 4230036/A 09/2023 LAND PATTERN EXAMPLE NON SOLDER MASK DEFINED SCALE: 9X SOLDER MASK OPENING TYP METAL TYP SYMM SYMM 4 5

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. LCCC - 2.03 mm max heightFK 20 LEADLESS CERAMIC CHIP CARRIER8.89 x 8.89, 1.27 mm pitch 4229370\\/A\\

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2

1.2 MAX

6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8)

0.05 MIN

8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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