SCD55100A

SCD55100A OSRAM

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 17

Technical content

Lead (Pb) Free Product - RoHS Compliant Standard Red SCD55100A Yellow SCD55101A High Efficiency Red SCD55102A Green SCD55103A High Efficiency Green SCD55104A Slimline 0.145’’ 10-Character 5x5 Dot Matrix Serial Input Dot Addressable Intelligent Display® Devices 2006-02-20 1

DESCRIPTION

The SCD55100A (Red), SCD55101A (Y ellow), SCD55102A (HER), SCD55103A (Green) and SCD55104A (HEG) are eight digit dot addressable 5 x 5 matrix, Serial Input, Intelligent Display devices. The ten 3.68 mm (0.145") high digits are packaged in a rugged, high quality optically transparent, standard 7.62 mm (0.3") pin spacing 28 pin plastic DIP . The on-board CMOS has a 250 bit RAM, one bit associ- ated with one LED, each to generate User Defined Char- acters. Due to the reduced LED count, power requirement and heat dissipation are reduced by 30%. Additionally in Power Down Mode quiescent current is <50 µA. The SCD5510XA is designed to work with the Serial port of most common microprocessors. The multiplex Clock I/O (CLK I/O) and multiplex Clock Select ( CLKSEL) pins offer the user the capability to supply a high speed external multiplex clock. This feature can minimize audio in-band interference for portable communication equipment or eliminate the visual synchronization effects found in high vibration environments such as avionics equipment.

FEATURES

• Low Profile Package: 60% Smaller than Industry Stan - dard 10-Digit Display  Ten 3.68 mm (0.145") 5 x 5 Dot Matrix Characters in Red, Y ellow, High Efficiency Red, Green, or High Efficiency Green  Optimum Display Surface Efficiency (display area to package ratio)  Low Power–30% Less Power Dissipation than 5 x 7 Format  High Speed Data Input Rate: 5.0 MHz  ROMless Serial Input, Dot Addressable Display—Ideal for User Defined Characters  Built-in Decoders, Multiplexers and LED Drivers  Readable from 1.8 meters (6 Feet)  Wide Viewing Angle, X Axis ± 55°, Y Axis ± 65°  Attributes: – 250 bit RAM for User Defined Characters – Eight Dimming Levels – Power Down Mode (<250 µW) – Hardware/Software Clear Function – Lamp Test  Internal or External Clock  End-Stackable Dual-in-line Plastic Package – 3.3 V Capability

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A Package Outlines Dimensions in mm (inch)

Ordering Information

Type Color of Emission Character Height mm (inch) Ordering Code SCD55104A standard red 3.68 (0.145) Q68100A0988 SCD55101A yellow Q68100A0989 SCD55102A high efficiency red Q68100A0990 SCD55103A green Q68100A0991 SCD55104A high efficiency green Q68100A0992 IDOD5211 38.1 (1.500) max. 3.68 (0.145) Pin 5.08 (0.200) 0.3 (0.012) typ. 1.27 (0.050) typ. Indicator 33.02 (1.300) ref. Seating Plane 2.54 (0.100) typ. ±0.25 (0.010) Tol. non accum. 1 SCD5510XA OSRAM YYWW ZY EIA Date Code Intensity Code Hue Code Dimension is at Seating Plane. 2. Display matrix and pins centered on package outline. 3. Display matrix centered to pin array. 4. Tolerance: ±.XXX (0.010) Color Code Part No 5. Lead dim .018 wide x .012 THK 0.25 (0.010)

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A 2006-02-20 3 Maximum Ratings Parameter Symbol Value Unit Operating temperature range Top – 40 … + 85 °C Storage temperature range Tstg – 40 … + 100 °C DC Supply Voltage VCC -0.5 to + 7.0 V Input Voltage Levels Relative to GND -0.5 to VCC to 0.5 V Solder Temperature 1.59 mm (0.063“) below seating plane, t < 5.0 s TS 260 °C Relative Humidity 85 % ESD (100 pF, 1.5 kΩ) VZ 2.0 kV Input Current ± 100 mA Power Dissipation at 85°C 1.7 W Maximum Number of LEDs on at 100% Brightness 160 IC Junction Temperature 125 °C Optical Characteristics at 25°C (VCC=5.0 V at 100% brightness level, viewing angle: X axis ± 55°, Y axis ± 65°) Description Symbol Values Unit Red SCD55100A Yellow SCD55101A High Efficiency Red SCD55102A Green SCD55103A High Efficiency Green SCD55104A Luminous Intensity (min.) (typ.) IV 36 124 208 124 237 124 238 124 500 µcd/dot µcd/dot Peak Wavelength (typ.) λpeak 665 583 630 565 568 nm Dominant Wavelength (typ.) λdom 639 584 626 569 572 nm Notes: 1. Dot to dot intensity matching at 100% brightness is 1.8:1. 2. Displays are binned for hue at 2.0 nm intervals. 3. Displays within a given intensity category have an intensity matching of 1.5:1 (max.).

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A Data Write Cycle Instruction Cycle Maximum Power Dissipation vs. Temperature LOAD DATA SDCLK TSDCW TSDCLK Period TLDS TDS TDH TLDH 3.5 V 1.5 V 3.5 V 1.5 V 3.5 V 1.5 V TSDCW TWR OR LOAD SDCLK DATA LOAD SDCLK DATA TBL D0D7D6D5D4D3D2D1D0 D0D7D6D5D4D3D2D1D0 IDDG5332 -400 P W TA 1.0 2.0 3.0 4.0 θJA = 31 ˚C/W D 0.5 1.5 2.5 3.5 -20 0 20 40 60 100

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A 2006-02-20 5 Input/Output Circuits Figures „Inputs“ and „Clock I/O“ show the input and output resis- tor/diode networks used for ESD protection and to eliminate sub- strate latch-up caused by input voltage over/under shoot. Inputs Top View Clock I/O Electrical Characteristics (over operating temperature) Parameter Min. Typ. Max. Units Conditions VCC 4.5 5.0 5.5 V — ICC (Pwr Dwn Mode) (4) — 50 — µA VCC=5.0 V, all inputs=0 V or VCC ICC 10 digits 16 dots/character — 250 365 mA VCC=5.0 V, “#” displayed in all 10 digits at 100% brightness at 25°C IIL Input current — — –10 µA VCC=5.0 V, VIN=0 V (all inputs) IIH Input current — — 10 µA VCC=VIN=5.0 V (all inputs) VIH 3.5 — — V VCC=4.5 V to 5.5 V VIL — — 1.5 V VCC=4.5 V to 5.5 V IOH (CLK I/O) — –8.9 — mA VCC=4.5 V, VOH=2.4 V IOL (CLK I/O) — 1.6 — mA VCC=4.5 V, VOL=0.4 V θJA — — 31 °C/W — Fext External Clock Input Frequency 120 — 347 kHz VCC=5.0 V, CLKSEL=0 Fosc Internal Clock Input Frequency 120 — 347 kHz VCC=5.0 V, CLKSEL=1 Clock I/O Bus Loading — — 240 pF — Clock Out Rise Time — — 500 ns VCC=4.5 V, VOH=2.4 V Clock Out Fall Time — — 500 ns VCC=4.5 V, VOH=0.4 V FM, Digit 375 768 1086 Hz — Notes: 1) Peak current 5/3 x ICC. 2) Unused inputs must be tied high. 3) Contact Infineon for 3.3 V operation. 4) External oscillator must be stopped if being used to maintain an ICC <50 µA. IDCD5021 GND 1 kΩInput CCV 11 4 28 15 IDPA5117 IDCD5026 GND 1 kΩInput/Output CCV

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A 2006-02-20 6 Dot Matrix Format mm (inch) Pin Assignment Pin Function Pin Function

1 SDCLK 28 GND

2 LOAD 27 DATA

3 NC 26 NC

4 NC 25 NC

5 NC 24 NC

6 VCC 23 VCC

7 NP 22 NP

8 NP 21 NP

9 VCC 20 VCC

10 NC 19 VCC

11 NC 18 NC

12 NC 17 NC

13 RST 16 CLKSEL

14 GND 15 CLK I/O

(over operating temperature range and VCC=4.5 V to 5.5 V) Symbol Description Min. Units TRC Reset Active Time 600 ns TLDS Load Setup Time 50 ns TDS Data Setup Time 50 ns TSDCLK Clock Period 200 ns TSDCW Clock Width 70 ns TLDH Load Hold Time 0 ns TDH Data Hold Time 25 ns TWR Total Write Time 2.2 µs TBL Time Between Loads 600 ns Note: TSDCW is the minimum time the SDCLK may be low or high. The SDCLK period must be a minimum of 200 ns. IDOD5212 C0 C1 C2 C3 C4 3.68 (0.145) 2.03 (0.080) Tolerance: ±0.25 (0.010) Pin Definitions Pin Function Definitions

1 SDCLK Loads data into the 8-bit serial data register

on a low to high transition.

2 LOAD Low input enables data clocking into 8-bit

serial shift register. When LOAD goes high, the contents of 8-bit serial Shift Register will be decoded.

3 NC No connection

4 NC No connection

5 NC No connection

6 VCC Power supply/heat sink

7 NP No pin

8 NP No pin

9 VCC Power supply/heat sink

10 NC No connection

11 NC No connection

12 NC No connection

13 RST Asynchronous input, when low will clear the

Multiplex Counter, User RAM and Data Register. Control Word Register is set to 100% brightness and the Address Register is set to select Digit 0. The display is blanked.

14 GND Power supply ground

15 CLK I/O Outputs master clock or inputs external clock.

16 CLKSEL H=internal clock, L=external clock

17 NC No connection

18 NC No connection

19 VCC Power supply/heat sink

20 VCC Power supply/heat sink

21 NP No pin

22 NP No pin

23 VCC Power supply/heat sink

24 NC No connection

25 NC No connection

26 NC No connection

27 DATA Serial data input

28 GND Power supply ground

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A 2006-02-20 7 Operation of the SCD5510XA The SCD5510XA display consists of a CMOS IC containing control logic and drivers for eight 5 x 5 characters. These components are assembled in a compact (38 mm x 10 mm) plastic package. Individual LED dot addressablity allows the user great freedom in creating special characters or mini-icons. The User Definable Character Set Examples illustrate 200 different character and sym- bol possibilities. The use of a serial data interface provides a highly efficient inter- connection between the display and the mother board. The SCD5510XA requires only 4 lines as compared to 15 for an equiv alent 8 character parallel input part. The on-board CMOS IC is the electronic heart of the display. The IC accepts decoded serial data, which is stored in the internal RAM. Asynchronously the RAM is read by the character multiplexer at a strobe rate that results in a flicker free display. Figure „Row and Column Location“ ( page 9) shows the three functional areas of the IC. These include: the input serial data register and control logic, a 250 bits two port RAM, and an internal multiplexer/display driver. SCD5510XA Block Diagram Display Column and Row Format C0 C1 C2 C3 C4 Row 0 1 1 1 1 1 Row 1 0 0 1 0 0 Row 2 0 0 1 0 0 Row 3 0 0 1 0 0 Row 4 0 0 1 0 0 Column Data Ranges Row 0 00H to 1FH Row 1 20H to 3FH Row 2 40H to 5FH Row 3 60H to 7FH Row 4 80H to 9FH LOAD Row Address Decode Write Character/ Write 50 x 5 Read 10 x 25 Column Output RAM 250 bits Display Multiplexer 5Adddress Character Register Adddress Register Word Control Software Clear OPCODE Decode D7 D6 D5 OPCODE DATA D4 D3 D2 D1 D0 Power Down Brightness & Lamp Test Data Clock Serial Data Oscillator Counter Chain & Timing Logic Column Logic & Driver 10 2345 89 10 - 5 x 5 Characters & Driver Row Decoder 10 MUX CLK I/O MUX Clock SEL RESET IDBD5069 Serial

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A 2006-02-20 8 The following explains how to format the serial data to be loaded into the display. The user supplies a string of bit mapped decoded characters. The contents of this string is shown in Figure „Loading Serial Character Data a“ (page 8). Figure „Loading Serial Charac- ter Data b“ (page 8) shows that each character consist of six 8 bit words. The first word encodes the display character location and the succeeding five bytes are row data. The row data represents the status (On, Off) of individual column LEDs. Figure „Loading Serial Character Data c“ (page 8) shows that each 8 bit word is formatted to include a three bit Operational Code (OPCODE) defined by bits D7–D5 and five bits (D4–D0) representing Column Data, Character Address, or Control Word Data. Figure „Loading Serial Character Data d“ (page 8) shows the sequence for loading the bytes of data. Bringing the LOAD line low enables the serial register to accept data. The shift action occurs on the low to high transition of the serial data clock (SDCLK). The least significant bit (D0) is loaded first. After eight clock pulses the LOAD line is brought high. With this transition the OPCODE is decoded. The decoded OPCODE directs D4–D0 to be latched in the Character Address register, stored in the RAM as Column data, or latched in the Control Word register. The control IC requires a minimum 600 ns delay between successive byte loads. As indicated in Figure „Loading Serial Character Data a“ (page 8), a total of 660 clock cycles (60-8 bit words) are required to load all ten characters into the display. The Character Address Register bits, D4–D0 (Table „Load Charac- ter Address“ (page 9)) and Row Address Register bits, D7–D5 (Table „Load Column Data“ (page 9)) direct the Column Data bits, D4–D0 (Table „Load Column Data“ (page 9)) to specific RAM loca- tion. Table „Character ’D’“ (page 8) shows the Row Address for the example character “D.” Column data is written and read asynchro- nously from the 250 bit RAM. Once loaded the internal oscillator and character multiplexer reads the data from the RAM. These characters are row strobed with column data as shown in Figures „Row and Column Location“ ( page 9) and „Row Strobing“ (page 10). The character strobe rate is determined by the internal or user supplied external MUX Clock and the IC’s ÷ 320 counter. Loading Serial Character Data Character “D” Op code D7 D6 D5 Column Data D4 D3 D2 D1 D0 C0 C1 C2 C3 C4 Hex Row 0 00 0 11 1 1 0 1E Row 1 00 1 10 0 0 1 31 Row 2 01 0 10 0 0 1 51 Row 3 01 1 10 0 0 1 71 Row 4 10 0 11 1 1 0 9E Character 0 Character 1 Character 2 Character 3 Character 4 Character 5 Character 6 Character 7 Character 8 Character 9

660 Clock Cycles, 132 µs

Example: Serial Clock = 5 MHz, Clock Period = 200 ns Time between LOADS LOAD Serial Clock DATA Clock Period t 0 D0 D1 D2 D3 D4 D5 D6 D7 11 Clock Cycles, 2.2 s Time Between Loads OPCODECharacter Address OPCODEColumn Data Character 0 Address Row 0 Column Data 66 Clock Cycles, 13.2 µs Row 1 Column Data Row 2 Column Data Row 3 Column Data Row 4 Column Data

0 D5 D6 D7

11 Clock Cycles, 2.2 s 600 ns(min.) Time Between Loads 600 ns(min.)

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A 2006-02-20 9 The user can activate four Control functions. These include: LED Brightness Level, Lamp Test, IC Power Down, or Display Clear. OPCODEs and five bit words are used to initiate these functions. The OPCODEs and Control Words for the Character Address and Loading Column Data are shown in Tables „Load Character Address“ ( page 9) and „Load Column Data“ (page 9). The user can select seven specific LED brightness levels, Table „Display Brightness“ (page 9). These brightness levels (in percent- ages of full brightness of the display) include: 100% (F0 HEX), 53% (F1HEX), 40% (F2HEX), 27% (F3HEX), 20% (F4HEX), 13% (F5HEX), and 6.6% (F6HEX). The brightness levels are controlled by chang- ing the duty factor of the row strobe pulse. Row and Column Location The SCD5510XA offers a unique Display Power Down feature which reduces ICC to less than 50 µA. When FFHEX is loaded, as shown in Table „Power Down“ (page 9), the display is set to 0% brightness and the internal multiplex clock is stopped. When in the Power Down mode data may still be written into the RAM. The dis- play is reactivated by loading a new Brightness Level Control Word into the display. The Lamp Test is enabled by loading F8 HEX, Table „Lamp Test“ (page 9), into the serial shift register. This Control Word sets all of the LEDs to a 53% brightness level. Operation of the Lamp Test has no affect on the RAM and is cleared by loading a Brightness Control Word. The Software Clear (C0HEX), given in Table „Software Clear“ (page 9), clears the Address Register and the RAM. The display is blanked and the Character Address Register will be set to Charac- ter 0. The internal counter and the Control Word Register are unaf- fected. The Software Clear will remain active until the next data input cycle is initiated. Load Character Address Op code D7 D6 D5 Character Address D4 D3 D2 D1 D0 Hex Operation Load 101 10 0 0 0 B0 Character 0 101 10 0 0 1 B1 Character 1 101 10 0 1 0 B2 Character 2 101 10 0 1 1 B3 Character 3 101 10 1 0 0 B4 Character 4 101 10 1 0 1 B5 Character 5 101 10 1 1 0 B6 Character 6 101 10 1 1 1 B7 Character 7 101 11 0 0 0 B8 Character 8 101 11 0 0 1 B9 Character 9 Load Column Data Op code D7 D6 D5 Column Data D4 D3 D2 D1 D0 Operation Load

000 C0 C1 C2 C3 C4 Row 0

001 C0 C1 C2 C3 C4 Row 1

010 C0 C1 C2 C3 C4 Row 2

011 C0 C1 C2 C3 C4 Row 3

100 C0 C1 C2 C3 C4 Row 4

Previously "on" LED On LED Off LED Columns Display Brightness Op code D7 D6 D5 Control Word D4 D3 D2 D1 D0 Hex Operation Level 111 10 0 0 0 F0 100% 111 10 0 0 1 F1 53% 111 10 0 1 0 F2 40% 111 10 0 1 1 F3 27% 111 10 1 0 0 F4 20% 111 10 1 0 1 F5 13% 111 10 1 1 0 F6 6.6% Power Down Op code D7 D6 D5 Control Word D4 D3 D2 D1 D0 Hex Operation Level 111 11 1 1 1 FF 0% brightness Lamp Test Op code D7 D6 D5 Control Word D4 D3 D2 D1 D0 Hex Operation Level 111 10 B B B Lamp Test (OFF) 111 11 0 0 1 F8 Lamp Test (OFF) Software Clear Op code D7 D6 D5 Control Word D4 D3 D2 D1 D0 Hex Operation Level 110 00 0 0 0 C0 CLEAR

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A 2006-02-20 10 Row Strobing Multiplexer and Display Driver The ten characters are row multiplexed with RAM resident column data. The strobe rate is established by the internal or external MUX Clock rate. The MUX Clock frequency is divided by a 320 counter chain. This results in a typical strobe rate of 750 Hz. By pulling the Clock SEL line low, the display can be operated from an external MUX Clock. The external clock is attached to the CLK I/O connection (pin 15). The maximum external MUX Clock frequency should be limited to 1.0 MHz. An asynchronous hardware Reset (pin 13) is also provided. Bring- ing this pin low will clear the Character Address Register, Control Word Register, RAM, and blanks the display. This action leaves the display set at Character Address 0, and the Brightness Level set at 100%. Electrical & Mechanical Considerations Interconnect Considerations Optimum product performance can be had when the following electrical and mechanical recommendations are adopted. The SCD5510XA’s IC is constructed in a high speed CMOS process, consequently high speed noise on the SERIAL DATA, SERIAL DATA CLOCK, LOAD and RESET lines may cause incorrect data to be written into the serial shift register. Adhere to transmission line termination procedures when using fast line drivers and long cables (>10 cm). Good digital grounds (pins 14, 28) and power supply decoupling (pins 6, 9, 20, 23) will insure that ICC (<400 mA peak) switching currents do not generate localized ground bounce. Therefore it is recommended that each display package use a 0.1 µF and 20 µF capacitor between VCC and ground. When the internal MUX Clock is being used connect the CLKSEL pin to VCC. In those applications where RESET will not be con- nected to the system’s reset control, it is recommended that this pin be connected to the center node of a series 0.1 µF and 100 kΩ RC network. Thus upon initial power up the RESET will be held low for 10 ms allowing adequate time for the system power supply to stabilize. The SCD5510XA allows up to 1.7 W of power dissipation at 70° and 1.29 W power dissipation at a maximum operating tempera - ture of 85°C. Approximately 60% of this power is dissipated by the IC to the PC board via the VCC connection (pins 6, 9, 20, 23). Opti- mum thermal reliability is obtained by connecting all of the VCC pins to a common pad located on both sides of the PC board. This technique offers a low thermal resistance for IC to system ambi - ent. ESD Protection The input protection structure of the SCD55100A/1A/2A/3A/4A provides significant protection against ESD damage. It is capable of withstanding discharges greater than 2.0 kV. Take all the stan- dard precautions, normal for CMOS components. These include properly grounding personnel, tools, tables, and transport carriers that come in contact with unshielded parts. If these conditions are not, or cannot be met, keep the leads of the device shorted together or the parts in anti-static packaging. Soldering Considerations The SCD55100A/1A/2A/3A/4A can be hand soldered with SN63 solder using a grounded iron set to 260 °C. Wave soldering is also possible following these conditions: Pre- heat that does not exceed 93°C on the solder side of the PC board or a package surface temperature of 85°C. Water soluble organic acid flux (except carboxylic acid) or rosin-based RMA flux without alcohol can be used. Wave temperature of 245°C ± 5°C with a dwell between 1.5 sec. to 3.0 sec. Exposure to the wave should not exceed temperatures above 260°C for five seconds at 1.59 mm (0.063") below the seat- ing plane. The packages should not be immersed in the wave. Post Solder Cleaning Procedures The least offensive cleaning solution is hot D.I. water (60 °C) for less than 15 minutes. Addition of mild saponifiers is acceptable. Do not use commercial dishwasher detergents. For faster cleaning, solvents may be used. Exercise care in choos- ing solvents as some may chemically attack the nylon package. Maximum exposure should not exceed two minutes at elevated tem peratures. Acceptable solvents are TF (trichlorotrifluorethane), TA, 111 Trichloroethane, and unheated acetone.(1) Note: 1) Acceptable commercial solvents are: Basic TF , Arklone, P . Genesolv, D. Genesolv DA, Blaco-Tron TF and Blaco-Tron TA. Unacceptable solvents contain alcohol, methanol, methylene chloride, ethanol, TP35, TCM, TMC, TMS+, TE, or TES. Since many commercial mixtures exist, contact a solvent vendor for chemical composition information. Some major solvent manufac turers are: Allied Chemical Corp oration, Specialty Chemical Divi - sion, Morristown, NJ; Baron-Blakeslee, Chicago, IL; Dow Chemical, Midland, MI; E.I. DuPont de Nemours & Co., Wilming - ton, DE. IDXX5188 Row 0 Row 1 Row 2 Row 3 Row 4 01234 Columns Load Row 0 Load Row 4 Columns 10 2 3 Row 3 Row 1 Row 0 Row 2 Load Row 1 Columns Row 4 10 2 43 Load Row 2 Row 2 Row 1 Row 3 Row 0 Row 4 Columns 213 4 Load Row 3 Row 0 Row 3 Row 1 Row 2 Row 4 Columns 012 4 3 Row 2 Row 1 Row 3 Row 0 Load Row 4Row

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A 2006-02-20 11 For further information refer to Appnotes 18 and 19 at www.osram-os.com An alternative to soldering and cleaning the display modules is to use sockets. Naturally, 28 pin DIP sockets 7.62 mm (0.300") wide with 2.54 mm (0.100") centers work well for single displays. Multiple display assemblies are best handled by longer SIP sockets or DIP sockets when available for uniform package alignment. Socket manufacturers are Aries Electronics, Inc., Frenchtown, NJ; Garry Manufacturing, New Brunswick, NJ; Robinson-Nugent, New Albany, IN; and Samtec Electronic Hardward, New Albany, IN. For further information refer to Appnote 22 at www.osram-os.com Optical Considerations The 3.683 mm (0.145") high character of the SCD5510XA gives readability up to eight feet. Proper filter selection enhances readability over this distance. Using filters emphasizes the contrast ratio between a lit LED and the character background. This will increase the discrimination of differ- ent characters. The only limitation is cost. Take into consideration the ambient lighting environment for the best cost/benefit ratio for filters. Incandescent (with almost no green) or fluorescent (with almost no red) lights do not have the flat spectral response of sunlight. Plastic band-pass filters are an inexpensive and effective way to strengthen contrast ratios. The SCD5510A/2A are red/high efficiency red dis- plays and should be matched with long wavelength pass filter in the 570 nm to 590 nm range. The SCD55103A/4A should be matched with a yellow-green band-pass filter that peaks at 565 nm. For displays of multiple colors, neutral density grey filters offer the best compro- mise. SCD Interface with Siemens/Intel 8031 Microprocessor (using serial port in mode 0) IDCD5221 XTAL2 RxD18 10

19 XTAL1

RST9 17P3.7 13P3.3 P3.4 14 8031 TxD 11 CLK LOAD DATA CCV

40 SCD

0.01 µF 22 µF

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A Additional contrast enhancement is gained by shading the displays. Plastic band-pass filters with built-in louvers offer the next step up in contrast improvement. Plastic filters can be improved further with anti-reflective coatings to reduce glare. The trade-off is fuzzy characters. Mounting the filters close to the display reduces this effect. Take care not to overheat the plastic filter by allowing for proper air flow. Optimal filter enhancements are gained by using circular polarized, anti-reflective, band-pass filters. The circular polarizing further enhances contrast by reducing the light that travels through the filter and reflects back off the display to less than 1%. Several filter manufacturers supply quality filter materials. Some of them are: Panelgraphic Corporation, W. Caldwell, NJ; SGL Homalite, Wilmington, DE; 3M Company, Visual Products Division, St. Paul, MN; Polaroid Corporation, Polarizer Division, Cambridge, MA; Marks Polarized Corporation, Deer Park, NY , Hoya Optics, Inc., Fremont, CA. One last note on mounting filters: recessing displays and bezel assemblies is an inexpensive way to provide a shading effect in overhead CA; Photo Chemical Products of California, Santa Monica, CA; I.E.E.–Atlas, Van Nuys, CA. Microprocessor Interface The microprocessor interface is through the serial port, SPI port or one out of eight data bits on the eight bit parallel port and also control lines SDCLK and LOAD. Power Up Sequence Upon power up display will come on at random. Thus the display should be reset at power-up. The reset will set the Address Register to Digit 0, User RAM is set to 0 (display blank) the Control Word is set to 0 (100% brightness with Lamp Test off) and the internal counters are reset. SCD5510XA Interface with Siemens/Intel 8031 Microprocessor CCV P0.0 P3.6 P3.1 P3.0 P1.0 RST 8031 XTAL1 XTAL2 CCV CCV Slave CC LOADCLK SD 1 2 DATA V Master 1369 1 4 SCD 20 16 CLK SD LOAD 2728 DATA 14139 SCD 19 15 22 µF + TAN 0.01 µF IDCD5222

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A 2006-02-20 13 SCD5510XA Interface with Motorola 68HC05C4 Microprocessor (using SPI port) Cascading Multiple Displays Multiple displays can be cascaded using the CLKSEL and CLK I/O pins as shown below. The display designated as the Master Clock source should have its CLKSEL pin tied high and the slaves should have their CLKSEL pins tied low. All CLK I/O pins should be tied together. One display CLK I/O can drive 15 slave CLK I/Os. Use RST to synchronize all display counters. Cascading Multiple Displays IDCD5223 CCV MOSI SCLK PA1 PA0 PA2 RST 68HC05C4 OSC2 OSC1 CCV CCV SD CLK LOAD 12 6 139 DATA SCD Master 28 27 23 1920 CCV TAN 22 µFSCD Slave SD CLK LOAD DATA 91 3 1 4 2015 28 27 23 19 16 15 0.01 µF IDCD5030 RST CLK SEL Intelligent Display CCV DATA SDCLK LOAD 14 more displays in between DATA SDCLK Decoder Address Address Decode 1-14 RST CLK I/O Intelligent Display DATA RST SDCLK CLK I/O LOAD CLK SEL Chip 15A2 LD CE

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A 2006-02-20 14 Loading Data Into the Display Use following procedure to load data into the display: 1. Power up the display. 2. Bring RST low (600 ns duration minimum) to clear the Multi- plex Counter, Address Register, Control Word Register, User Ram and Data Register. The display will be blank. Dis- play brightness is set to 100%. 3. If a different brightness is desired, load the proper brightness opcode into the Control Word Register. 4. Load the Digit Address into the display. 5. Load display row and column data for the selected digit. 6. Repeat steps 4 and 5 for all digits. Data Contents for the Word “Displays” Step D7 D6 D5 D4 D3 D2 D1 D0 Function A B (optional) 11 0 11 1 000 0 0 10B B B CLEAR BRIGHTNESS SELECT 10 1 00 0 00 1 01 0 01 1 10 0 100 00 111 10 100 01 100 01 100 01 111 10 DIGIT D0 SELECT ROW 0 D0 (D) ROW 1 D0 (D) ROW 2 D0 (D) ROW 3 D0 (D) ROW 4 D0 (D) 10 1 00 0 00 1 01 0 01 1 10 0 100 01 011 10 001 00 001 00 001 00 011 10 DIGIT D1 SELECT ROW 0 D1 (I) ROW 1 D1 (I) ROW 2 D1 (I) ROW 3 D1 (I) ROW 4 D1 (I) 10 1 00 0 00 1 01 0 01 1 10 0 10010 01111 10000 01110 00001 11110 DIGIT D2 SELECT ROW 0 D2 (S) ROW 1 D2 (S) ROW 2 D2 (S) ROW 3 D2 (S) ROW 4 D2 (S) 10 1 00 0 00 1 01 0 01 1 10 0 10011 11110 10001 11110 10000 10000 DIGIT D3 SELECT ROW 0 D3 (P) ROW 1 D3 (P) ROW 2 D3 (P) ROW 3 D3 (P) ROW 4 D3 (P) 10 1 00 0 00 1 01 0 01 1 10 0 10100 10000 10000 10000 10000 11111 DIGIT D4 SELECT ROW 0 D4 (L) ROW 1 D4 (L) ROW 2 D4 (L) ROW 3 D4 (L) ROW 4 D4 (L) 10 1 00 0 00 1 01 0 01 1 10 0 101 0 1 001 0 0 010 1 0 111 1 1 100 0 1 100 0 1 DIGIT D5 SELECT ROW 0 D5 (A) ROW 1 D5 (A) ROW 2 D5 (A) ROW 3 D5 (A) ROW 4 D5 (A) 10 1 00 0 00 1 01 0 01 1 10 0 1 0110 1 0001 0 1010 0 0100 0 0100 0 0100 DIGIT D6 SELECT ROW 0 D6 (Y) ROW 1 D6 (Y) ROW 2 D6 (Y) ROW 3 D6 (Y) ROW 4 D6 (Y) 10 1 00 0 00 1 01 0 01 1 10 0 10111 01111 10000 01110 00001 11110 DIGIT D7 SELECT ROW 0 D7 (S) ROW 1 D7 (S) ROW 2 D7 (S) ROW 3 D7 (S) ROW 4 D7 (S) Note: If the display is already reset at Power Up, there is no need for Software Clear.

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A 2006-02-20 15 User Definable Character Set Examples* Upper and Lower Case Alphabets Numerals and Punctuation *CAUTION: No more than 128 LEDs “on” at one time at 100% brightness. IDCS5089 HEX CODE CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX 04 1E 8E00 IDCS5090 HEX CODE CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX 0E 04

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A User Definable Character Set Examples* (continued) Scientific Notations, etc. Foreign Characters *CAUTION: No more than 128 LEDs “on” at one time at 100% brightness. IDCS5091 HEX CODE CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX 06 04 IDCS5092 HEX CODE CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX CODE HEX 1F 1F

SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A 2006-02-20 17 Published by OSRAM Opto Semiconductors GmbH Wernerwerkstrasse 2, D-93049 Regensburg www.osram-os.com © All Rights Reserved. Attention please! The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact our Sales Organization. If printed or downloaded, please find the latest version in the Internet. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1) may only be used in life-support devices or systems2) with the express written approval of OSRAM OS. 1) A critical component is a component used in a life-support devi ce or system whose failure can reasonably be expected to cause t he failure of that life-support device or system, or to affect its safety or the effectiveness of that device or system. 2) Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and susta in human life. If they fail, it is reasonable to assume that the health and the life of the user may be endangered. Revision History: 2006-02-20 Previous Version: 2004-12-02 Page Subjects (major changes since last revision) Date of change all Lead free device 2006-01-23