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SCAN90004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis datasheet (Rev. P)

Document overview

Manufacturer or author: Texas Instruments, Incorporated [SNLS182,P]
PDF pages: 16

Technical content

www.ti.com SNLS182P –MAY 2005–REVISED APRIL 2013 SCAN900044-ChannelLVDSBuffer/Repeater withPre-Emphasis Check forSamples: SCAN90004 1FEATURES DESCRIPTION The SCAN90004 isa fourchannel1.5 Gbps LVDS 2• 1.5Gbps Maximum Data Rate Per Channel buffer/repeater.High speed data paths and flow-• ConfigurablePre-emphasis DrivesLossy through pinoutminimize internaldevice jitterandBackplanes and Cables simplifyboard layout, while configurablepre-

Low Output Skew and Jitter emphasis overcomes ISI jittereffectsfrom lossy backplanes and cables. The differentialinputs• LVDS/CML/LVPECL Compatible Input,LVDS interfaceto LVDS, and Bus LVDS signalssuch asOutput thoseon TI's10-,16-,and 18-bitBus LVDS SerDes,• On-chip 100Ω Inputand Output Termination as wellas CML and LVPECL. The differentialinputs
12 kV ESD Protectionon LVDS Outputs and outputsare internallyterminatedwitha 100Ω resistorto improveperformanceand minimizeboard• IEEE 1149.1JTAG Interface space.The repeaterfunctionisespeciallyusefulfor• IEEE 1149.6LimitedCapability boostingsignalsforlongerdistancetransmissionover
FaultInsertion lossycablesand backplanes.
Single3.3VSupply IntegratedtestabilitycircuitrysupportsIEEE1149.1
Very Low Power Consumption (JTAG) on single-endedLVTTL/CMOS I/O and limited IEEE1149.6 capabilityon high-speed• Industrial-40to+85°C Temperature Range differentialLVDS interconnects.The 3.3V supply,• Small TQFP Package Footprint CMOS process,and LVDS I/O ensure stablehigh
See DS90LV004 forNon-JTAG Version performanceatlow power overtheentireindustrial- 40 to+85°C temperaturerange. TypicalApplication Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

IEEE 1149.1 TAP (JTAG) & 1149.6 Pre-emphasis and Control OUT0+ OUT0-IN0- IN0+ OUT1+ OUT1-IN1- IN1+ OUT2+ OUT2-IN2- IN2+ OUT3+ OUT3-IN3- IN3+ 13 2414 21 2216 2317 1815 19 20 48 3747 40 3945 3844 4346 42 41 SCAN90004 (TQFP) PEM0 PEM1 VDD VDD VDD N/C VDD GND GND VDD VDD PWDN N/C TDO TDI VDD VDD N/C N/C VDD VDD TMS TCK TRST IN0+ IN0- IN1+ IN1- GND GND IN2+ IN2- IN3+ IN3- GND GND OUT0+ OUT0- OUT1+ OUT1- GND GND OUT2+ OUT2- OUT3+ OUT3- GND GND SCAN90004 SNLS182P –MAY 2005–REVISED APRIL 2013 www.ti.com Block and Connection Diagrams Figure1.SCAN90004 Block Diagram Figure2.Pinout-Top View Pin Descriptions Pin TQFP Pin I/O,Type DescriptionName Number DIFFERENTIAL INPUTS IN0+ 13 I,LVDS Channel0 invertingand non-invertingdifferentialinputs. IN0− 14 IN1+ 15 I,LVDS Channel1 invertingand non-invertingdifferentialinputs. IN1− 16 IN2+ 19 I,LVDS Channel2 invertingand non-invertingdifferentialinputs. IN2− 20 IN3+ 21 I,LVDS Channel3 invertingand non-invertingdifferentialinputs. IN3− 22 DIFFERENTIAL OUTPUTS OUT0+ 48 O, LVDS Channel0 invertingand non-invertingdifferentialoutputs.(1) OUT0 − 47 OUT1+ 46 O, LVDS Channel1 invertingand non-invertingdifferentialoutputs.(1) OUT1 − 45 OUT2+ 42 O, LVDS Channel2 invertingand non-invertingdifferentialoutputs.(1) OUT2 − 41 OUT3+ 40 O, LVDS Channel3 invertingand non-invertingdifferentialoutputs.(1) OUT3- 39 DIGITAL CONTROL INTERFACE PWDN 12 I,LVTTL A logiclowatPWDN activatesthehardwarepower down mode. (1) The LVDS outputsdo notsupporta multidrop(BLVDS) environment.The LVDS outputcharacteristicsoftheSCAN90004 devicehave been optimizedforpoint-to-pointbackplaneand cableapplications.

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www.ti.com SNLS182P –MAY 2005–REVISED APRIL 2013 Pin Descriptions(continued) Pin TQFP Pin I/O,Type DescriptionName Number PEM0 1 I,LVTTL Pre-emphasisControlInputs(affectsallChannels) PEM1 2 TDI 34 I,LVTTL TestData InputtosupportIEEE 1149.1features TDO 35 O, LVTTL TestData OutputtosupportIEEE 1149.1features TMS 27 I,LVTTL TestMode SelecttosupportIEEE 1149.1features TCK 26 I,LVTTL TestClocktosupportIEEE 1149.1features TRST 25 I,LVTTL TestResettosupportIEEE 1149.1features POWER VDD 3,4,5,7,10,11,28,29,32,33 I,Power VDD = 3.3V,±5% GND 8,9,17,18,23,24,37,38,43,44 I,Power Ground N/C 6,30,31,36 No Connect These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1) SupplyVoltage(VDD ) −0.3Vto+4.0V CMOS InputVoltage -0.3Vto(VDD +0.3V) LVDS InputVoltage(2) -0.3Vto(VDD +0.3V) LVDS OutputVoltage -0.3Vto(VDD +0.3V) LVDS OutputShortCircuitCurrent +40 mA JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature(Solder,4sec) 260°C Max Pkg Power Capacity@ 25°C 1.64W ThermalResistance(θJA) 76°C/W Package Deratingabove +25°C 13.2mW/°C ESD LastPassingVoltage(LVDS output HBM, 1.5kΩ,100pF 12kV pins) EIAJ,0Ω,200pF 250V ESD LastPassingVoltage(Allotherpins) HBM, 1.5kΩ,100pF 8kV EIAJ,0Ω,200pF 250V (1) Absolutemaximum ratingsarethosevaluesbeyond whichdamage tothedevicemay occur.The databookspecificationsshouldbe met, withoutexception,toensurethatthesystemdesignisreliableoveritspower supply,temperature,and output/inputloadingvariables.TI does notrecommend operationofproductsoutsideofrecommended operationconditions. (2) VID max < 2.4V Recommended OperatingConditions SupplyVoltage(VDD ) 3.15Vto3.45V InputVoltage(VI) (1) 0V toVDD OutputVoltage(VO ) 0V toVDD OperatingTemperature(TA)Industrial −40°C to+85°C (1) VID max < 2.4V Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SCAN90004

SNLS182P –MAY 2005–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ (1) Max Units LVTTL DC SPECIFICATIONS (PWDN, PEM0, PEM1, TDI,TDO, TCK, TMS, TRST) VIH HighLevelInputVoltage 2.0 VDD V VIL Low LevelInputVoltage GND 0.8 V IIH HighLevelInputCurrent VIN = VDD = VDDMAX −10 +10 µA IIL Low LevelInputCurrent VIN = VSS ,VDD = VDDMAX −10 +10 µA IILR Low LevelInputCurrent TDI,TMS, TRST -40 -200 µA C IN1 InputCapacitance Any DigitalInputPintoVSS 3.5 pF C OUT1 OutputCapacitance Any DigitalOutputPintoVSS 5.5 pF VCL InputClamp Voltage ICL = −18 mA −1.5 −0.8 V VOH HighLevelOutputVoltage IOH = −12 mA, VDD = 3.15V 2.4 V (TDO) IOH = −100 µA,VDD = 3.15V VDD -0.2 V VOL Low LevelOutputVoltage IOL = 12 mA, VDD = 3.15V 0.5 V (TDO) IOL = 100 µA,VDD = 3.15V 0.2 V IOS OutputShortCircuitCurrent TDO −15 −125 mA IOZ OutputTRI-STATE Current TDO −10 +10 µA LVDS INPUT DC SPECIFICATIONS (INn±) VTH DifferentialInputHighThreshold VCM = 0.8Vto3.4V, 0 100 mV(2) VDD = 3.45V VTL DifferentialInputLow Threshold VCM = 0.8Vto3.4V, −100 0 mV(2) VDD = 3.45V VID DifferentialInputVoltage VCM = 0.8Vto3.4V,VDD = 3.45V 100 2400 mV VCMR Common Mode VoltageRange VID = 150 mV, VDD = 3.45V 0.05 3.40 V C IN2 InputCapacitance IN+ orIN− toVSS 5.2 pF IIN InputCurrent VIN = 3.45V,VDD = VDDMAX −10 +10 µA VIN = 0V,VDD = VDDMAX −10 +10 µA LVDS OUTPUT DC SPECIFICATIONS (OUTn ±) VOD DifferentialOutputVoltage, R L = 100Ω externalresistorbetween OUT+ and 250 500 600 mV0% Pre-emphasis(2) OUT − ΔVOD Change inVOD between -35 35 mVComplementaryStates VOS OffsetVoltage(3) 1.05 1.18 1.475 V ΔVOS Change inVOS between -35 35 mVComplementaryStates IOS OutputShortCircuitCurrent OUT+ orOUT − ShorttoGND −60 −90 mA C OUT2 OutputCapacitance OUT+ orOUT − toGND when TRI-STATE 5.5 pF SUPPLY CURRENT (Static) ICC SupplyCurrent Allinputsand outputsenabledand active, terminatedwithexternaldifferentialloadof100Ω 117 140 mA between OUT+ and OUT-, 0% pre-emphasis ICCZ SupplyCurrent-Power Down PWDN = L,0% pre-emphasis 2.7 6 mAMode SWITCHING CHARACTERISTICS — LVDS OUTPUTS tLHT DifferentialLow toHighTransitionUse an alternating1 and 0 patternat200 Mb/s, 210 300 psTime measure between 20% and 80% ofVOD .(4) tHLT DifferentialHightoLow Transition 210 300 psTime (1) Typicalparametersaremeasured atVDD = 3.3V,TA = 25°C. They areforreferencepurposes,and arenotproduction-tested. (2) DifferentialoutputvoltageVOD isdefinedas ABS(OUT+ –OUT −).DifferentialinputvoltageVID isdefinedas ABS(IN+–IN−). (3) OutputoffsetvoltageVOS isdefinedas theaverageoftheLVDS single-endedoutputvoltagesatlogichighand logiclowstates. (4) Not productiontested.Specifiedby a statisticalanalysison a sample basisatthetimeofcharacterization.

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www.ti.com SNLS182P –MAY 2005–REVISED APRIL 2013 ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ (1) Max Units tPLHD DifferentialLow toHigh Use an alternating1 and 0 patternat200 Mb/s, 2.0 3.2 nsPropagationDelay measure at50% VOD between inputtooutput. tPHLD DifferentialHightoLow 2.0 3.2 nsPropagationDelay tSKD1 PulseSkew |tPLHD –tPHLD |(4) 25 80 ps tSKCC OutputChanneltoChannelSkew Differenceinpropagationdelay(tPLHD ortPHLD ) 50 125 psamong alloutputchannels.(4) tSKP ParttoPartSkew (4) Common edge,partsatsame temp and VCC (4) 1.1 ns tJIT Jitter(0% Pre-emphasis)(5) RJ -Alternating1 and 0 at750 MHz (6) 1.1 1.5 psrms DJ -K28.5Pattern,1.5Gbps (7) 43 62 psp-p TJ -PRBS 223-1Pattern,1.5Gbps (8) 35 85 psp-p tON LVDS OutputEnableTime Time fromPWDN toOUT ± change fromTRI-STATE 300 nstoactive. tOFF LVDS OutputDisableTime Time fromPWDN toOUT ± change fromactiveto 12 nsTRI-STATE. SWITCHING CHARACTERISTICS — SCAN FEATURES fMAX Maximum TCK ClockFrequency R L = 500Ω, 25.0 MHz C L = 35 pFtS TDI toTCK, H orL 3.0 ns tH TDI toTCK, H orL 0.5 ns tS TMS toTCK, H orL 2.5 ns tH TMS toTCK, H orL 0.5 ns tW TCK PulseWidth,H orL 10.0 ns tW TRST PulseWidth,L 2.5 ns tREC RecoveryTime,TRST toTCK 1.0 ns (5) Jitterisnotproductiontested,butspecifiedthroughcharacterizationon a sample basis. (6) Random Jitter,orRJ,ismeasured RMS witha histogramincluding1500 histogramwindow hits.The inputvoltage= VID = 500mV, 50% dutycycleat750MHz, tr = tf= 50ps (20% to80%). (7) DeterministicJitter,orDJ,ismeasured toa histogrammean witha sample sizeof350 hits.The inputvoltage= VID = 500mV, K28.5 patternat1.5Gbps, tr = tf= 50ps (20% to80%).The K28.5patternisrepeatingbitstreamsof(00111110101100000101). (8) TotalJitter,orTJ,ismeasured peak topeak witha histogramincluding3500 window hits.Stimulusand fixturejitterhas been subtracted.The inputvoltage= VID = 500mV, 223-1PRBS patternat1.5Gbps, tr = tf= 50ps (20% to80%). Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SCAN90004

SNLS182P –MAY 2005–REVISED APRIL 2013 www.ti.com FEATURE DESCRIPTIONS INTERNAL TERMINATIONS The SCAN90004 has integratedterminationresistorson both the inputand outputs.The inputshave a 100Ω resistoracrossthedifferentialpair,placingthereceiverterminationas closeas possibletotheinputstageofthe device.The LVDS outputsalsocontainan integrated100Ω ohm terminationresistor,thisresistorisused to reducetheeffectsofNear End Crosstalk(NEXT) and does nottaketheplaceofthe100 ohm terminationatthe inputsto the receivingdevice.The integratedterminationsimprovesignalintegrityand decreasethe external component countresultinginspace savings. OUTPUT CHARACTERISTICS The outputcharacteristicsof the SCAN90004 have been optimizedforpoint-to-pointbackplaneand cable applications,and arenotintendedformultipointormultidropsignaling. POWERDOWN MODE The PWDN inputactivatesa hardwarepowerdown mode. When thepowerdown mode isactive(PWDN=L), all inputand outputbuffersand internalbias circuitryare powered offand disabled.Outputs are tri-statedin powerdown mode. JTAG Circuitryisactiveper theIEEE standard,butdoes notswitchunlessTCK istoggling. When exitingpowerdown mode, thereisa delayassociatedwithturningon bandgap referencesand input/output buffercircuitsas indicatedintheLVDS OutputSwitchingCharacteristics Upon assertingthepower down function(PWDN = Low),and ifthePre-emphasisfeatureisenable,itispossible forthe driveroutputto sourcecurrentfora shortamount of timeliftingthe outputcommon mode to VDD . To preventthisoccurrence,a load dischargepulldown path can be used on eitheroutput(1 kΩ to ground recommended). Alternately,a commonly deployed externalfailsafenetwork willalso providethispath (see INPUT FAILSAFE BIASING ).The occurrenceofthisisapplicationdependant,and parametersthatwillaffectif thisisofconcerninclude:AC coupling,use ofthepowerdown feature,presenceofthedischargepath,presence ofthefailsafebiasing,theusage ofthepre-emphasisfeature,and inputcharacteristicsofthedownstream LVDS Receiver. PRE-EMPHASIS Pre-emphasisdramaticallyreducesISIjitterfromlongorlossytransmissionmedia.Two pinsareused toselect thepre-emphasislevelforalloutputs:off,low,medium, orhigh. Table1.Pre-emphasis ControlSelectionTable PEM1 PEM0 Pre-Emphasis 0 0 Off 0 1 Low 1 0 Medium 1 1 High INPUT FAILSAFE BIASING FailsafebiasingoftheLVDS linkshouldbe consideredifthedownstream ReceiverisON and enabledwhen the sourceisinTRI-STATE, powered off,or removed.Thiswillseta validknown inputstatetotheactivereceiver. Thisisaccomplishedby usinga pullup resistortoVDD on the‘plus’line,and a pulldown resistortoGND on the ‘minus’line.Resistorvaluesare inthe750 Ω toseveralk Ω range.The exactvaluedepends upon thedesired common mode biaspoint,terminationresistor(s)and desiredinputdifferentialvoltagesetting.Please referto applicationnoteAN-1194 (SNLA051 ) “FailsafeBiasingofLVDS interfaces” formore informationand a general discussion.

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100: Differential T-Line 100: LVDS Driver SCAN90004 www.ti.com SNLS182P –MAY 2005–REVISED APRIL 2013 Design-for-Test(DfT)Features IEEE 1149.1(JTAG) SUPPORT The SCAN90004 supportsa fullycompliantIEEE 1149.1interface.The TestAccess Port(TAP) providesaccess toboundaryscan cellsateach LVTTL I/Oon thedeviceforinterconnecttesting.Differentialpinsareincludedin thesame boundaryscan chainbutinsteadcontainIEEE1149.6cells.IEEE1149.6istheimprovedIEEE standard fortestinghigh-speeddifferentialsignals. RefertotheBSDL filelocatedon TI’s websiteforthedetailsoftheSCAN90004 IEEE 1149.1implementation. IEEE 1149.6SUPPORT AC-coupled differentialinterconnectionson very high speed (1+ Gbps) data paths are not testableusing traditionalIEEE 1149.1 techniques.The IEEE 1149.1 structuresand methods are intendedto teststatic(DC- coupled),singleended networks.IEEE 1149.6istargetedforthetestingofhigh-speeddifferential(includingAC coupled)networks.The SCAN90004 includescircuitrytosupportAC-coupledtestingon alldifferentialinputsand outputsand offerslimitedtestcapability.The limitationsare due to severalapplicationspecificfactors(board layout,capacitorvalue,data rateetc.),and alsoIO compliance(LVDS linksingeneralare DC coupled).The SCAN90004 has notbeen testedforfullcomplianceorfullcompatibilitytotheIEEE1149.6standard.Testingof the deviceinthe targetedapplicationwiththe appropriateJTAG softwarewilldeterminewhat extentof IEEE 1149.6supportisprovidedby thedevice. FAULT INSERTION FaultInsertionisa techniqueused toassistintheverificationand debug ofdiagnosticsoftware.Duringsystem testingfaultsare "injected"tosimulatehardwarefailureand thushelpverifythemonitoringsoftwarecan detect and diagnose these faults.In the SCAN90004 an IEEE1149.1 "stuck-at"instructioncan createa stuck-at condition,eitherhigh or low,on any pin or combinationof pins.A more detaileddescriptionof the stuck-at featurecan be foundinTIApplicationsnoteAN-1313 (SNLA060 ). ApplicationInformation INPUT INTERFACING The SCAN90004 acceptsdifferentialsignalsand allowsimpleAC or DC coupling.With a wide common mode range,theSCAN90004 can be DC-coupledwithallcommon differentialdrivers(i.e.LVPECL, LVDS, CML). The followingthreefiguresillustratetypicalDC-coupled interfaceto common differentialdrivers.Note thatthe SCAN90004 inputsareinternallyterminatedwitha 100Ω resistor. Figure3. TypicalLVDS DriverDC-Coupled InterfacetoSCAN90004 Input Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SCAN90004

100: 100: Differential T-Line Differential Receiver SCAN90004 Driver 100: OUT+ OUT- 150-250: 100: Differential T-Line LVDS Receiver IN+ IN- 100: LVPECL Driver 150-250: OUT+ OUT- 50:50: VCC CML3.3V or CML2.5V Driver 100: Differential T-Line SCAN90004 Receiver IN+ IN- 100: SCAN90004 SNLS182P –MAY 2005–REVISED APRIL 2013 www.ti.com Figure4. TypicalCML DriverDC-Coupled InterfacetoSCAN90004 Input Figure5. TypicalLVPECL DriverDC-Coupled InterfacetoSCAN90004 Input OUTPUT INTERFACING The SCAN90004 outputssignalsthatare complianttotheLVDS standard.Theiroutputscan be DC-coupledto most common differentialreceivers.Figure6 illustratestypicalDC-coupled interfaceto common differential receiversand assumes thatthereceivershave highimpedance inputs.Whilemost differentialreceivershave a common mode inputrange thatcan accommodate LVDS compliantsignals,itis recommended to check respectivereceiver'sdatasheetpriortoimplementingthesuggestedinterfaceimplementation. Figure6. TypicalSCAN90004 Output DC-Coupled Interfacetoan LVDS, CML or LVPECL Receiver

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POWER SUPPLY CURRENT (mA) 350 BIT DATA RATE (Gbps) 100 150 200 250 300 1.25 PRBS-23, 0% PRE PRBS-23, Max PRE Clock, 0% PRE Clock, Max PRE TOTAL JITTER - tJ (ps) 120 BIT DATA RATE (Gbps) 0 0.5 1.0 1.5 2.0 100 VCM = 0.25V VCM = 0.5V VCM = 1.2V VCM = 3.05V VCM = 2.4V SCAN90004 www.ti.com SNLS182P –MAY 2005–REVISED APRIL 2013 TypicalPerformance Characteristics Power Supply Current TotalJitter(TJ) vs. vs. BitData Rate BitData Rate Dynamic power supplycurrentwas measured while TotalJittermeasured at0V differentialwhile runninga clockorPRBS 223-1pattern runninga PRBS 223-1pattern withall4 channelsactive. witha singlechannelactive. Figure7. Figure8. TotalJitter(U.I.) TotalJitter(U.I.) vs. vs. BitData Rate BitData Rate SCAN90004 as Driver SCAN90004 as Receiver TotalJittermeasured whileSCAN90004 outputis TotalJittermeasured atSCAN90004 receiveroutputs drivinga PRBS 27-1NRZ pattern afterreceivinga PRBS 27-1NRZ pattern witha singleactivechannelacrossa Belden1700A cable. overthespecifiedcablelength. Data measured atend ofspecifiedcablelength. datacollectedatreceiveroutputs, receiverlocatedatend ofspecifiedBelden1700A cablelength. Figure9. Figure10. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SCAN90004

TOTAL JITTER - tJ (ps) TEMPERATURE (° C) -40 0 40 60 100 -20 20 80 100 mV/Div 200 ps/Div 100% 50% 25% SCAN90004 SNLS182P –MAY 2005–REVISED APRIL 2013 www.ti.com TypicalPerformance Characteristics(continued) TotalJitter(TJ) PositiveEdge Transition vs. vs. Temperature Pre-emphasis Level TotalJittermeasured at0V differential whilerunninga PRBS 223-1pattern witha singlechannelactive. VCC = 3.3V,VID = 0.5V,VCM = 1.2V,1.5 Gbps datarate,0% Pre-emphasis Figure11. Figure12.

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www.ti.com SNLS182P –MAY 2005–REVISED APRIL 2013

REVISION HISTORY

www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) SCAN90004TVS/NOPB Active Production TQFP (PFB) | 48 250 | JEDEC TRAY (10+1) Yes SN Level-3-260C-168 HR -40 to 85 SCAN 90004TVS SCAN90004TVS/NOPB.A Active Production TQFP (PFB) | 48 250 | JEDEC TRAY (10+1) Yes SN Level-3-260C-168 HR -40 to 85 SCAN 90004TVS (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com PACKAGE OUTLINE C 48X 0.27 0.1744X 0.5 PIN 1 ID (0.13) TYP

0.05 MIN0 -7

4X 5.5 9.2

8.8 TYP

0.75 0.45 B7.2 6.8 NOTE 3 A 7.2 6.8 NOTE 3 0.25 GAGE PLANE

1.2 MAX

(1) PLASTIC QUAD FLATPACK TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MS-026. 13 24 3748

0.08 C A B

0.08 A 16 DETAIL A TYPICAL SCALE 1.900

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

(8.5) (8.5) 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM SYMM 48 37 13 24 SEE DETAILS METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP (8.5) (8.5) TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE SCALE:8X SYMM SYMM 48 37 13 24

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4-Channel LVDS Buffer/Repeater with Pre-Emphasis

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4-Channel LVDS Buffer/Repeater with Pre-Emphasis

Source title SCAN90004 Datasheet(PDF) - Texas Instruments

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