SC5104

SC5104 ETC1

Document overview

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Technical content

$C5104 - 64K X 4 BiCMOS ECL I/O STATIC RAM ee GENERAL DESCRIPTION FEATURES Silicon Connection's SC5104 is a fully static, . spee asyncronous random access memory, organized T2nSHS ns grades 65,536 words by 4 bits. The device is built using + Power Supply -5.2V + 10%, SCC's 1.0 micron BICMOS and features advanced * 100K compatible ECL VO's it techniques thi in12nS limes. circuit techniques that result in 12 nS access times. + Balanced read and write cycle times Writing and reading the memory is accomplished via + Up to 33% of write cycle timing Is industry standard timing and signals. To write the allowed for system skews memory the device must first be selected (S pulled . LOW) while enabling a write cycle (W pulled LOW). Power dissipation <1.1W Data on the input pins (DO - D3) will then be written + Soft Error rate less than 100 FITs into the memory address specified on the address + ESD protection greater than 2000 V pins (AO - A15). with latch-up Immunity > 200 mA To read the memory the device is selected (S pulled + High density, high performance 28-pin LOW) while the write enable (W) remains in the flatpack HIGH state. This will allow the memory contents of + 1.0 micron BICMOS Technology the current address (AO - A15) to be presented on output pins QO - Q3. The output pins (QO - Q3) will temain LOW (inactive) if either the chip select (S) is HIGH or write enable (W) is LOW. Top View _ Pin Names Do 1 28 s Dt 2 a b-w ‘Address Inputs 02 3 26 AIS 2 = D3 4 2 LA Chip Select Qo 5 421X538Ceramic 24: |--A13 Qi 6 Flatpak 23 Ai2 | 00-03 _| put a2 8 it Lead Pitcl 21 Vee ivy] Pr os fs 20 [ato AI 1 18 As a 12 vbw AB 13 16 AB Aa 14 15 AS

1 September 19, 1989

Silicon Connections - SC5104 PRELIMINARY Absolute Maximum Ratings AC Test Conditions LatCh-Up CUITE .eseeceeteceereeneieeeerter 2200 MA ——INPUt Pin (CIN) ssscsssnsnsntsesenetassssesseeeees BLO PF Output Pin (COUT) ...ssssseessseessseesssesssessesseess 8.0 PF W LOGIC DIAGRAM [A _TRUTH TABLE [s|wiofa] Move | ; —t> Aid Do v 2: [ELE TE TET ware |

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; o 1 PS Pi: tirtritt ‘ADDRESS Ver = -5.2V + 10%, Voc = Ground, Tc = 0°C to +85°C Symbol | Pavanaar | __Condons | in | Wax [Uni Output HIGH Voltage Vin = VidiMax) or Viqminy — [ -1025 | -880 | mv | Output LOW Voltage Loading with 50 ohms to -2.0v | -1810 |-1620 | mv | Output HIGH Voltage Vin = VIH(MIN) OF VIL(MAX) [-1025| | mv | Output LOW Voltage Loading with 50 ohms to-2.0v[ | -1620[ mv | : 2 September 19, 1989

Silicon Connections - SC5104 PRELIMINARY —_—_e eee SN OC EEIEINAR TY Read Cycle AC Timing Characteristics Vee =-5.2V + 10%, Voc = Ground, Tc = 0°C to +85°C [ sest0at2 | Scst0a5 | Symbol [Parameter in | Wax| Win | Moe [Un TAVAX | Address Valid to Address Invalid ee TAVQV | Address Valid to Output Valid | [2 [fs | ns | TAXQX | Address Invalid to Output Invalid [3 {| 8 [ 3 | 10 | ns | TSLSH | ChipSelectLOWtoChipSelectHiGH | 7 | | 7 | | ns | TSLQV | Chip Select LOW to Output Valid | [4] [4 [os] TSHQL | Chip Select HIGH to Output LOW [ [4] [4 [os] Read Cycle 1 ‘Chip Select is active prior to or within TAVQV-TSLOV after address valid RSSSSR OBIE TAVOV TAXOX Data out BSS] PREVIOUS DATA _ POR ROOT Ieseteccesnnecttoecancetaeatereeeseey RRR Read Cycle 2 Address is valid a minimum of TAVQV-TSLOV prior to Chip Select becoming active Chip Select A N

3 September 19, 1989

Silicon Connections - SC5104 PRELIMINARY Write Cycle 1 Write Cycle 1 is W controlled. This is established by S being held active (LOW) prior to W becoming active (LOW). TWLQL must be observed in Write Cycle 1 in order to avoid data bus cantention in common V/O applications, At the end of Write Cycle 1 data out may become active y if W becomes inactive (HIGH) prior to S becoming inactive (HIGH) AC Timing Characteristics Vee = -$.2V # 10%, Voc = Ground, Te = 0°C to +85°C [ sesioa-12 | scs10415 | [Symibor [Parameter an [ma [on [| o TAVAX | Address Valid to Address Invalid [2] [6] [ns | TWLSH | Write Enable LOW to Chip Select HIGH [3s | | 0 { [as | TDVWH | Data Valid to Write HIGH | s | [wo] [ns | TWHDX | Write HIGH to Data Don't Care fo | {of [as] TOL | WeteLOW to GutpulLOW Poe

2 TAVAX

SOOO ADDRESS VALID Beem ororoonreyl a7 y Z yp od YW Wt Wis MM HAX Wit Enable WLLL WLLL Yt Lads VL L4 TAVWL TWHDX Data In ——— VOLO OLO OOOO OOM OOOO OOOO OOOO OOOO L, BS} eeetetetetetatetetatetetetatatetecatatel stctatetetctclchotstcteete DATA VALID LASKY TWLQL __,| TWHQV Data Or : recestetshctshctstctstahctctebstetctctetchvenicererirevecicerecerenns : 4 September 19, 1989

Silicon Connections - SC5104 PRELIMINARY See eee eS ee CORELIMINAR YT Write Cycle 2 Write Cycle 2 is S controlled. This is established by W being active coincident with or prior to S becoming actiye (LOW). This cycle has identical specifications to Write Cycle 1 with the exceptions of S and W being interchanged. For common I/O applications this cycle may be more appropriate, as the data bus restrictions are eliminated. AC Timing Characteristics Vee = -5.2V + 10%, Voc = Ground, To = 0°C to +85°C [ scsto4-12 | scs104-15 | [| Symbol | Parameter | Min | Max | Min | Max | Units | TAVSL | Address Valid to Chip Select LOW fof [of {ns | TSLSH | Chip Select LOW to Chip Select HIGH [3 | [0] [as | TSLWH | Chip Select LOW to Write Enable HIGH |e { [wo] [as] TDVSH | Data Valid to Chip Select HIGH [fe {[ {| w] [ns | TSHDX | Chip Select HIGH to Data Don't Care fo] [of [as] TAVAX Addre EON ‘ADDRESS VALID ORO TSHAX TSLWH ay L y BD , Utéhda Wi MMM . TSHDX TDVSH Data In eaeesegemeneteatete ete tetatetatatatatatatatetatetateretenn DATA VALID ORR Data Low Low

5 September 19, 1989

Silicon Connections - SC5104 PRELIMINARY Consecutive Write Cycles AC Timing Characteristics Vee =-5.2V + 10%, Veo = Ground, Te =0°C to +85°C Write Enable HIGH to WriteEnableLow | 4 | [| 4 [| | ns | TSHSL_[ Chip Select HIGHto ChipSeletLow | 4 | | 4 | | as | Minimum Write Pulse Disable ADDRESS RRRRRQRQOV WRITE ENABLE Minimum Select Pulse Disable EEEEEEER CHIP SELECT Vee Figure 2 AC Test Circuit FIGURE 1 scsioe soos 80% 30% 08V Tagan 50% 50% 2 20% = tov tr y .7V tr = Rise Time cy =3pF ty = Fall Tis 0.1 UF. L 50% = Timing Reference = , Sohn

6 September 19, 1989

Silicon Connections - SC5104 PRELIMINARY Package Flat Pack 025 max | c— 01 WE -—— c——J a0 A1i3. ———) a A atta — _ vcc Ail ~S—390 Se 030+ .001 c——j a2 $C5104 VEE E———_ 002 009 090+ .015 oc Ai AaB -E——, oc aA As --———, | | ceadilial _ na .001 Jj. jee I 200 4 015 006 037 + .005

7 September 19, 1989

Silicon Connections - SC5104 PRELIMINARY Ordering Codes Order Placement Attention: Order Entry Silicon Connections Corporation 6160 Lusk Bivd., Suite C-204 San Diego, CA 92121 Phone: 619 - 535 - 0442 FAX: 619 - 535 - 1635 , 8 September 19, 1989