SC3010S

SC3010 ETC

Document overview

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Technical content

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 INFRARED REMOTE CONTROL TRANSMITTER

DESCRIPTION

SC3010 is a remote control transmitter utilizing CMOS Technology specially designed for use on general purpose (RC-5) infrared applications with low voltage supply and large debounce time. SC3010 supports 32 systems. Each system has a maximum of 64 commands; thus, SC3010 can provide up to a total of 2,048 commands.

FEATURES

• CMOS Technology * Low Voltage Supply * Supports up to 32 systems * Single Pin Oscillator * Bi-phase Transmission Technique * Provides 2,048 Commands

APPLICATIONS

• Television *V C R * Audio Equipment * Multi-Media System * Personal Computer DIP-28 SOP-28 /G3 /G3

ORDERING INFORMATION

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 BLOCK DIAGRAM OSC Test Mode Select Mode Selection Keyboard Encoder Master Reset Generator 8 7 14 28 Output Parallel to Serial converter Command and System Address Latch Control Unit Keyboard Driver Decoder DividerDecoder OSC SMS KI7 KI6 KI5 KI4 KI3 KI2 KI1 KI0 DOUT MDOUT Vss VDD KO7 KO0 KO6 KO5 KO4 KO3 KO2 KO1 ABSOLUTE MAXIMUM RATING (Tamb=25°C , unless otherwise specified) Characteristic Symbol Test conditions Value Unit Supply Voltage* V DD VSS -0.3 ~ 5.5 V Input Voltage* V IN VDD =3 V -0.5 ~ VDD +0.5 V Output Voltage* V OUT VDD =3 V -0.5 ~ VDD +0.5 V Operating Temperature T OPR VDD =3 V -20~85 °C NOTE: * = with reference to Vss

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 ELECTRICAL CHARACTERISTICS (Tamb=25°C, unless otherwise specified)/G3 Parameter Symbol Test conditions Min Typ Max Unit Supply Voltage V DD Freq=455KHz 2.0 3.0 5.5 V Stand-By Current I DD VDD =3V (Output no load) 0 10 µA Input Current(KI0~KI7,C0~C3) I IN VI=0V T1=0 T2=0 SMS=0 15 600 µA High Level Input Voltage (KI0~KI7,C0~C3,SMS,T1,T2) VIH VDD =3V,(KI0~KI7 And C0~C3 Connected To VDD ) 0.7 VDD V Low Level Input Voltage (KI0~KI7,C0~C3,SMS,T1,T2) VIL VDD =3V ,( T1,T2,OSC,SMS Connected To VSS ) 0.3 VDD V VI=3V VDD =3V T1=T2=High 0 1.0Input Current Leakage (KI0~KI7,C0~C3) ILEAK1 VI=0V VDD =3V T1=T2=High 0 1.0 µA ILEAK2 VI=0V VDD =3V T1=T2=High 0 1.0Input Current Leakage (OSC) ILEAK3 VI=3V VDD =3V T1=T2=High 4.5 15 30 µA VI=3V VDD =3V T=25°C0 1 . 0Input Leakage Current (SMS,T1,T2) ILEAK4 VI=0V VDD =3V T=25°C0 1 . 0 µA High Level Output Voltage (Dout, MDOUT ) VOH VDD =3V IOH =0.4mA VDD- 0.3 Low Level Output Voltage (Dout, MDOUT ) VOL VDD =3V IOH =0.6mA 0.35 V Vo=3V V DD =3V T=25°C1 0Output Current Leakage (Dout, MDOUT ) ILEAK5 Vo=0V V DD =3V T=25°C1 µA Low Level Output Voltage (KO0~KO7) VOL VDD =3V IOL =0.3mA 0.8 V Vo=3V V DD =3V T=25°C0 1Output Current Leakage (KO0~KO7) ILEAK6 Vo=3V V DD =3V T=-25~85°C3 1 0 µA Drive Current (Dout, MDout) ID V DD =3V Vo=1.5V 1.5 2 mA Operational Frequency Fosc1 V DD =3V 400 600 KHz Free-Running Frequency Fosc2 V DD =3V 50 100 KHz PIN DESCRIPTION Pin No. Symbol I/O Description NOTE

1 KI7 IP Key Sense Input Pin

2 SMS I System Mode Selection Input Pin

3~6 C0~C3 IP Key Sense Input Pins 7M D OUT O Generated Output Data Pin modulated with 1/12 oscillator frequency at a 25% duty factor 8D OUT O Generated Output Data Pin 9~13 KO7~KO3 OD Scan Driver Pins

14 V SS Power Negative Power Supply

15~17 KO2~KO0 OD Scan Driver Pins

18 OSC I Oscillator Input Pin

19 T2 I Test Pin 2

20 T1 I Test Pin 1

21~27 KI0~KI6 IP Key Sense Input Pins

28 V DD Power Positive Power Supply

IP= Input with p-channel pull-up transistor; OD = Output with open drain n-channel transistor

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 FUNCTIONAL DESCRIPTION 1. KEY INPUT OPERATION A Key Input Operation may be considered legal or illegal depending on the keys pressed. For key interconnection refer to the application circuit diagram in APPLICATION CIRCUIT SECTION. The maximum value of the switched key contact series resistance is 7kΩ . a). Legal Key Input A legal key input operation enables the device to activate the corresponding codes. A key input operation is considered as legal if it is 1). a connection of one K-Input (KI0~KI7) to one K-Output (KO0~KO7), or 2).a connection of one C-Input(C0~C3) to one K-Output (KO0~KO7) when the System Mode Selection (SMS) Pin is in a LOW state. If the SMS is in a HIGH state, then a wired connection must be made between a C-Input to a K-Output in order to generate the system number. For connections consisting of one K-Input or C-Input to more than one K-Output Pins, the last scan signal is recognized as LEGAL. b). Illegal Key Input An illegal key input operation does not produce any activity. No activity will be generated if 1) two or more K- Input/C-Input Pins or 2) C-Input and K-Input Pins are activated simultaneously. The oscillator will not start. Thus, this operation is considered as ILLEGAL. 2. INPUTS: KI0~KI7 & C0~C3 In the quiescent state, the command inputs KI0~KI7 are pulled HIGH by an internal pull-up transistor. Also if the system is quiescent and the System Mode Selection Input (SMS) is in High state so that current flow may be prevented. A wired connection in the C-KO Matrix provides 32 systems. 3. DATA OUTPUT Debounce Time (16-Bit Time) Scan Time (2-Bit Time) Start Bit Control Bit System Bits Command Bits LSBLSB MSB One Code First Code Second Code Repetition Time MSB Where: debounce time+ scan time=18 bit-times, Repetition time=4x16 bit-times Figure 1: Data Output Format

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 The generated information is transmitted through the output signal DOUT . The Data Output Code consists of 1.5 Start Bits (2xLogic 1), 1 Control Bit, 5 System Bits, and 6 Command Bits. Please refer to the diagram above for the data output format. (See also Command and System Matrixes). After a legal key operation is performed, the KO outputs are switched off and a 16-bit debounce time period is experienced followed by a 2-bit scan cycle time. During the scanning cycle the outputs are switched to the conductive state one at a time. Code is transmitted using a biphase technique. Please refer to the diagram below. The MDOUT Output Signal transmits the generated data modulated by 1/12 of the oscillator frequency with a 25% duty factor. Logic 1 Logic 0 where: 1 bit-time=3x28xTosc=1.688ms (typ. Tosc=1/455KHz) Figure 2: Biphase Code Transmission Technique Both the DOUT and the MDOUT are non-conducting (3-state outputs) when in the quiescent state. The Scan Driver Outputs (KO0~KO7) are open drain n-channel and conduct when the circuit is in the quiescent state. 4. SYSTEM MODES a). Combined System Mode (SMS=Low) The KI and the C Sense Inputs have p-channel pull-up transistors (meaning they are normally in HIGH state). They are pulled to LOW state when an output is connected, to them as a result of a legal key operation. A legal key operation in the KI-KO or C-KO Matrix will initiate a debounce cycle. Once key contact has been established for 18- bit time without any interruption, the Oscillator Enable Signal is latched and the key may be released. The device is reset when there is an interruption during the 18-bit time period. At the end of the debounce cycle, KO Outputs are switched off and two scan cycles begins. When KI or C Input senses a low level output, a Latch-Enable Signal is fed to the System (C-Input) or Command (KI-Input) Latches. After latching a system number, the device will generate the last command (i.e. all command bits logic 1) in the selected system for as long as the key is pressed. Latching of a command number causes the chip to generate this command together with the system number stored in the system latch. By releasing the key, the device will be reset if no data is to be transmitted at the time. The complete code frame is transmitted even if the key is released during code transmission.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 b). Single System Mode (SMS=High) In the Single System Mode, the KI-Sense Inputs are also pulled High by the p-channel pull-up transistors, as in the Combined System Mode. The C-Sense Inputs, however, are disabled by switching off their pull-high transistors. A system code is provided by a wired connection between the C-KO Matrix. The debounce cycle can ONLY be started by any legal key operation in the KI-KO Matrix. Once the key contact has been established for 18-bit time without any interruption, the Oscillator-Enable Signal is latched and the key may be released. Any interruption during the 18- bit time period resets the internal action. At the end of the debounce cycle, the pull-up transistors in the KI-Lines are then switched off and the pull-up transistors in the C-lines are turned ON for the first scan cycle. The wired connection in the C-matrix matrix is then translated into a system number and stored in the system latch. At the end of the first scan cycle, 1) the C-Input pull- up transistors are switched off and the inputs are again disabled, 2) KI-Sense Input pull-up transistors are turned on. The command number is generated by the second scan cycle. This command number is then latched and transmitted together with the system number. 5.KEY RELEASE DETECTION An additional control bit is complemented after key release. This additional control bit tells the decoder that the next code is a new command. This feature is important in cases where more digits are needed to be inputted (i.e. Teletext channel numbers or Viewdata pages). The extra control bit will only be complemented after the completion of at least one code transmission. The scan cycles are repeated before every code transmission; thus, even with the Take Over of key operation during the code transmission, the correct system and command numbers are generated. 6.RESETTING THE DEVICE The device will immediately reset under the following conditions: 1). A key is released during the debounce time 2). A key is released between two codes 3). During Matrix Scanning a). A key is released while one of the drivers outputs is in the low ohmic state (Logic 0) b). A key is released before that key has been detected. c). There is no wired connection in the C-KO Matrix when SMS is in High State.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 7.OSCILLATOR The OSC is a 1-pin oscillator input/output terminal. The oscillator is constructed by connecting in series a ceramic resonator like TOKO CRK429. 8. TEST MODE When T1,T2 and OSC Pins are in HIGH State, the circuit initializes. All internal nodes except for the LATCH are defined. The latch is defined when a scan cycle starts by pulling down a KI or a C Input while the oscillator is active. If the debounce cycle has been completed, then the scan cycle can be accomplished 3x23 times faster by setting the T1 to HIGH. If the scan cycle has been completed, the Latch contents can be read 3x27 times faster by setting t h eT 2t oH I G H .

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 SC3010 COMMAND MATRIX DATA CODE The Command Matrix Data Code is given in the table below: KI-Line KO-Line Command Bits No. 0 1 2 34 56 70 123 45 6 7 54 3 2 10 0 • • 000000 1 • • 000001 2 • • 000010 3 • • 000011 4 • • 000100 5 • • 000101 6 • • 000110 7 • • 000111 8 • • 001000 9 • • 001001 10 • • 001010 11 • • 001011 12 • • 001100 13 • • 001101 14 • • 001110 15 • • 001111 16 • • 010000 17 • • 010001 18 • • 010010 19 • • 010011 20 • • 010100 21 • • 010101 22 • • 010110 23 • • 010111 24 • • 011000 25 • • 011001 26 • • 011010 27 • • 011011 28 • • 011100 29 • • 011101 30 • • 011110 31 • • 011111 (to be continued)

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 (continued) KI-Line KO-Line Command Bits No. 0 1 2 34 56 70 123 45 6 7 54 3 2 10 32 • • 100000 33 • • 100001 34 • • 100010 35 • • 100011 36 • • 100100 37 • • 100101 38 • • 100110 39 • • 100111 40 • • 101000 41 • • 101001 42 • • 101010 43 • • 101011 44 • • 101100 45 • • 101101 46 • • 101110 47 • • 101111 48 • • 110000 49 • • 110001 50 • • 110010 51 • • 110011 52 • • 110100 53 • • 110101 54 • • 110110 55 • • 110111 56 • • 111000 57 • • 111001 58 • • 111010 59 • • 111011 60 • • 111100 61 • • 111101 62 • • 111110 63 • • 111111

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 SC3010 SYSTEM MATRIX DATA CODE The System Matrix Data Code for K-KO Lines are given in the table below: System No. C-Line KO-Line System Bits 0 1 2 3 0 1 2 3 4 5 6 7 4 3 2 1 0 0 • • 00000 1 • • 00001 2 • • 00010 3 • • 00011 4 • • 00100 5 • • 00101 6 • • 00110 7 • • 00111 8 • • 01000 9 • • 01001 10 • • 01010 11 • • 01011 12 • • 01100 13 • • 01101 14 • • 01110 15 • • 01111 16 • • 10000 17 • • 10001 18 • • 10010 19 • • 10011 20 • • 10100 21 • • 10101 22 • • 10110 23 • • 10111 24 • • 11000 25 • • 11001 26 • • 11010 27 • • 11011 28 • • 11100 29 • • 11101 30 • • 11110 31 • • 11111

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 APPLICATION CIRCUIT 1213 10111617 915 87 2 20 19 18 SC3010 Resonator Vss VDD VDD 270/Ga1 1/Ga1 IR LED VDD KO 0 KO 1 D OUT KI KI6 KI5 KI4 KI3 KI2 KI1 KI0 KO 2 KO 3 KO 4 KO 5 KO 6 KO 7 MD OUT SMS T1 T2 OSC 47/Gad F NOTE: There is a connection between the C0~C3 Lines and KO0~KO7 Lines if SMS is tied to VDD.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 CHIP TOPOGRAPHY 25 24 23 22 21 20 19 18 11109876543 /G3 size: 1.71 x 1.69 mm2 /G3 PAD COORDINATES (Unit:µm) No. Symbol X Y No. Symbol X Y 1 P1 -674.50 -407.50 15 P15 693.50 -49.00 2 P2 -674.50 -554.00 16 P16 693.50 91.00 3 P3 -674.50 -704.00 17 P17 693.50 231.00 4 P4 -450.50 -704.00 18 P18 537.00 680.50 5 P5 -309.75 -704.25 19 P19 386.75 680.50 6 P6 -146.50 -704.25 20 P20 246.75 680.50 7 P7 -18.75 -704.25 21 P21 97.25 680.50 8 P8 221.75 -704.25 22 P22 -42.75 680.50 9 P9 400.25 -704.25 23 P23 -192.25 680.50 10 P10 539.25 -704.25 24 P24 -332.00 680.50 11 P11 679.00 -704.25 25 P25 -481.50 680.50 12 P12 693.50 -468.75 26 P26 -674.50 614.50 13 P13 693.50 -329.00 27 P27 -674.50 449.00 14 P14 693.50 -189.00 28 P28 -674.50 267.375 Note: The original point of the coordinate is the die center.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 PCB WIRE LAYOUT SCHEMATIC: Transmitting tube output ground line The transmitting tube ground line and IC ground line should layout separated or overstriking ground line. The above IC only use to hint, not to specified. Note:/G2d6 * In wire layout, the power filter capacitor should near to IC. * In wire layout, should avoid power line and ground line too long. * Recommended infrared transmit unit and IC ground line should layout separated, or overstriking lines. * The emitter of triode connect 1 /Ga1 resistor at least. * Recommended triode use 9014.

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 PACKAGE OUTLINE DIP-28-600-2.54 UNIT: mm 13.8 /G66 0.25 2.54 0.5MIN 4.96MAX3.00MIN 15.24(600) 0.25 /G66 0.05 15 degree 0.46/G66 0.08 37.34/G66 0.3 1.52/G66 0.5 2.16MAX SOP-28-375-1.27 UNIT: mm 10.2 /G66 0.4 7.6 /G66 0.3 9.525(375)

2.8 MAX

17.75/G66 0.25 16.51 1.27 0.45/G66 0.1 0.15/G66 0.05 /G3

/G3 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD /G3 Rev: 2.1 2002-02-28/G3 Attach

Revision History

2001.11.07 2.0 2002.02.28 2.1 Modify the “Absolute maximum rating “ Modify the “Application circuit “ Add the “PCB wire layout schematic” Modify the “package outline” /G3