SAB2793B Datasheet PDF & Specifications

Manufacturer	Series	Package	Documents	Available	Select specification
List of Unclassifed Man...	-	-	1	PDF HTML	Viewing

SAB2797B ETC1

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 30

Technical content

“ey ‘ny, Advanced Flo Disk Formatter/ Control ler Family . modate ingle and double-density formats Features 5AB 27998 |SAB27978 ° tm 3740 single density (FM) Ny Single density (FM) [x | x IBM System 34 double density (MFM) , [x | @ Automatic seek with verify Double density (MFM) x x @ Multiple sector read/write True data bus x © TTL-compatible @ Programmable contro! Side select output [| x Selectable track-to-track access Internal CLK divide Head load timing © Software-compatible with the SAB 179X floppy @ Improved On-chip PLL data separator disk formatter/controlier family © On-chip write precompensation logic © Full functional- and pin-compatible @ Single +5V supply to the SAB 2793A/2797A Soft sector format compatibility Pin Configuration Logic Symbol wed abwr tee re td 2how | ar es ousce pros —sr weds nbiet ‘OOH \\, one shot GNo Cj apc = DN ase ‘The SAB 2793B/2797B are floppy disk controllers in performance phase-lock-loop data separator as N-channel MOS LS! technology designed to inter- well as write precompensation logic. face with SAB 8080/8085/805 1/8086/8088/80186/ When operating in double density mode, write. 80188/80286 family processors. Its flexibility and precompensation is automatically engaged to a ease of use makes it an ideal floppy disk interface value programmed via an external potentiometer. between conventional floppy disks andall computer An on-chip VCO and phase comparator allows systems. Software-compatible with its predecessor, adjustable frequency range for 51/4 "8" floppy the SAB 179X, the device also contains a high- disk and microfloppy disk interface. 1.87 Siemens Aktiengesellschaft 39

Pin Definitions and Functions input () Symbol Output (0) | Function ENP ENABLE PRECOMP Allogic high on this input enables write precompensation to be performed on the write data output WE 2 WRITE ENABLE A logic low on this input gates data on the DAL into the selected register when CS is low cs CHIPSELECT Alogic low on this input selects the chip and enables computer communication with the device RE READ ENABLE Alogic low on this input controls the placement of data froma selected register on the DAL when CS is low A0,A1 REGISTER SELECT LINES These inputs select the register to receive/transfer data on the DAL lines under RE and WE control: CS Al AO RE WE @ @ 0 Status register Command register © 0 1 Track register Track register © 1 0 Sector register Sector register ® 1 1 Dataregister Data register DAL to 7-14 ie) DATA ACCESS LINES DAL? 8.bit bidirectional bus used for transfer of commands, status and data STEP STEP The step output contains a pulse for each step DIRC DIRECTION Direction output is active high when stepping in, active low when stepping out 58 "7 5%", 8” SELECT This input selects the internal VCO frequency for use with 5%" drives or 8” drives RPW READ PULSE WIDTH An external potentiometer tied to this input controls the phase comparator within the data separator wR MASTER RESET A logic low (50 us min.) on this input resets the device and loads hex 03 into the command register. The “not ready bit” (status bit 7) is reset during MR active. When MR is brought toa logic high a restore command is executed, regardless of the state of the ready signal from the drive. Also hex 01 is, loaded into sector register TEST 22 TEST A logic low on this input allows adjustment of external resistors by enabling internal signals to appear on selected pins Siemens Aktiengeselischaft 40

a Pin Definitions and Functions (cont'd) Input (I) ‘Symbol Output (0) | Function PUMP 23 PUMP High-impedance output signal which is forced high or low to increase/decrease the VCO frequency cLK CLOCK This input requires a free-running, 50% duty cycle square-wave clock for internal timing reference, 2 MHz +1% for 8” drives, 1. MHz + 1% for minifloppies ENMF ENABLE MINIFLOPPY (SAB 27938) A logic low on this input enables an internal divide by 2 of the master clock. This allows both 5%" and 8” drive operation with a single 2 MHz clock. For a 1 MHz clock on pin 24, this ling must be left open or tied to a logic 1 SSO ‘SIDE SELECT OUTPUT (SAB 2797B) The logic level of the side select output is directly controlled by the U flag in type I! or lll commands. When U = 1, SSOis set toa logic 1. When U = 0, SSO is set to a logic 0. The SSO is compared with the side information in the sector ID field. Ifthey do not correspond, status bit 4 (RNF) is set. The side select output is only updated at the beginning of a type Il or Ill com- mand. It is forced to a logic 0 upon a master reset condition vco VOLTAGE CONTROLLED OSCILLATOR ‘An external capacitor tied to this pin adjusts the VCO center frequency RAWREAD 27 RAWREAD The data input signal directly from the drive. This input shall be a negative pulse for each recorded flux transition HLD 28 HEAD LOAD The HLD output controls the loading of the read/write head against the media Teas TRACK GREATER THAN 43 This output informs the drive that the read/write headis positioned between tracks 44 and 76, This output is valid only during read and write commands WG 30 WRITE GATE This output is made valid before writing is to be performed on the diskette WD WRITE DATA MEM or FM output pulse per flux transition. WD contains the unique address marks as well as data and clock in both FM and MFM formats READY READY This input indicates disk readiness and is sampled for a logic high before read or write commands are performed. If ready is low the read or write operation is not performed and an interrupt is generated. Type | operations are performed regardless of the state of ready. The ready input appears in inverted format as status register bit 7 Siemens Aktiengesellschaft 4

Pin Definitions and Functions (cont'd) input (i) ‘Symbol Output (0) | Function wew WRITE PRECOMP WIDTH Anexternal potentiometer tied to his input controls the amount of delay in write precompensation mode ‘TROO TRACK 00 This input informs the SAB 27938/27978 that the read/write head is positioned over track 00 3 35 INDEX PULSE This input informs the SAB 2793B/2797B when the index hole is encountered on the diskette WPRT WRITE PROTECT This input is sampled whenever a write command is received. Allogic low terminates the command and sets the write Protect status bit DDEN 37 DOUBLE DENSITY This input pin selects either single or double density operation. When DDEN = 0, double density is selected. When DDEN = 1, single density is selected Dra 38 DATA REQUEST This output indicates that the data register (DR) contains assembled data in read operations, or the DR is empty in write operations. This signal is reset when serviced by the computer through reading or loading the data register INTRO 39 INTERRUPT REQUEST This output is set at the completion of any command and is reset when the status register is read or the command register is written to i HLT HEAD LOAD TIMING When a logic high is found on the HLT input the head is. assumed to be engaged. It is typically derived from a single shot triggered by HLD vec [2 [= [rower surPyvsv1 Siemens Aktiengesellschaft 42

a Block Diagram (oat) ata Conmand sector track Stans fester Register Register L Register i Regier tte | | sd a ow snitt {te bse ES | ee i ew wPw two [co oo W6. NTR 1643 WRT FR i B Ta fig READY rn ra ee a rr a Centet 230818) Contr RHF Ss0, cx fT} OER rea Siemens Aktiengesellschaft 43

‘The SAB 27938/27978 are N-channel MOS LSI made as close as possible with the computer devices performing the functions of a Floppy Disk _interface, instruction set, and I/O registers being Formatter/Controlier in a single-chip implemen- _identical. Also, head load control is identical in tation. The SAB 27938/27978 is IBM 3740 com- each case, the actual pin assignments vary by only patible in single density mode (FM) and System 34 _a few pins from any one to another. compatible in double density mode (MFM). The The processor interface consists of an 8-bit bi- SAB 27938/27978 contains all the features of its _directional bus for data, status, and control word predecessor, the SAB 179X, plus a high-perfor transfers. The SAB 2793B/2797Bis set up to operate mance phase-lock-loop data separator as well as. ona multiplexed bus with other bus-oriented write precompensation logic. In double density devices. The SAB 27938/27978 is TTL compatible mode, write precompensation is automatically onall inputs and outputs. The outputs will drive one ‘engaged to a value programmed via an external TTL toad or three LS loads. potentiometer. In order to maintain compatibility, The SAB 27978 has a side select output to control the SAB 179X and SAB 2793B/2797B designs were —_ double sided drives. Organization The Floppy Disk Formatter block diagram is. Command Register (CR) - This 8-bit register holds illustrated on page 5. The primary sections include _ the command presently being executed. This the parallel processor interface and the Floppy Disk register should not be loaded when the device is interface. busy unless the new command is a Force Interrupt Data Shift Register (DSR) — This 8-bit register command. The command register can be loaded assembles serial data from the Read Data input from the DAL, but not read onto the DAL. (RAW READ) during read operations and transfers Status Register (STR) - This 8-bit register holds serial data to the Write Data output during write device status information. The meaning of the operations. status bits depends on the type of command Data Register (DR) - This 8-bit register is used as a__ previously executed. This register can be read onto holding register during disk read and write the DAL, but not loaded from the DAL. Seer vee ts in disk read operations the assembled Cac Logic This logicis used to checkor to generate lata byte is transferred in parallel from the Data the 16-bit Gycte Recundancy Check (CRC), the Shift Register to the Data Register. In disk write rolynomial fe: Gx) = x°© 4 x? xe 1 operations information is transferred in parallel oh vere fu Xe Ni ro +x th the from the Data Register to the Data ShiftRegister. 45 ot mark andamto the CRC characte The Cac When executing the Seek command the Data teri ft p tothe ¢ to dat bein ‘nif " Register holds the address of the desired track Ce Ee eae ee Prior to data boing shifte position. This register is loaded from the DAL and rough the circuit. gated onto the DAL under processor control. Arithmetic/Logic Unit (ALU) — The ALU is a serial ‘Track Register (TR) — This 8-bit register holds the COMparator, incrementer, and decrementer and is track number of the current Read/Write head used for register modification and comparisons position. Itis incremented by one everytime the __With the disk recorded ID field. head is stepped in (towards track 76) and decre- Timing and Control — All computer and Floppy Disk mented by one when the head is stepped out interface controls are generated through this logic. (towards track 00). The contents of the register are The internal device timing is generated from an compared with the recorded track number in the ID external crystal clock. field during disk read, write and verify operations. ‘The Track Register can be loaded from ortransferred | AM Detector ~ The address mark detector detects to the DAL. This register should not be loaded when _'D, data and index address marks during read and the device is busy. write operations. Sector Register (SR) — This 8-bit register holds the Write Precompensation — Enables write pre- address of the desired sector position. The contents compensation to be performed on the Write Data of the register are compared with the recorded output. sector number in the ID field during disk read or Data Separator — A high-performance phase-lock- write operations. The Sector Register contents can _loop data separator with on-chip VCO and phase be loaded from or transferredtothe DAL. This regis- comparator allows adjustable frequency range for ter should not be loaded when the device is busy. 51" or 8” Floppy Disk interfacing Siemens Aktiengesellschaft 44

a Processor Interface The interface to the processor is accomplished In disk write operations the Data Request is acti- through the eight Data Access Lines (DAL) and vated when the Data Register transfers its contents associated control signals. The DAL are used to. to the Data Shift Register, and requires a new data transfer data, status, and control words out of or byte. Itis reset when the Data Register is loaded with into the SAB 2793B/2797B. The DAL are three-state new data by the processor. If new data is not buffers that are enabled as output drivers when loaded at the time the next serial byte is required by Chip Select (CS) and Read Enable (RE) are active _the Floppy Disk, a byte of zeros is written on the (low logic state) or act as input receivers when CS: diskette and the Lost Data bit is set in the ‘Status and Write Enable (WE) are active. Register. When data transfer with the Floppy Disk Controller Upon completion of every command an INTRO is: is required by the host processor, the: deviceaddress generated. INTRQ is reset either by reading the iedevoded and CS is made low. The address bits A1 Status Register or by loading the Command Register ‘and AO, combined with the signals RE duringaread with a new command. In addition, INTRQ is gen- ‘operation or WE during a write operation, are erated if a Force Interrupt command condition interpreted as selector for the following registers: is met. The SAB 27938/2797B has two modes of operation ai [ao [READ [WRITE depending on the state of DDEN (Pin 37). When DDEN = 1, Single Density (FM) is selected. When 3 Status Register Command Register GEN = 0, Double Density (MFM) is selected. In rack Register _| Track Register : ‘ 4 eer eaiemor | Sector Register either case, the CLK input (Pin 24) is set at 2 MHz 4 tor Rea! for 8" drives or at 1 MHz for 5%” drives.

1 Data Register _| Data Register ‘i

On the SAB 27938 the ENMF input (Pin 25) can be used for controlling both, 5'/"" and 8” drives: During direct memory access (DMA) types of data with a single 2 MHz clock. When ENMF = 0, an transfers between the Data Register of the internal divide by 2 of the CLK is performed. When SAB 27938/2797B and the processor, the Data ENMF = 1-no divide takes place. This allows the Request (DRO) output is used for data transfer tine of a2 MHz clock for both, 817" and 8” control. we. signal also appears as status bit1 configurations. during read and write operations. The internal VCO fre ncy must also Jet to the Indisk read operations the Data Requestis activated proper value. The Seatnout (Pin This oe oe alot (set high) when an assembled serial input byte data separator operation by internally dividing the is transferred in parallel to the Data Register. This read clock. When 5/8 = 0, 5%" drive data separation bit is cleared when the Data Register is read bythe ig selected; when 6/8 = 1, 8” drive data separation processor. If the Data Register is read after one or _ig selected. more characters have been lost by having trans- ferred new data into the register prior to processor r fered new detainto terete: par occa _coceaa) TENWE 28) [88(77"_ Deve The read operation continues until the end of sector 2 MHz 8" is reached. ‘2 MHz 5M"

1 MHz Sie"

All other conditions are invalid. Siemens Aktiengesellschaft 45

The SAB 27938/2797B is software-compatible with The number of sectors per track as far as the the SAB 179X series of Floppy Disk Controllers. SAB 27938/27978 is concerned can vary between 1 ‘Commands, status, and data transfers are per- and 255 sectors. The number of tracks as far as the formed in the same way. Software generated forthe _ SAB 27938/27978 is concerned is from 0 to 255 ‘SAB 179X can be transferred to a SAB 2793B/27978 tracks. For IBM 3740 compatibility, sector lengths system without modification. are 128 byte with 26 sectors per track. For System 34 In addition to the SAB 179X, the SAB 27938/27978 compatibility (MFM), sector lengths are 256 byte/ contains an internal data separator and write sector with 26 sectors/track; or lengths of 1024 precompensation circuit. The TEST (Pin 22) ine is ___byte/sector with 8 sectors/track used to adjust both, data separator and precompen- sation. When TEST = 0, the WD (Pin 31) line is. General Disk Write Operation eee nate chet Adjacent ct the WPW \\When writing isto take place on the diskette the {[Pin33) line con then be accomplished. A second Write Gate (WG) output is activated, allowing single shot tracks the precomp setting at approxi. cUFFeNttO flow into the Read/Write head. As a mately 3:1 to ensure adequate Write Data pulse precaution to erroneous writing the first data byte widths to meet drive specifications must be loaded into the Data Register in response Similarly, data separation is also adjusted with toa Data Request from the SAB27938/2797B TEST ~ 0. The 1G43 (Pin 29} line is internally before the Write Gate signal can be activated. connected to the output of the read data single shot, Writing is inhibited when the Write Protect input is which is adjusted via the RPW (Pin 18) line. The logic low, in which case any write commands DIRC (Pin 16) line contains the read clock eutput immediately terminated, an interrupt is generated (500 kHz for 8” drives). The VCO trimming capacitor 2nd the Write Protect status bit is set. (Pin 26) is adjusted to center frequency. For write operations, the SAB 2783B/2797B Internal timing signals are used to generate pulses Provides Write Gate (Pin 30) and Write Data (Pin 31) during the adjustment mode sothat these adjust. u‘Puts. Write Data consists of a series of pulses set ments can be made while the device is in operation, ‘0 @ width approximately three times greater than The TEST line also contains a pull-up resistor, so the Precomp adjustment, Write Data provides the \\ adjustments can be performed simply by grounding U4UE address marks in both formats, | the TEST pin, overriding the pull-up. The TEST pin. cannot be used to disable stepping rates during way ‘operation as its function is quite different from the Whenever a read or write command (Type Il or Il) is SAB 179X. received the SAB 2793B/2797B samples the Ready Other pins on the device also include pull-up input. If this input is logic low the command is not resistors and may be left open to satisfy alogic1 executed and an interrupt is generated. All Type | condition. These are: ENP, 5/8, ENMF, WPRT, ‘commands are performed regardless of the state of ‘DDEN, HLT, TEST, and MR. the Ready input. Also, whenever a Type Il or Ill ‘command is received, the TG43 signal output is General Disk Read Operation updated. TG43 may be tied to ENP to enable write Sector lengths of 128, 256, 512 or 1024 are obtain. __Precompensation on tracks 4476, able either in FM or MFM formats. For FM, DDEN should be placed to logic 1. For MFM formats, DDEN should be placed to a logic 0. Sector lengths are determined at format time by the fourth byte in the ID field. Sector Length Table* Sector Length Number of Bytes Field (hex) in Sector (decimal) 00 128 01 256 02 512 03 1024 * SAB 2797B may vary ~ see command summary. Siemens Aktiengesellschatt 46

Write Precompensation VCO Operation When operating in double density mode (ODEN = After adjustments have been made, the TEST pin 0), the SAB 27938/27978 has the capability of is returned to a logic 1 and the device is ready for providing a user-defined precompensation value __ operation. Adjustments may be made in-circuit for Write Data. An external potentiometer (10k) tied — since ‘the DIRC and TG43 lines may toggle without to the WPW signal (Pin 33) allows a setting of 100to affecting the drive. 300 ns from nominal. The PUMP output (Pin 23) consists of positive and Setting the write precomp value is accomplished by negative pulses. Their duration is equivalent to forcing the TEST line (Pin 22) to a logic 0. Astream _ the phase difference of incoming Data versus VCO bf pulses can then be seen on the Write Data (Pin31) frequency. This signal is internally connected to the line. Adjust the WPW Potentiometer forthe desired VCO input, but a filter is needed to connect these pulse width. This adjustment may be performed in-_ pulses to a slow moving OC voltage. evcuit since the Write Gate (Pin 30) is inactive while The internal phase-detector is unsymmetrical for a TEST = 0. random distribution of data pulses by a factor of two, in favor of a PUMP UP condition. Therefore it is Data Separation desirable to have a PUMP DOWN twice as respon- . 0 sive to prevent run-away during a lock attempt. The SAB 2793B/27978 can operate witheither ana first-order lag-lead filter can be used at the PUMP external data separator or its own internal recovery ‘ ao eae ee etonatine TEST line (Pin 22) in” OtbuE(Pin 23). This fit controls i as conjunction with MR (Pin 19) will select internal or neous response of the VCO to bit-shifted data (jitter) ‘external mode. as well as response to normal frequency shift i.e. To program the SAB 27938/27978 for external VCO, the lock-up time. A balance must be accomplished a MR pulse must be applied while TEST = 0. A clock between the two conditions to inhibit overrespon- equivalent to eight times the data rate (e.g. 4.0 MHz peeaaed to jitter and to baer extremely wige Hep eeuble density) ie applied to the VCO input 0ck-up response leading fo PLNEE Ta auiny The (Pin 26), The feedback reference voltages available Net 8 fects these two reactions in mutually Gnthe PUMP output Pin 23) for external integration OPPOSie directions. to control the VCO. TEST is returned to a logic 1 for ogmal operation. Nt Ta lied. The following Fiter Circuit is recommended For internal VCO operation, the TEST line mustbe _'0°8” FM/MEM: high during the MR pulse, then set to a logic 0 for the adjustment procedure. 50k Potentiometer tied to the RPW input (Pin 18) is used to set the internal Read Data pulse for proper PUMP. phasing. With a scope on Pin 29 (TG43), adjust the (Pin 23) RPW pulse for 1/8 of the data rate (250 ns for 8” OA pF Double Density). An external, variable capacitor of a typically 5t0 60 pFis tied to the VCO input {Pin 26) for adjusting center frequency. With a frequency counter on Pin 16 (DIRC) adjust the trimmer cap to yield the appropriate data rate (500 kHz for 8” Double Density). The DDEN line must be low while []rKa ZN ANN the 5/8 line is held high or the adjustment times above will be doubled. Since 51” Drives operate at exactly one-half the data rate (250 Kbyte/s) the above capacitor should be doubled to 0.2 or 0.22 uF. Siemens Aktiengeselischaft 47

Commands for SAB 27938 Commands for SAB 27978 Bits Bits Type Command 7, 6 5 43 2 1 0 765 43210

1 Restore 0 0 0 0 h Vn ft 000 0 h VA fo

i] Seek 00 0 1 Ah Vf fo 00 0 1 h VG fo

1 Step 0 0 1 Th Vin wm }0 0 1 Th VG fo

1 Step-in Oo 10 Th Vi ff o 10 Th V fy fo

t Step-out oO 1 1 Th Von te o 14 Th Von fo i Read sector 100ms ECoOl]100mtEUO i Write Sector 10 1 mS EC ali o01mL EU a» ul Read Address 1°10 00 € 0 0 1 1° 0 00 € UO ul Read Track 1 1° 1 0 6 E—E 0 0 1 1°10 0 € UO Ml Write Track 1711 0600/1114 10E6EU0 Wv Force Interrupt 11 01k b ih ib 110 7 bb kk hh be Flag Summary Command Description Type f 1, fo~ Stepping Motor Rate ‘See page 13 for details

1 V_ = Track Number Verify Flag V_ =0,No verify

V_ = 1, Verity on destination track i h = Head Load Flag fh = 0, Unload head at beginning h_ = 1, Load head at beginning

1 T= Track Update Flag T = 0,No update

T = 1,Updete track register | 8c a) = Data Address Mark a> = 0, FB (DAM) a = 1, F8 (deleted DAM) " C= Side Compare Flag C = 0, Disable side compare | C = 1,Enable side compare | N&ill —|U_ = Update SSO U_ = 0, Update SSO t0 0 U_ = 1, Update SSO to 1 N&il | & = 15ms Delay E = 0,No 15ms delay E = 1,15ms delay (30 ms for 1 MHzclock) W S = Side Compare Flag S = 0, Compare for side 0 S = 1, Compare for side 1 i L_ = Sector Length Flag L_ = 1 (implicit) for SAB 27938 LSB’s Sector Length in ID Field 00 o1 10 W 2565121024 «128 W m = Multiple Record Flag m = 0, Single record m = 1,Multiple records v k= Interrupt Conditions Flags W=1 Interrupt on Not Ready to Ready Transition 11 =1; Interrupt on Ready to Not Ready Transition I2=1: Interrupt on Next Index Pulse 1354: Immediate Interrupt Requires a Reset * . [3-10 = 0: Terminate with No interrupt (INTRQ) * See Type IV command description for further information. ‘Siemens Aktiengeselischaft 48

a Status Register Summary Bit] All Type! Read Read Read Write Write Commands _| Address Sector Track Sector Track S7|NOTREADY |NOTREADY |NOTREADY [NOTREADY |NOTREADY | NOT READY 6 | WRITE 0 ° 0 WRITE WRITE PROTECT PROTECT PROTECT $5| HEAD LOADED | 0 RECORD TYPE |0 0 0 $4] SEEKERROR | RNF RNF 0 RNF 0 $3]CRCERROR |CRCERROR |CRCERROR {0 CRCERROR | 0 '$2| TRACK 00 LOSTDATA |LOSTDATA |LOSTDATA |LOSTDATA | LOST DATA $1 INDEX ora DRO Ra DRO RQ so] BUSY BUSY BUSY BUSY BUSY BUSY Status for Type | Commands Bit[Name___[ Meaning ‘S7| NOTREADY __| This bit, when set, indicates that the drive is not ready. When reset, itindicates that the drive is ready. This bit is an inverted copy of the Ready input and logically ORed with wR. 86 WRITE When set, indicates that Write Protect in activated. This bits an inverted copy of PROTECT WPRT input. 35] HEAD LOADED | When set. it indicates that the head is loaded and engaged. This bit is a logical AND of HLD and HLT signals. ‘S4]SEEKERROR | When set. the desired track was not verified. This bit is reset to 0 when updated. 83] CRCERROR _ | CRC encountered in ID field. S2[ TRACK 00 ‘When set, indicates that Read/Write head is positioned to Track 00. This bit is an inverted copy of the TROO input. $1] INDEX ‘When set, indicates that index markis detected from drive. This bit is an inverted copy of the IP input. so| BUSY ‘When set, command is in progress. When reset, no command is in progress. Status for Type Il and tlt Commands S7|NOTREADY | This bit, when set, indicates that the drive is not ready. When reset, it indicates thatthe drive is ready. This bit is an inverted copy of the Ready input and ORed with MR. The Type il and ill Commands will not execute unless the drive is ready. S6| WRITE For Read Record: not used. For Read Track: not used. On any Write: It indicates @ PROTECT Write Protect. This bit is reset, when updated. $5] RECORD TYPE | For Read Record: It indicates the record-type code from data field address mark. 1 = Deleted Data Mark. 0 = Data Mark. For any Write: forced to a zero. 4] RECORD NOT | When set, it indicates that the desired track, sector, or side were not found. This bit is FOUND (RNF)_| reset when updated. S3}CRCERROR _ | IfSdisset, anerror is found in one or more ID fields; otherwise it indicates error in data field. This bit is reset when updated. S2]LOSTDATA | Whenset, it indicates that the computer did not respond to DRQ in one byte time. This bit is reset to zero when updated. 1] DATA This bit is a copyof the DRQ output. When set, it indicates that the DR is full on a read REQUEST ‘operation or the DR is empty on a write operation. This bit is reset to zero when updated. so[Busy When set, command is under execution. When reset, no commands under execution. Siemens Aktiengesellschaft 49

Summary of Adjustment Procedures Write Precompensation 1) Set TEST (Pin 22) to a logic high. 2) Strobe MR (Pin 19). 3) Set TEST (Pin 22) to a logic low. 4) Observe pulse width on WD (Pin 31). 5) Adjust WPW (Pin 33) for desired pulse width (Precomp Value). 6) Set TEST (Pin 22) to a logic high. Data Separator 1) Set TEST (Pin 22) to a logic high. 2) Strobe MAR (Pin 19). Ensure that 5/8, and ODEN are set properly. 3) Set TEST (Pin 22) to a logic low, 4) Observe pulse width on TG43 (Pin 29). 5) Adjust RPW (Pin 18) for 1/8 of the read clock (250 ns for 8" DD, 500 ns for 5'/«"’ DD, etc.). 6) Observe frequency on DIRC (Pin 16). 7) Adjust variable capacitor on VCO pin for data rate (500 kHz for 8” DD, 250 kHz for 51/4” DD, etc.), 8) Set TEST (Pin 22) to a logic high. NOTE: To maintain internal VCO operation, insure that TEST = 1 whenever a master reset pulse is applied. Status Register Upon receipt of any command, except the Force The format of the Status Register is shown below: Interrupt command, the Busy Status bit is set and SSS the rest of the status bits is updated or cleared for (BITS) the new command. Ifthe Force Interruptcommand —> 6] 8 [4 |3]2]7]0 is received while a current command is under execution, the Busy status bitis reset, andtherestot _S7 | $6 | 5 | sa | ss | sz | st so the status bits is left unchanged. If the Force Interrupt command is received while there is no Status varies according to the type of command current command under execution, the Busy Status &ecuted as shown on page 11. bitis reset and the rest of the status bits is updated or cleared as after a Type | command. - - The user can optionally read the Status Register Because of internal sync cycles, certain time delays through program control or by using the DRQ line ust be observed when operating under pro- with DMA or interrupt methods. When the Data grammed 1/0. They are: Register is read, the DRQ bit in the Status Register = = and the DRQ line are automatically reset. Awrite to Operation Next Operation | Delay Req'd. the Data Register also causes the reset of both DROs. [ FM | MEM he Busy bitin the Status may be monitored bya Write to Read Busy Bit | 12us | 6us user program to mmand is C .d Reg. | (Status Bi¢ 0} ‘complete, in lieu of using the INTRO line. When ommend Reg. | Status BHO) using the INTRQ, a busy status check is not Write to [ReeaSats | 805 | 144s recommended because reading the Status Register Command Reg. | Bits 1-7 to determine the condition of Busy will reset the Write to Read from Diff. oO INTRO line. Any Register| Register Times double when clock = 1 MHz ‘Siemens Aktiengeselischaft 50

a Command Description ‘The SAB 27938/27978 will accept eleven com- command is completed, an interrupt is generated mands. Command words should only be loaded in and the Busy status bit is reset. The Status Register the Command Register when the Busy status bit is indicates whether the completed command en- off (Status bit 0). The only exception is the Force countered an error or was fault-free. For ease of Interrupt command. Whenever acommandis being _ discussion, commands are divided into four types. executed, the Busy status bit is set. When a Commands and types are summarized on page 10. Type | Commands ‘The Type | commands include the Restore, Seek, ‘operation begins at the end of the 15 millisecond Step, Step-In and Step-Out commands. Each of the setting time after the head is loaded against the Type | commands contains a rate field (ro, r:) which _ media. The track number from the first encountered determines the stepping motor rate. ID field is compared against the contents of the A2 us (MFM) or 4 \\1s (FM) pulse is provided as an Track Register. If the track numbers correspond and output to the drive. For every step pulse issued, the the ID field Cyclic Redundancy Check (CRC) is drive moves one track location in a direction correct, the verify operation is compiete and an determined by the Direction output. The chip steps INTRQ is generated with no errors. Ifthere is amatch the drive in the same direction it has been stepped _but not a valid CRC, the CRC Error status bit is set previously, unless the command changes direction. (Status bit 3), and the next encountered ID field is The Direction signal is active high when stepping in read from the disk for the verification operation. and lowwhen stepping out. The Direction signalhas The SAB 27938/27978 must find an ID field with been valid 12 us before the first stepping pulse is correct track number and correct CRC within 5 revo- generated. The rates can be applied to a Step- lutions of the media; otherwise the Seek Error is set Direction motor through the device interface, and an INTRA is generated. If V = 0, no verification is performed. The Head Load (HLD) output controls Stepping Rates the movement of the Read/Write head against the [ema] media. HLO is activated at the beginning of a Type | clk A MHz command if the h flag is set (h = 1), at the end of the mo |test=1 ‘| TeST=1 ‘Type | command if the Verify flag is set (V = 1), or o 3ms éms upon receipt of any Type Il or Ill command. Once 0 ems 12m. HLD is active it remains active until either a Type | 1 10ms 20ms command is received with h= 0 and V = 0, or if the 1 15ms 30 ms SAB 27938/27978 is in an idle state (non-busy) and 15 index pulses have occurred. After the last directional step, additional 15 milli- Bee A eestor the nead seconds of head settling time are generated if the ‘engage time. Verify flag is set ve eo eae the that this When HLT= 1, the SAB 27938/27978 assumes the ‘ eisalso head is completely engaged. The head engage ‘a 15 ms head setting time if the E flag is set in any time is typically 30 to 100 ms depending on drive. Type ll or It command. The low to high transition on HLD is typically When a Seek, Step or Restore command is executed used to fire a single shot. The output of the single an optional verification of Read/Write head position shot is then used for HLT and supplied as an input can be performed by setting bit 2 (V = 1) in the to the SAB 2793B/2797B. command word to a logic 1. The verification Siemens Aktiengesellschaft 51

HLD | 30 to 100ms HLT from one-shot When both HLD and HLT are true, the SAB 27938/ Seek 27978 will read from or write to the media. The This command assumes that the Track Register “AND” of HLD and HLT appears as status bit 5 in contains the track number of the current position of Type I status. the Read/Write heed and the Data Register contains. the desired track number. The SAB 2793B/2797B Summary of the Type | commands: will update the Track Register and issue stepping ith = Qand V = 0, HLDis reset. a pulses in the appropriate direction until the contents Ifh= 1and V = 0, HUD is set at the beginning ofthe GF the Track Register are equal to the contents of the command and HLT is not sampled noristhere anata Register (the desired track location). A internal 15 ms delay. verification operation takes place if the V flag is on. Ith = Oand V = 1, HLD is set near the end of the The h bit allows the head to be loaded at the start of command, an internal 1 ms delay occurs, andthe the command. Aninterruptis generated atthe termi- SAB 2793B/2797B waits for HLT to be true. nation of the command. Note: When using multiple ifh = 1and V = 1, HLD is set at the beginning ofthe qrives, the Track Register must be updated for the | command. drive selected before seek commands are issued. | Near the end of the command, after all the steps have been issued, an internal 16 ms delay occurs Step and the SAB 2793B/2797B waits for HLT to occur. | For Type il and ill commands with € flag off, HLD is _/Pen receipt of this command, the SAB £7038) | made active and HLT is sampled until true. With € _2787B issues one stepping pulse to the disk drive sample he stepping motor direction is the same as in the flag on, HLD is made active, an internal 15 ms delay occurs and then HLT is sampled until true. previous Step command. After a delay determined by the r; ro field, a verification takes piace if the V flag is on. Ifthe T flag is on, the Track Register is updated, The h bit allows the head to be loaded at the start of, Restore (Seek Track 0) the command. An interrupt is generated at the Upon receipt of this command the Track 00 (TRO0) termination of the command: inputis sampled. If TROVis active low indicating the Gea, pin Read/Write heads positioned over track 0, the Track Register is loaded with zeros and an interrupt is Upon receipt of this command, the SAB 27938/ generated. If TRO0 is not active low, stepping pulses 27978 issues one stepping pulse towards track 76. ata rate specified by the ry rofield are issued until__ If the T flags on, the Track Register is incremented the TROO input is activated. At this time the Track by one. After a delay determined by the 1; fo field, a Register is loaded with zeros and an interrupt is verification takes place if the V flag is on. The h bit generated. If the TROO input does not go active low _ allows the head to be loaded at the start of the after 255 stepping pulses, the SAB 27938/2797B command. An interrupt is generated at the termi- terminates operation, interrupts and sets the Seek ation of the command. error status bit. A verification operation takes place if the V flag is set. The h bit allows the head to be -—«Step-Out loaded at the start of command. Note that the Upon receipt of this command, the SAB 2793B/ Restore command is always executed when MR. 2797B issues one stepping pulse towards track 0. If goes from an active to an inactive state. the T flag is on, the Track Register is decremented by Siemens Aktiengesellschaft 52

one. After a delay determined by the r; fo field, a Verification takes place if the V flag is on. The h bit allows the head to be loaded at the start of the command. An interrupt is generated at the termination of the command Type Il Commands The Type ll Commands are the Read Sector and The Type ll commands for the SAB 27938 also Write Sector commands. Prior to loading a Typell__contain Side Select Compare flags. When C = 0 ‘command into the Command Register the com- {bit 1) no side comparison is made. When C = 1, the puter must load the Sector Register with the desired _ LSB of the side number is read off the ID field ofthe pector number. Upon receipt of the Type llcom- disk and compared with the contents of the S flag mand, the Busy status bit is set. If the E flag is 1 (this (bit 3). If the S flag corresponds to the side number is the normal case) HLD is made active and HLT is. recorded in the ID field, the SAB 2793B/2797B sampled after a 15 ms delay. ifthe E flag is 0,the _ continues with the ID search. If a comparison is not head is loaded and HLT is sampled without a made within 5 index pulses, the interrupt line is 15 ms delay. made active and the Record-Not-Found status bit When an ID field is located on the disk, the is set. ‘SAB 27938/2797B compares the track number on _The Type ll and lil commands for the SAB 27978 the ID field with the Track Register. Ifthey do not _ contains a Side Select flag (bit 1). When U = 0, SSO match, the next encountered ID field is read anda is updated to 0. Similary, U = 1 updates SSO to 1. ‘comparison is again made. If there has been a The chip compares the SSO to the ID field. Ifthey do match, the Sector Number of the ID field is not correspond within 5 revolutions the interrupt compared with the Sector Register. If there is no line is made active and the RNF status bit is set. sector match, the next encountered ID field is read The SAB 2797B Read Sector and Write Sector com- off the disk and again compared. If the ID field CRC mands include an L flag. The L flag, in conjunction is correct, the data field is then located and will be with the Sector length byte of the ID Field, allows either written into, or read from depending upon the different byte lengths to be implemented in each command. The SAB 2793B/27978 must find an ID _ sector. For IBM compatibility, the L flag should be field with a track number, sector number, side set toa one. number, and CRC within 5 revolutions of the disk; otherwise, the Record-Not-Found status bit is set (Status bit 4) and the command is terminated with ead Sector an interrupt. Each of the Type Ilcommands contains Upon receipt of the Read Sector command, the head ‘an m flag which determines if multiple records is loaded, the Busy status bit set, and when an ID (sectors) are to be read or written, depending upon _ field is encountered that has the correct track the command. If m = 0, a single sector is read or number, correct sector number, correct side num- written and an interrupt is generated at the ber, and correct CRC, the data field is presented to termination of the command. If m = 1, multiple the computer. The Data Address Mark of the data records are read or written with the Sector Register _ field must be found within 30 byte in single density internally updated so that an address verification and 43 byte in double density after the last ID field can occur on the next record. The SAB 27938/ CRC byte; if not, the ID field search is repeated. 27978 will continue to read or write multiple records When the first character or byte of the data field has and update the Sector Register in numerical been shifted through the DSR, it is transferred to the ascending sequence until the Sector register DR, and DRQ is generated. When the next byte is exceeds the number of sectors on the track or until accumulated in the DSR, it is transferred to the DR the Force Interrupt command is loaded into the and another DRQ is generated. If the computer has Command Register, which terminates the command not read the previous contents of the DR before a and generates an interrupt. new character is transferred that character is lost For example: If the SAB 2793B/2797B is instructed and the Lost Data status bit is set. This sequence to read sector 27 and there are only 26 sectors on continues until the complete data field has been the track, the Sector Register exceeds the number input to the computer. If there is a CRC error at the available. The SAB 2793B/27978 will search for __end of the data field, the CRC Error status bit is disk revolutions, interrupt out, reset Busy, and set set, and the command is terminated (even if it is a the Record-Not-Found status bit. multiple sector command). Siemens Aktiengesellschaft 53

At the end of the read operation, the type of Data disk. At this time the Data Address Mark is written Address Mark encountered in the field is re- on the disk as determined by the as field of the corded in the Status Register (bit 5) as shown: ‘command as shown below: Status Bit a0 Data Address Mark (Bit 0)

7 Deleted Data Mark 1 Deleted Data Mark

Write Sector ‘The SAB 27938/27978 then writes the data field and Upon receipt of the Write Sector command, the _ generates DRQs to the computer. If the DRQ is not head is loaded (HLD active) and the Busy status bit serviced in time for continuous writing, the Lost is set. When an ID field is encountered that has the _Data status bits set and a byte of zeros is written on correct track number, correct sector number, correct the disk. The command is not terminated. After the side number, and correct CRC, a DRO is generated. last data byte has been written on the disk, the two- The SAB 2793B/2797B counts off 11 bytes in single byte CRC is computed internally and written on density and 22 bytes in double density fromthe CRC the disk followed by one byte of hex FE in FM or in field, and the Write Gate (WG) output is made active MFM. The WG output is then deactivated. For a ifthe DRQis serviced (i.e. the DR has been loaded by 2 MHz clock the INTRQ is set between 8 and 12 us the computer). lf DRO has not been serviced, the _ after the last CRC byte has been written. For partial commands terminated and the Lost Data status bit sector writing, the proper method is to write the data is set. If the ORO has been serviced, the WGis made _ and fill the balance with zeros. By letting the chip fill active and six bytes of zeros in single density and the zeros, errors may be masked by the Lost Data 12 bytes in double density are then written on the _status and improper CRC bytes. Types Ill Commands Read Address All gap, header, and data bytes are assembled and transferred to the Data Register. DRQs are Upon receipt of the Read Address command, the seated for each byte. The accumulation of bytes head is loaded and the Busy status bit is set. The ; is synchronized to each address mark encountered next encounterad ID fiald is then read from the An interrupt is generated at the termination of the disk, and the six data bytes of the ID field are mrmand. assembled ancl transferred to the DR. And ORQis this command has several characteristics which genertedtor each byt. ThesixbytesofthelD eld Tats eutaple or dagnostcnurpones They are . no CRC checking is performed; gap information is included in the data stream; the internal side com- ine CRC pare is not performed; and the address mark \\ddress| number | address | length | 1 | 2 ° detector is on for the duration of the command. vf [3 [4 Ts Te Because the AM detectoris always on, write splices or noise may cause the chip to look for an Although the CRC characters are transferred to the AM. If an address mark does not appear on sched- computer, the SAB 27938/27978 checks for validity _ule with the Lost Data status flag being set, the ID and the CRC Error status bitis set ifthere isa CRC AM, ID field, ID CRC bytes, DAM, data and data CRC error. The track address of the ID field is written into bytes for each sector will be correct. The gap bytes the Sector Register so that a comparison can be may be read incorrectly during write splice time made by the host. Atthe end of the operation an _ because of synchronization. interrupts generated and the Busy status bit is reset. Write Track Formatting the Disk Read Track Formatting the disk is a comparatively simple task Upon receipt of the Read Track command, the head __ when operating programmed I/O or when operating is loaded, and the Busy status bit is set. Reading under DMA with a large amount of memory. Data starts with the leading edge of the firstencountered —_ and gap information must be provided at the com- index pulse and continues until the nextindex pulse. puter interface. Formatting the disk is accomplished Siemens Aktiengesellschaft 54

a by positioning the R/W head over the desired track This sequence continues from one index markto the number and issuing the Write Track command. next. Normally, whatever data pattern appears in Upon receipt of the Write Track command, the head the Data Register, it is written on the disk with isloaded andthe Busy status bitis set. Writing starts a normal clock pattern. However, if the SAB 27938/ with the leading edge of the first encountered index 27978 detects a data pattern of FS thru FE in the pulse and continues until the next index pulse, at Data Register, this is interpreted as Data Address which time the interrupt is activated. The data Marks with missing clocks or CRC generation. The request is activated immediately upon receipt of CRC generator is initialized when any data byte from command, but writing will not start before the F8to FE is about to be transferred from the DR to the first byte is loaded into the Data Register. If the DSR or by receipt of F5 in MFM. An F7 pattern will DR has not been loaded by the time the index pulse _generate two CRC characters in FM or MFM. As a is encountered the operation is terminated by consequence, the patterns F5 thru FE must not making the device not busy. The Lost Data status bit appear in the gaps, data fields, or ID fields. Also, ig set, and the interrupt is activated. If a byte is not CRCs must be generated by an F7 pattern. Disks may present in the DR when needed, a byte of zeros is __be formatted in IBM 3740 or System 34 formats with substituted, sector lengths of 128, 256, 512, or 1024 byte. Control Bytes for initialization Data Pattern ‘SAB 27938/2797B Interpretation SAB 27938/2797B Interpretation in DR (hex) in FM (DDEN = 1) in MFM (DDEN = 0) 00 thru F4 Write 00 thru F4 with CLK = FF ‘Write 00 thru F4, in MFM FS Not Allowed Write A1" in MFM, Preset CRC Fe Not Allowed Write C22 in MFM

7 Generate 2 CRC Bytes Generate 2 CRC Bytes

F8 thru FB Write F8 thru FB, CLK = C7, Preset CRC | Write F8 thru FB, in MFM FC Write FC with CLK = D7 Write FC in MEM FD Write FD with CLK = FF Write FD in MEM FE Write FE, CLK = C7, Preset CRC Write FE in MFM FF Write FF with CLK = FF Write FF in MFM ¥ Missing clock transition between bits 4 and 5

21 Missing clock transition between bits 3 and 4

The Force Interrupt command is generally used to command terminated. Reading the status register terminate a multiple sector Read or Write command —_ or writing to the Command Register will not auto- orto ensure Type status in the Status Register. This matically clear the interrupt, The hex DOs the only command can be loaded into the Command ‘command that will enable the immediate interrupt Register at any time. If there is a current command —_(hex D8) to clear on a subsequent load Command under execution (Busy status bit set) the command _Register or read Status Register operation. Follow a will be terminated and the Busy status bit reset. hex D8 with @ DO command. Wait 8 ys (double The lower four bits of the command determine the _ density) or 16 us (single density} before issuing a conditional interrupt as follows: new command after a Force Interrupt command has 0: Not-Ready to Ready Transition been issued (times double when clock = 1 MHz). 11: Ready to Not-Ready Transition ‘Loading a new command sooner than this will 12: Every Index Pulse nullify the forced interrupt. Forced interrupt stops 13: Immediate Interrupt any command at the end of an internal micro- The conditional interrupt is enabled when the instruction and generates INTRO when the specified corresponding bit positions of the command condition is met. Forced interrupt will wait until (I3-10) are set to a1. Then, when the condition for ALU operations in progress are completed (CRC interrupt is met, the INTRQ line will go high signify- calculations, comparisons, etc:). More than one ing that the condition specified has occurred. condition may be set at a time. If, for example, the if 13-10 are all set to zero (hex DO), no interrupt will Ready to Not-Ready condition (I1 = 1) and the Every occur but any command presently under execution —_ Index Pulse (I2 = 1) are both set, the resultant com- will be immediately terminated. When using the mand will be hex DA. The OR function is performed immediate interrupt condition (I3 = 1),an interrupt so that either a Ready to Not-Ready or the next Index will be immediately generated and the current Pulse will cause an interrupt condition. Siemens Aktiengeselischaft 55

IBM 3740 Format - 128 Byte/Sector (8”) IBM System 34 Format - 256 Byte/Sector (8") ‘Shown below is the IBM single-density format with Shown in the following table is the IBM double- 128 byte/sector. In order to format a diskette, the density format with 256 byte/sector. In order to user must issue the Write Track command, and load —_ formata diskette the user must issue the Write Track the Data Register with the following values. For ‘command and load the Data Register with the every byte to be written, there is one data request. _ following values. For every byte to be written, there is one data request. Number Hex Value of of Bytes _| Byte Written Number — | Hex Value of 40 | FF (or 00)" of Bytes _| Byte Written 6 | 00 80 | 4E 1 | FC (Index Mark) 12 | 00 26 | FF (or 00) 3 | F6 (Writes C2) » 6 00 1 FC (Index Mark)

1 FE (ID Address Mark) 50 4e

1 Track Number uy 12 00

1 Side Number (00 or 01) 3 F5 (Writes A1)

1 | Sector Number (1 thru 1A) 1_| FE (ID Address Mark)

1 Joo 1 | Track Number (0 through 4C)

1 F7 (2 CRCs Written) 1 Side Number (0 or 1)

a FF (or 00) 1 Sector Number (1 through 1A) 6 00 1 01 (Sector Length) 1 FB (Data Address Mark) 1 F? (2 CRCs Written)

128 Data (E5) 22 ae

1 | F7 (2 CRCs Written) 12 | 00

27 FF (or 00) 3 F5 (Writes Al)

2477) FF (or 00) 1 FB (Data Address Mark)

256 Data (E5)

| 1 F7 (2 CRCs Written) | 54 | 4€ | 598”) 4E 1 Write bracketed field 26 times. | Continue writing until SAB 2793B/2797B interrupts out. Approx. 247 (598) byte. 3! Optional ‘00’ on SAB 2797B only is allowed. Siemens Aktiengeselischaft 56

a Recommended ~ 128 Byte/Sector (Minidiskette) __ Recommended ~ 256 Byte/Sector (Minidiskette) Shown below is the recommended single-density Shown below is the recommended double-density format with 128 byte/sector. In order to format a format with 256 byte/sector. In order to format a diskette, the user must issue the Write Track diskette the user must issue the Write Track ‘command, and load the Data Register with the command and load the Data Register with the following values. For every byte to be written, there following values. For every byte to be written, there is one data request. is one data request. Number Hex Value of Number Hex Value of of Bytes __| Byte Written of Bytes _| Byte Written 40__| FF (or 00) 60 [ae u 6 00 412 00

1 FE (ID Address Mark) 3 FS (Writes A1)

1 | Track Number 1 | FE (ID Address Mark) 1 | Side Number (00 or 07) 1 | Track Number (0 through 4C)

1 Sector Number (1 through 10) 1 Side Number (0 or 1)

1 00 (Sector Length) 1 ‘Sector Number (1 through 10) 1 | F7(@CRCs Written) 1} 01 (Sector Length) Ww FF (or 00) 1 F7 (2 CRCs Written) 6 00 22 4e

1 FB (Data Address Mark) 12 00

128 Data (E5) 3 F5 (Write Al)

1 F7 (2. CRCs Written) 1 FB (Data Address Mark)

10 FF (or 00) 256 Data (E5)

3497 | FF (or 00) 1 | F7(2CRCs Written) za ae 718" | 4e Non-Standard Formats Variations in the IBM formats are possible to a limited extent if the following requirements are met: 1. Sector size must be 128, 256, 512 or 1024 byte. 2. Gap 2 cannot be varied from the recommended format. 3.3 bytes of A1 must be used in MFM. In addition, the Index Address Mark is not required for operation by the SAB 2793B/2797B. Gap 1, 3, and 4 lengths can be as short as 2 bytes for SAB 2793B/ 27978 operation, however, PLL lock-up time, motor speed variation, write-splice area, etc., will add more bytes to each gap to achieve proper operation. Itis recommended that the IBM format should be used for highest system reliability. [rm | ment Gap! TeByteFF | 32Byte4E Gap nipyerF — |22 Byte aE * 6 Byte 00 12 Byte 00

3 Byte Al

Gap ill 10 Byte FF 24 Byte 4E

4 Byt900 Seeat Dirt bracketed field T8times:

‘ontinue writing until ” inter: Seplv 16 Byte FF__| 16 Byte 4E rupts out. Approx. 349 (718) byte. Byte counts must be exact. ) Byte counts are minimum, except exactly 3 bytes ‘of A1 must be written in MFM. ‘Siemens Aktiengesellschaft 57

_— ee [= | on 8 = | 2 | h Eq ; “HE La | ue ox ial i HE a ii Bee fa Siemens Aktiengeselischaft 58

Recommended Double-Density Format (Minidiskette) La “| sf | i aa Py fa) LL ea [=] 3 Es 8 bast] / P-L i ach . has ry é g z g 3 Siemens Aktiengesellschaft 60

a Absolut Maximum Ratings” Ambient Temperature Under Bias Oto + 70°C Storage Temperature ~65 to +150°C Voltage on Any Pin with Respect to Ground (VSS) -05t0 +7V Power Dissipation 2W DC Characteristics TA = 010 70°C; VCC = +5%; VSS = OV sme “Tie [et Tenconeen [in. [7yp. [Max._| 1L1__| Input Leakage Current” [-[- [ro [ua __ | vin=vec H1L2 _ | Internal Leakage Current” [100 _[- | 1700 VIN = OV 1OL __ | Output Leakage Current [- [= [ro [ua __[vour=vec vi | input High Voltage [zo [= - |v = Vi___ [input Low Voltage [- = fos [v= VOH | Output High Voltage loa [- [- |v _ [10H =~ 100ua VOL__| Output Low Voltage [-_|[- [oas |v [tor=1.6ma_- VOHP | Output High PUMP [22 |- [- |v ___[tonp=~1.0ma VOLP _[ Output Low PUMP [-_[- [oz |v [iorp=+1.0ma icc | Supply Current [- [70 [150 [ma _ | Alloutputs open. Capacitance”! i Symbol] Parameter Limit Value | Unit _| Test Condition (max.) CIN Input Capacitance | _15 | _pF_| Unmeasured pins © Stresses above those listed under , Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2/111 applies to normal inputs, IIL 2 to inputs with internal pull-up resistors on pins 1, 17, 19, 22, 36, 37, and 40, Also pin 25 on SAB 27938.

2 This parameter is periodically sampled and not 100% tested

Siemens Aktiengesellschaft 61

TA = 010 70°C; VCC = +5V +5%; VSS = OV. All timing readings at VOL-= 0.8V and VOH = 2.0V. Read Enable Timing Symbol] Parameter Test Condition [min [Typ. [Max._| TSET _| Setup Adar. and C5 to RE [so |[- |[- [ns |- THLD _| Hold Addr. and CS from RE. ce ee ee TRE__[ RE Pulse Width [200 [- [- [ns [cu=s0pF ToAR [DRG Reset from RE |= [100 [200 [ns [- TIRR_ [INTRO Reset from RE [= [800 [3000 [ns [- TDACC | Data Valid from RE |= [100 [200 [ns [cu =50pF TOOH | Data Hold from RE [20 [- iso [ns [CL=50pF Read Enable Timing wene ron rT = ma —| ' 5 ' RR ' — Intra! Tservice? oe AgALS" vi TRE ® ve ser ota are ox [- oo Toace DRQ rising edge: Indicates that the data register has assembled data. DRQ falling edge: _Indicates that the data register was read. INTRO rising edge: Occurs at end of command, INTRO falling edge: Indicates that the status register was read CS may be permanently tied low if desired. 2'T Service (worst case) FM = 27.5 us 3! Time doubles when CLK = 1 MHz. —MFM = 13.5 us Siemens Aktiengeselischaft 62

Symbol | Parameter Test Condition [ min. [Typ [Max | TSET | Setup Addr. and CS to WE [so [= [= [ns - THLO _| Hold Addr. and CS from WE fro [- |- [ns |- Twe | WE Pulse width Ee ee TORR | ORO Reset from WE [=~ [roo [200 [ns |= TIRR_[ INTRO Reset from WE [= [500 [3000 [ns __|~ TDS _ | Dota Setup to WE fiso [= [= [ns f= TOH [Data Hold from WE [so [== [ans Write Enable Timing 016 oF Ips | Ra i we ora — ' . wwrea Terie” vo. ao} asa" ve 1 WE ca wit rset be ales ron DRO risingedge: _ Indicates that the data register is empty. DRO falling edge: _ Indicates that the data register is loaded. INTRO rising edge: _ Indicates the end of a command. INTRO falling edge: Indicates that the command register is written to. ‘| CS may be permanently tied low if desired. When writing Data into Sector, Track or Data Register, the User cannot read this register until at least 4 us in MFM after the rising edge of WE. When writing into the Command Register status is not valid until some 28 us in FM/14.us in MFM later. These times double when CLK = 1 MHz. 2) T Service (worst case); FM = 23.5 1s; MFM = 11.5 us. 9) Time doubles when CLK = 1 MHz ‘Siemens Aktiengesellschaft 63

PB — 1 viK Lie] we — V1 f- vi Le —| 101 ser oH ee re Sip aa 4 e sons t ome sn von roe ae i sxe a Siemens Aktiengesellschaft 65

Symbol Unit | Test Condition [min [Typ. [Mex Tew [RAWREAD Puce wiaih | 0 | 200-[- [ns [= Read Data Timing TBC TPW RAW READ. Write Data Timing nee a se ve [eeonton [in [typ. | ox_| MFM. MFM. Gwe [wine Geuomwe ee a Ce eT All times double when CLK = 1 MHz; no Write precompensation. Write Data Timing TWP | —— WD | Twa! TWF WG ‘Siemens Aktiengesellschaft 66

Plastic Package, P-DIP, 40 pins 18,2h002 HT eee A ASIA a TT J Vy YU thos ooh ie 7 4 8 Woz 4 25h _ ioe 045" 38 15242 SSS SSS Sees SST SST 509.65 Dimensions inmm Siemens Aktiengeselischaft 67

Ordering Information

‘SAB 2793B-P (Q67120-Y82 Floppy disk controller; true data bus, single-sided operation SAB 27978-P 067120-Y84_| Floppy disk controller; true data bus, double-sided operation Siemens Aktiengeselischaft 68

Overview

SAB2793B is listed in the IC category. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

Advanced Floppy Disk Formatter/Controller Family

Description