SAA9057A ETC1
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Philips Semiconductors Video Products Preliminary specification LN Clock signal generator circuit SAAS057A for digital TV systems (CGC) a Supercedes data of April 1991 FEATURES QUICK REFERENCE DATA Clock generation suitable for digital TV systems (line-locked) SYMBOL PARAMETER [ wn, [ve [ax. | unre | PLL frequency multiplier to 7 Dividers to generate clocks LL1.5, digit ly volta 7 as _| [ss iv | U2 LL2A,LL3 and LT (4th, ard |YODD_| Stal supply voltage (Pins 8,17) [so _| and 2nd multiples of input analog supply current an 2nd ef fe [ra « Skew contol or clock outputs [000 _| sal supe eurent jo [eo [ma Reset control and power fail Virco | LFCO input voltage detection (peak-to-peak value) Vppa | V i | input frequency range lees | | 7.25 | MHz vi input voltage LOW os Vv input voltage HIGH Vopp | V ouput voage HIGH Bo [eeely _| SAA9051A not for new designs, put voltage oD for new applications use Tamb operating ambient temperature SAA9057B or SAA7157 range 70 (|9C GENERAL DESCRIPTION The SAA9057A generates all clock ORDERING INFORMATION signals required for a digital TV system suitable for the SAA9Oxx EXTENDED PACKAGE family. Optional extras (feature box TYPE NUMBER lawns] [cove _| etc.) can be driven via external PIN POSITION MATERIAL buffers, adventageous for a digital ‘SAASOS7A j20] ou «|p| sOT146 TV system based on display standard conversion concepts. SAAOS7AT mini-pack (S020) | plastic | SOTI63A May 1992 3-309
Philips Semiconductors Preliminary specification Clock signal generator circuit for digital TV systems (CGC) SAAS0S7A Oe PINNING PIN CONFIGURATION [srweou[ pw [oescnpnon su wf Uo bus sx | 4 [anaoggonmey || vor Poon | & | analog svppyvorage sy iY naan Fl [suis | 6 | sensorimputroupnuts | YE EI - Vooor [84 [13] SLLS [Suiza | 0 | sensorinpurtroupurutza || tan Farce futaa | 10 | tne-ockes dock ouput signal or ADE (ines froo)| [RESN [12 [resctouputtecivelow) | [sus | 13 | sersorinputtroupatlts [2 [78 inorecked cock ouput sara Ones iigoo) | [Hat | 2 [inwiecied cock ouputsonal@inesiireod | LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). smo] rnanenen | wn [woe [or Wan cn | aoencevetage Vopa=Yooo |-__|s00_[mv_| vo _[eupavatage ow =20ma) —[-05 [vooo |v _| [Pox [walpowerdaspaion fo fiat |W | Fano [ceesing anverienperanrerange fo [70 [=o _| eso [esevosmicraraing erations [fer |v | * Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is recommended to take normal handling precautions appropriate to "Handling MOS devices °. May 1992 3-311
Philips Semiconductors Preliminary specification Clock signal generator circuit for digital TV systems (CGC) SAA9057A CHARACTERISTICS fawieoe | vananeren———[_conomons [wm | we [ wax | or [Yoon | aracg sumivotagoiansy «| —~—SCS~wSO ‘ds [ooo | ata sven votage ns eana™m | «das sofas |v _| Foon | araiog upey curernipny fi «ta Hoo feats supp urent tg ri) free? ———*dtto ‘feo [ma_| [Vuser | poweron eset tveshovolage [Fea ——*dt- ‘das dv | [vin [0Cimpuivotags Sid Cd ‘on lico | inpurtroquencyrange S| SSSSSC~*d ts ids | ee a ce va [ipuvogeow TCC Cid [Vm [rouvoragenicn | «2 Vo 1 _| fix [epeticstage crest [ci _|mpuicapactance SS] SCd* dS dr [vou [oumutvotagetow ————<diu=ema—igo [ides dv [Vou | oupuvotagenich “lows 0Sma__f2a | Ivo |v __| [ii [ouutcakanecurens | «do Cn ee Output signals LL1.5, LL2, LL2A, LL3, LL3T (pins 7, 10, 14, 15 and 20) [Vo._[oupuvotagetow tg =2ma ito «(ids id [Vow | cupuvotegeHicH | lowe-osma [28 | _|voon |v _ [in [outputteakagecunent _———(nighimpedares | __|x0__[ wa _| [tome | compositersetime [note tinote2 ffs | ouputecueney 2 dtd «dpc | [[ouputtreaueney 2A | =i «deco | | | __foutputtreauency ues fete _| iu [ouytactortsanatie —notetiFigad [ao 50 eo de [ [euytecortiza usaraiist |rowritigs faa _|so_|s7_[% _| CC May 1992 3312
Philips Semiconductors Preliminary specification Clock signal generator circuit SAAQ057A for digital TV systems (CGC) a Notes to the characteristics 1. fLFCo = 7.0 MHz and output load 40 pF. Vggq and Vggp short connected together. 2. tcomp is the rise time from LOW of all clocks to HIGH of all clocks (Fig.3) including rise time, skew and jitter components. Measurements taken between 0.6 V and 2.6 V. 3. MS function is not tested. tus Thus Tuss_, ——— —— 26v us 18V o6v tr ty Jp tay tue ~ Tuan Le —— 26V LL2A 15V o5v ety bee in + ——— tt ts rt te LL | * — 26v Lust | } I—— 15v | OV weHase Fig.3 Output timing. May 1992 3-313
Philips Semiconductors Preliminary specification Clock signal generator circuit for digital TV systems (CGC) SAA9057A j ov 7777/7 BE, LFCO. 4 oscillation 5 Yj RESN ts It+-—— 14 fe— operation | oparasan LL . com -— tLea 4 A LL3. oo Por LUT bit-} iT PLL tock-on Bower tale clock HIGH reset procedure intone? rset — wenaer Fig.4 Reset procedure. May 1992 3-314
Philips Semiconductors Preliminary specification miulips semiconductors Clock signal generator circuit for digital TV systems (CGC) SAA9057A A +12 V analog +5 :V digilal “ev IKK sso 0.1 pF Lust [] 220 2 19 > 1s 0.1 uF bap | | ” 0:33 uF ssp I} 3 18 3 18 4 17 4 WF ou |_| i | Yoon +5.1V 5 16 Ly 16 82x79" iF 6 18 6 18 csv1 HF ON esp | | us 7 “4 7 4 . i 8 13 8 13 i a 2 8 2 ee | 10 WW 10 W as LTT ws Woo RESN wens Fig.5 Application circuit May 1992 3-315