DATASHEET SEARCH SITE

Document overview

  • Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 7

Technical content

Features

Excellent temperature stability Ultra Low Jitter 0.05 to 0.3 ps integrated 12 kHz to 20 MHz Wide frequency range Close-in Phase Noise optimized for Wireless RF applications Cost-effective SMD packages with narrow pads compatible to J-Lead packages Low profile 2.6 mm height available Specifications ----- 1.0 SPECIFICATION REFERENCES Line Parameter

Description

1.1 Model Description RVX1490M VCXO 1.2 RoHS Compliant Yes 1.3 Reference Number 1.4 Rakon Part Number 1.5 Package Type Type 1 (Standard), or Type 2 (Reduced profile), or Type 3 (Low profile) ----- 2.0 FREQUENCY CHARACTERISTICS Line Parameter Test Condition Value Unit 2.1 Frequency 50 to 500 MHz 2.2 Operating Temperature Range -40 to 85 2.3 Frequency Stability Including Temperature range, Supply variation, Load variation and 15 years aging at 25°C ±30 to 50 ppm 2.4 Temperature Stability Over operating temperature range only ±10 to 20 ppm ----- 3.0 POWER SUPPLY Line Parameter Test Condition Value Unit 3.1 Supply Voltage (VDD) With a tolerance of ±10% (not available with all configurations) 3.3 V 3.2 Supply Current 55 to 80 mA ----- Page 1

4.0 CONTROL VOLTAGE (VCO) Line Parameter Test Condition Value Unit 4.1 Absolute Pull Range (APR) ±50 min ppm 4.2 Total Pull Range Frequency shift from minimum to maximum control voltage 100 to 250 ppm 4.3 Control Voltage Nominal 1.65V 0 to 3.3 V 4.4 Linearity Control voltage 0.3 to 3V 10 max 4.5 Slope Positive only 4.6 Modulation BW 15 min kHz 4.7 Input Impedance MΩ ----- 5.0 OUTPUT CHARACTERISTICS Line Parameter Test Condition Value Unit 5.1 Output LVPECL 5.2 Output Voltage (Vol) 50Ω nominal load. (VDD - 1.6V) max. 5.3 Output Voltage (Voh) 50Ω nominal load. (VDD - 1.03V) min. 5.4 Duty Cycle @ VDD-1.3V 45 to 55 5.5 Output Load With VDD-2V Ω 5.6 Rise Time/ Fall Time 80%/20% 0.6 max ns 5.7 RMS Phase Jitter Typical integrated 12kHz to 20MHz 0.05 to 0.15 ps ----- 6.0 SSB PHASE NOISE Line Parameter Test Condition Value Unit 6.1 SSB Phase Noise power density @ 10 Hz offset Typical value for a 122.88 MHz VCXO @ 25 °C -70 dBc/Hz 6.2 SSB Phase Noise power density @ 100 Hz offset Typical value for a 122.88 MHz VCXO @ 25 °C -100 dBc/Hz 6.3 SSB Phase Noise power density @ 1 kHz offset Typical value for a 122.88 MHz VCXO @ 25 °C -127 dBc/Hz 6.4 SSB Phase Noise power density @ 10 kHz offset Typical value for a 122.88 MHz VCXO @ 25 °C -145 dBc/Hz 6.5 SSB Phase Noise power density @ 100 kHz offset Typical value for a 122.88 MHz VCXO @ 25 °C -155 dBc/Hz 6.6 SSB Phase Noise power density @ 1 MHz offset Typical value for a 122.88 MHz VCXO @ 25 °C -157 dBc/Hz ----- 7.0 SSB PHASE NOISE Line Parameter Test Condition Value Unit 7.1 SSB Phase Noise power density @ 10 Hz offset Typical value for a 491.52 MHz VCXO @ 25 °C -60 dBc/Hz 7.2 SSB Phase Noise power density @ 100 Hz offset Typical value for a 491.52 MHz VCXO @ 25 °C -90 dBc/Hz 7.3 SSB Phase Noise power density @ 1 kHz offset Typical value for a 491.52 MHz VCXO @ 25 °C -113 dBc/Hz 7.4 SSB Phase Noise power density @ 10 kHz offset Typical value for a 491.52 MHz VCXO @ 25 °C -132 dBc/Hz 7.5 SSB Phase Noise power density @ 100 kHz offset Typical value for a 491.52 MHz VCXO @ 25 °C -145 dBc/Hz ----- Page 2

8.0 ENVIRONMENTAL SPECIFICATION Line Parameter 8.1 Mechanical Shock MIL-STD-883, Method 2002 8.2 Storage Temperature Range -55 to 125°C 8.3 Humidity After 48 hours at 85°C±2°C 85% humidity non-condensing 8.4 Thermal Shock MIL-STD-883, Method 1011 8.5 Vibration MIL-STD-883, Method 2007 ----- 9.0 MANUFACTURING INFORMATION Line Parameter 9.1 Packaging Description Tape and reel. Standard packing quantity is 500 per reel 9.2 Reflow Solder reflow process as per attached profile ----- 10.0 PIN CONNECTIONS Line Parameter 10.1 Pin 1 VCO 10.2 Pin 2 E/D* or NC 10.3 Pin 3 GND 10.4 Pin 4 OUTPUT 10.5 Pin 5 COMPLIMENTARY OUTPUT 10.6 Pin 6 VDD 10.7 * Output Enabled >70% of VDD on E/D pin, or E/D pin left open (connected to internal pull-up resistor) 10.8 * Output Disabled <30% of VDD on E/D pin, or E/D pin to GND 10.9 * Output Enabled Low Available upon request ----- 11.0 PRODUCT MARKING Line Parameter 11.1 Top Line 11.2 Middle Line 11.3 Bottom Line [o FYWW] Pin 1, Manufacturing code, Year code* and Week code** 11.4 * Year Code A = 2010, B = 2011, C = 2012, D = 2013, ... Z = 2035 11.5 ** Week Code WW = 01 = Week of first Monday of the year Page 3

Drawing Name: XO/VCXO 1490M T6 Model Drawing Page 4

Drawing Name: Rakon 1490 Test Circuit Page 5

Drawing Name: 1490M-Hi Series Tape & Reel Page 6

Drawing Name: Pb-Free Reflow Page 7