RTL8029AS

RTL8029AS ETC2

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 41

Technical content

Realtek PCI Full-Duplex Ethernet Controller with built-in SRAM ADVANCE INFORMATION REALTEK SEMI-CONDUCTOR CO., LTD. HEAD OFFICE 1F, NO. 11, INDUSTRY E. RD. IX, SCIENCE-BASED INDUSTRIAL PARK, HSINCHU 30077, TAIWAN, R.O.C. TEL:886-3-5780211 FAX:886-3-5776047 OFFICE 3F, NO. 56, WU-KUNG 6 RD., TAIPEI HSIEN, TAIWAN, R.O.C. TEL: 886-2-2980098 FAX: 886-2-2980094, 2980097

LS009.0 1997.01.16 RTL8029AS Preliminary

LS009.0 1997.01.16 RTL8029AS Preliminary

LS009.0 1997.01.16 RTL8029AS Preliminary 1. FEATURES m 1 0 0 - p in P Q F P ¯ Pin-to-pin compatible with RTL8029 ¯ 16K byte SRAM built in ¯ Compliance to PCI V2.1 ¯ Programmable PCI Vendor ID and Sub Vendor ID m P C I lo c a l b u s s in g le - c h ip E th e r n e t c o n t r o lle r m C o m p lia n t to E th e r n e t I I a n d I E E E 8 0 2 .3 1 0 B a s e 5 , 1 0 B a s e 2 , 1 0 B a s e T m S u p p o r ts F u ll- D u p le x E th e r n e t fu n c tio n t o d o u b le c h a n n e l b a n d w id t h ¯ Support Flow Control(802.3x) to improve network performance in full-duplex mode m S u p p o r ts th r e e le v e l p o w e r d o w n m o d e s : - S le e p - P o w e r d o w n w ith in te r n a l c lo c k r u n n in g - P o w e r d o w n w ith in te r n a l c lo c k h a lt e d m B u ilt- in d a ta p r e fe tc h fu n c tio n to im p r o v e p e r f o r m a n c e m B u ilt- in 1 0 B a s e T tr a n s c e iv e r m P r o v id e s a u to - d e te c t c a p a b ility b e tw e e n in t e g r a t e d 1 0 B a s e T t r a n s c e iv e r a n d A t t a c h m e n t U n it I n te r fa c e ( A U I ) m S u p p o r ts a u to p o la r ity c o r r e c tio n fo r 1 0 B a s e T m S u p p o r ts B o o t R O M fu n c tio n fo r P C I b u s m S u p p o r ts 8 K , 1 6 K a n d 3 2 K B o o t R O M s iz e m U s e 9 3 4 6 ( 6 4 * 1 6 - b it E E P R O M ) to s t o r e r e s o u r c e c o n f ig u r a t io n s a n d I D p a r a m e t e r s m C a p a b le o f p r o g r a m m in g b la n k 9 3 4 6 o n b o a r d f o r m a n u f a c t u r in g c o n v e n ie n c e m S u p p o r ts 4 d ia g n o s tic L E D p in s w ith p r o g r a m m a b le o u t p u t s P.S. “¯” denotes new feature of RTL8029AS

LS009.0 1997.01.16 RTL8029AS Preliminary 2. GENERAL DESCRIPTION T h e R T L 8 0 2 9 A S c o n tr o lle r is a n N E 2 0 0 0 c o m p a t ib le E t h e r n e t C o n t r o lle r f o r P C I in t e r f a c e . T a k in g t h e b e n e fit o f P C I 's h ig h th r o u g h p u t r a te , t h e R T L 8 0 2 9 A S c o n t r o lle r o f f e r s a 3 2 - b it d a t a p a t h t o h ig h ly im p r o v e th e d a ta tr a n s fe r r a te c o m p a r e d w it h t r a d it io n a l E t h e r n e t c a r d o n I S A , E I S A a n d M C A b u s . D u e to th e a d d itio n a l b e n e fit s o f P C I , t h e R T L 8 0 2 9 A S c o n t r o lle r p r o v id e s a lo w m a in ta in in g c o s t n e tw o r k e n v ir o n m e n t w it h o u t u s a g e b a r r ie r s . T h e A u t o - c o n f ig u r a t io n f u n c t io n o f P C I c a n r e lie v e th e u s e r s fr o m p a in s o f ta k in g c a r e t h e s y s t e m r e s o u r c e c o n f lic t . T h e R T L 8 0 2 9 A S c o n tr o lle r a ls o s u p p o r ts fu ll- d u p le x a n d p o w e r d o w n f e a t u r e s . W it h t h r e e le v e ls p o w e r d o w n c o n t r o l f e a tu r e s , th e R T L 8 0 2 9 A S c o n tr o lle r is m a d e t o b e a n id e a l c h o ic e o f t h e n e t w o r k d e v ic e f o r a G R E E N P C I P C s y s te m . T h e fu ll- d u p le x f u n c t io n e n a b le s s im u lt a n e o u s ly t r a n s m is s io n a n d r e c e p t io n o n th e tw is te d - p a ir lin k to a fu ll- d u p le x E t h e r n e t s w it c h in g h u b . T h is f e a t u r e n o t o n ly in c r e a s e s t h e c h a n n e l b a n d w id th fr o m 1 0 to 2 0 M b p s b u t a ls o a v o id s t h e p e r f o r m a n c e d e g r a d in g p r o b le m d u e t o t h e c h a n n e l c o n te n tio n c h a r a c te r is tic s o f th e E t h e r n e t C S M A /C D p r o t o c o l. T h e R T L 8 0 2 9 A S c o n tr o lle r r e q u ir e s n o g lu e lo g ic a n d in t e g r a t e s w it h M a n c h e s t e r E n c o d e r /D e c o d e r a n d 1 0 B a s e T tr a n s c e iv e r o n c h ip . T h e b u ilt - in 1 0 B a s e T t r a n s c e iv e r c a n a u t o m a t ic a lly c o r r e c t t h e p o la r ity e r r o r o n its r e c e iv in g p a ir . T h e R T L 8 0 2 9 A S c o n t r o lle r a ls o h a s t h e c a p a b ilit y o f a u t o - s e n s in g fo r 1 0 B a s e 2 o r 1 0 B a s e T c o n n e c t io n . F o u r d ia g n o s t ic L E D s s u p p o r t e d b y R T L 8 0 2 9 A S c o n tr o lle r s im p lify th e tr o u b le s h o o tin g p r o c e d u r e in a n e t w o r k . F u r t h e r m o r e , T h e R T L 8 0 2 9 A S c o n tr o lle r s u p p o r ts 8 K , 1 6 K & 3 2 K b y te B o o t R O M . I t c a n b e a p p lie d in a w o r k s t a t io n w it h o u t d is k t o im p r o v e th e n e tw o r k s e c u r ity a n d m a n a g e m e n t c o n v e n ie n c e . D a t a p r e f e t c h f u n c t io n in R T L 8 0 2 9 A S c o n tr o lle r c a n e n h a n c e th e d a t a t r a n s m is s io n a n d h ig h ly u p lif t t h e n e t w o r k p e r f o r m a n c e w ith o u t e x tr a fe e .

LS009.0 1997.01.16 RTL8029AS Preliminary 3. PIN CONFIGURATION 79 X2

80 GND

81 CD-

82 CD+

83 RX-

84 RX+

85 VDD

87 TPIN+

88 INTAB

89 RSTB

90 CLK

91 GND

92 AD31

93 AD30

94 AD29

95 AD28

96 AD27

97 AD26

98 AD25

86 TPIN-

48 GND

47 MD0

46 MD1

45 MD2

44 MD3

43 MD4

42 MD5

41 MD6

40 MD7

37 AD1

36 AD2

35 AD3

34 GND

33 AD4

32 AD5

31 AD6

30 AD7

29 CBE0B

39 VDD

38 AD0

100 VDD

1 CBE3B

2 IDSEL

3 AD23

4 AD22

5 AD21

6 AD20

7 AD19

8 AD18

9 AD17

10 AD16

11 GND

12 CBE2B

13 FRAMEB

27 AD9

26 AD10

25 AD11

24 AD12

23 AD13

22 VDD

21 AD14

20 AD15

19 CBE1B

18 PAR

28 AD8

17 GND

16 DEVSELB15 TRDYB

14 IRDYB

99 AD24

62 MA8

61 MA7

60 MA6

59 MA5

58 MA4

57 MA3[EESK]

56 MA2[EEDI]

55 MA1[EEDO]

54 MA0

53 EECS

63 MA9

52 VDD

51 MA14

49 BOEB

65 MA1166 MA12

67 MA13

68 LED2[LED_TX]

69 LED1[LED_RX][LED_CRS]

70 LED0[LED_COL][LED_LINK]

71 LED_BNC

72 GND

73 TPOUT+

74 TPOUT-

64 MA10

75 VDD

76 TX-

77 TX+

LS009.0 1997.01.16 RTL8029AS Preliminary 4. PIN DESCRIPTIONS 4.1. Signal Type Definition P P o w e r p in s in c lu d e V D D a n d G N D . I I n p u t is a s ta n d a r d in p u t- o n ly s ig n a l. O I t in d ic a te s o u tp u t s ig n a l. T/S T r i- S ta te is a b i- d ir e c tio n a l, t r i- s t a t e in p u t /o u t p u t p in . S/T/S S u s ta in e d T r i- S ta te is a n a c t iv e lo w t r i- s t a t e s ig n a l o w n e d a n d d r iv e n b y o n e a n d o n ly o n e a g e n t a t a tim e . T h e a g e n t t h a t d r iv e s a n S /T /S p in lo w m u s t d r iv e it h ig h fo r a t le a s t o n e c lo c k b e fo r e le t t in g it f lo a t . O/D O p e n D r a in a llo w e d m u ltip le d e v ic e t o s h a r e a s a w ir e - O R . 4.2. Power Pins No. Name Type Description 2 2 , 3 9 , 5 2 , 7 5 , 8 5 , 1 0 0 V D D P + 5 V D C p o w e r 1 1 , 1 7 , 3 4 , 4 8 , 7 2 , 8 0 , 9 1 G N D P G r o u n d 4.3. PCI Bus Interface Pins No. Name Type Descriptions 9 0 C L K I B u s C lo c k p r o v id e s tim in g f o r a ll tr a n s a c tio n s o n P C I a n d is a n in p u t p in to e v e r y P C I d e v ic e . A ll b u s s ig n a ls a r e s a m p le d o n th e r is in g e d g e o f C L K a n d a ll p a r a m e te r s a r e d e f in e d w ith r e s p e c t to th is e d g e . 9 2 - 9 9 , 3 - 1 0 , 2 0 , 2 1 , 2 3 - 2 8 , 3 0 - 3 3 , 3 5 - 3 8 A D 3 1 - 0 T /S A d d r e s s /D a ta a r e m u ltip le x e d o n th e s a m e P C I p in s . A b u s tr a n s a c tio n c o n s is ts o f a n a d d r e s s p h a s e f o llo w e d b y o n e o r m o r e d a ta p h a s e s . T h e a d d r e s s p h a s e is th e c lo c k c y c le in w h ic h F R A M E B is a s s e r te d . D u r in g d a ta p h a s e A D 7 - 0 c o n ta in th e le a s t s ig n if ic a n t b y te ( ls b ) a n d A D 3 1 - 2 4 c o n ta in th e m o s t s ig n if ic a n t b y te ( m s b ) . W r ite d a ta is s ta b le a n d v a lid w h e n I R D Y B is a s s e r te d a n d r e a d d a ta is s ta b le a n d v a lid w h e n T R D Y B is a s s e r te d . 1 , 1 2 , 1 9 , 2 9 C B E 3 - 0 B T /S B u s C o m m a n d /B y te E n a b le s a r e m u ltip le x e d o n th e s a m e P C I p in s . D u r in g th e a d d r e s s p h a s e o f a tr a n s a c tio n , C B E 3 - 0 B d e f in e th e B u s C o m m a n d . D u r in g th e d a ta p h a s e C B E 3 - 0 B a r e u s e d a s B y te E n a b le s . T h e B y te E n a b le s d e f in e w h ic h p h y s ic a l b y te la n e s c a r r y m e a n in g d a ta . C B E 0 B a p p lie s to b y te 0 ( ls b ) a n d C B E 3 B a p p lie s to b y te 3 ( m s b ) .

LS009.0 1997.01.16 RTL8029AS Preliminary 1 8 P A R T /S P a r ity is e v e n p a r ity a c r o s s A D 3 1 - 0 a n d C B E 3 - 0 B . P A R is s ta b le a n d v a lid o n e c lo c k a f te r th e a d d r e s s p h a s e . F o r d a ta p h a s e s P A R is s ta b le a n d v a lid o n e c lo c k a f te r e ith e r I R D Y B is a s s e r te d o n a w r ite tr a n s a c tio n o r T R D Y B is a s s e r te d o n a r e a d tr a n s a c tio n . 1 3 F R A M E B S /T /S C y c le F r a m e is d r iv e n b y th e c u r r e n t m a s te r to in d ic a te th e b e g in n in g a n d d u r a tio n o f a n a c c e s s . F R A M E B is a s s e r te d to in d ic a te a b u s tr a n s a c tio n is b e g in n in g . W h ile F R A M E B is a s s e r te d , d a ta tr a n s f e r s c o n tin u e . W h e n F R A M E B is d e a s s e r te d , th e tr a n s a c tio n is in th e f in a l d a ta p h a s e . 1 4 I R D Y B S /T /S I n itia to r R e a d y in d ic a te s th e in itia tin g a g e n t's a b ility to c o m p le te th e c u r r e n t d a ta p h a s e o f th e tr a n s a c tio n . I R D Y B is u s e d in c o n ju n c tio n w ith T R D Y B . A d a ta p h a s e is c o m p le te d o n a n y c lo c k w h e n b o th I R D Y B a n d T R D Y B a r e a s s e r te d . D u r in g a w r ite , I R D Y B in d ic a te s th a t v a lid d a ta is p r e s e n t o n A D 3 1 - 0 . D u r in g a r e a d , it in d ic a te s th e m a s te r is p r e p a r e to a c c e p t d a ta . W a it c y c le s a r e in s e r te d u n til b o th I R D Y B a n d T R D Y B a r e a s s e r te d s im u lta n e o u s ly . 1 5 T R D Y B S /T /S T a r g e t R e a d y in d ic a te s th e ta r g e t's a g e n t's a b ility to c o m p le te th e c u r r e n t d a ta p h a s e o f th e tr a n s a c tio n . T R D Y B is u s e d in c o n ju n c tio n w ith I R D Y B . A d a ta p h a s e is c o m p le te d o n a n y c lo c k w h e n b o th T R D Y B a n d I R D Y B a r e a s s e r te d . D u r in g a r e a d , T R D Y B in d ic a te s th a t v a lid d a ta is p r e s e n t o n A D 3 1 - 0 . D u r in g a w r ite , it in d ic a te s th e ta r g e t is p r e p a r e to a c c e p t d a ta . W a it c y c le s a r e in s e r te d u n til b o th I R D Y B a n d T R D Y B a r e a s s e r te d s im u lta n e o u s ly . 1 6 D E V S E L B S /T /S D e v ic e S e le c t, w h e n a c tiv e ly d r iv e n , in d ic a te s th e d r iv in g d e v ic e h a s d e c o d e d its a d d r e s s a s th e ta r g e t o f th e c u r r e n t a c c e s s . A s a n in p u t, D E V S E L B in d ic a te s w h e th e r a n y d e v ic e o n th e b u s h a s b e e n s e le c te d .

2 I D S E L I I n itia liz a tio n D e v ic e S e le c t is u s e d a s a c h ip s e le c t f o r

R T L 8 0 2 9 A S c o n tr o lle r d u r in g c o n f ig u r a tio n r e a d a n d w r ite tr a n s a c tio n . 8 9 R S T B I W h e n R S T B is a s s e r te d lo w , th e R T L 8 0 2 9 A S p e r f o r m s a n in te r n a l s y s te m h a r d w a r e r e s e t. R S T B m u s t b e h e ld f o r a m in im u m o f 1 2 0 n s p e r io d s . R S T B m a y b e a s y n c h r o n o u s to C L K w h e n a s s e r te d o r d e a s s e r te d . I t is r e c o m m e n d e d th a t th e d e a s s e r tio n b e s y n c h r o n o u s to g u a r a n te e c le a n a n d b o u n c e f r e e e d g e . 8 8 I N T A B O /D I n te r r u p t A is a n a s y n c h r o n o u s a tte n tio n s ig n a l w h ic h is u s e d to r e q u e s t a n in te r r u p t. 4.4. Memory Interface Pins (including BROM, EEPROM) No. Name Type Description 4 9 B O E B O B o o t R O M c h ip s e le c t. A c tiv e lo w s ig n a l, a s s e r te d w h e n B o o t R O M is r e a d . 5 0 N C - U n u s e d 5 3 E E C S O 9 3 4 6 c h ip s e le c t. A c tiv e h ig h s ig n a l, a s s e r te d w h e n 9 3 4 6 is r e a d /w r ite . 5 1 , 6 7 - 5 4 M A 1 4 - 0 O B o o t R O M a d d r e s s b u s [ 5 7 ] [ E E S K ] O 9 3 4 6 s e r ia l d a ta c lo c k

LS009.0 1997.01.16 RTL8029AS Preliminary [ 5 6 ] [ E E D I ] O 9 3 4 6 s e r ia l d a ta in p u t [ 5 5 ] [ E E D O ] I 9 3 4 6 s e r ia l d a ta o u tp u t 4 0 - 4 7 M D 7 - 0 I /O B o o t R O M d a ta b u s 4.5. Medium Interface Pins No. Name Type Description 8 2 , 8 1 C D + ,C D - I T h is A U I c o llis io n in p u t p a ir c a r r ie s th e d if f e r e n tia l c o llis io n in p u t s ig n a l f r o m th e M A U . 8 4 , 8 3 R X + ,R X - I T h is A U I r e c e iv e in p u t p a ir c a r r ie s th e d if f e r e n tia l r e c e iv e in p u t s ig n a l f r o m th e M A U . 7 7 , 7 6 T X + ,T X - O T h is A U I tr a n s m it o u tp u t p a ir c o n ta in s d if f e r e n tia l lin e d r iv e r s w h ic h s e n d M a n c h e s te r e n c o d e d d a ta to th e M A U . T h e s e o u tp u ts a r e s o u r c e f o llo w e r s a n d r e q u ir e 2 7 0 o h m p u ll- d o w n r e s is to r s to G N D . 8 7 , 8 6 T P I N + ,T P I N - I T h is T P in p u t p a ir r e c e iv e s th e 1 0 M b its /s d if f e r e n tia l M a n c h e s te r e n c o d e d d a ta f r o m th e tw is te d - p a ir w ir e . 7 3 , 7 4 T P O U T + ,T P O U T - O T h is p a ir c a r r ie s th e d if f e r e n tia l T P tr a n s m it o u tp u t. T h e o u tp u t M a n c h e s te r e n c o d e d s ig n a ls h a v e b e e n p r e - d is to r te d to p r e v e n t o v e r c h a r g e o n th e tw is te d - p a ir m e d ia a n d th u s r e d u c e jitte r s . 7 8 X 1 I 2 0 M h z c r y s ta l o r e x te r n a l o s c illa to r in p u t. 7 9 X 2 O C r y s ta l f e e d b a c k o u tp u t. T h is o u tp u t is u s e d in c r y s ta l c o n n e c tio n o n ly . I t m u s t b e le f t o p e n w h e n X 1 is d r iv e n w ith a n e x te r n a l o s c illa to r . 4.6. LED Output Pins No. Name Type Description 7 1 L E D _ B N C O T h is p in g o e s h ig h w h e n R T L 8 0 2 9 A S 's m e d iu m ty p e is s e t to 1 0 B a s e 2 m o d e o r a u to - d e te c t m o d e w ith lin k te s t f a ilu r e . O th e r w is e , th is p in is lo w . T h is p in c a n b e u s e d to c o n tr o l th e p o w e r o f th e D C c o n v e r te r f o r C X M A U a n d c o n n e c te d to a n L E D to in d ic a te th e u s e d m e d iu m ty p e . 7 0 L E D 0 O W h e n L E D S 0 b it ( in C O N F I G 3 r e g is te r o f R T L 8 0 2 9 A S P a g e 3 ) is 0 , th is p in a c ts a s L E D _ C O L . W h e n L E D S 0 = 1 , it a c ts a s L E D _ L I N K . 6 9 , 6 8 L E D 1 ,L E D 2 O W h e n L E D S 1 b it ( in C O N F I G 3 r e g is te r o f R T L 8 0 2 9 A S P a g e 3 ) is 0 , th e s e 2 p in s a c t a s L E D _ R X & L E D _ T X r e s p e c tiv e ly . W h e n L E D S 1 = 1 , th e s e p in s a c t a s L E D _ C R S & M C S B . P le a s e r e f e r to s e c tio n 6 .5 f o r d e ta ils o f th e lig h te n in g b e h a v io r o f a ll L E D s .

LS009.0 1997.01.16 RTL8029AS Preliminary 1 0 5. REGISTER DESCRIPTIONS T h e r e g is te r s in R T L 8 0 2 9 A S c o n tr o lle r c a n b e r o u g h ly d iv id e d in t o t w o g r o u p s b y t h e ir a d d r e s s a n d f u n c tio n s - - o n e fo r N E 2 0 0 0 , th e o th e r fo r P C I C o n f ig u r a t io n S p a c e . 5.1. Group 1: NE2000 Registers T h is g r o u p in c lu d e s 4 p a g e s o f r e g is te r s w h ic h a r e s e le c t e d b y b it P S 0 & P S 1 in t h e C R r e g is t e r . E a c h p a g e c o n t a in s 1 6 r e g is te r s . B e s id e s t h o s e r e g is t e r s c o m p a t ib le w it h N E 2 0 0 0 , t h e R T L 8 0 2 9 A S c o n tr o lle r d e fin e s s o m e r e g is te r s fo r s o ftw a r e c o n f ig u r a t io n a n d f e a t u r e e n h a n c e m e n t . 5.1.1. Register Table No (Hex) Page0 Page1 Page2 Page3 [R] [W] [R/W] [R] [R] [W] 0 0 C R C R C R C R C R C R 0 1 C L D A 0 P S T A R T P A R 0 P S T A R T 9346CR 9346CR 0 2 C L D A 1 P S T O P P A R 1 P S T O P - - 0 3 B N R Y B N R Y P A R 2 - CONFIG0 - 0 4 T S R T P S R P A R 3 T P S R - - 0 5 N C R T B C R 0 P A R 4 - CONFIG2 CONFIG2 0 6 F I F O T B C R 1 P A R 5 - CONFIG3 CONFIG3 0 7 I S R I S R C U R R - - - 0 8 C R D A 0 R S A R 0 M A R 0 - - - 0 9 C R D A 1 R S A R 1 M A R 1 - - HLTCLK

0 A 8029ID0 R B C R 0 M A R 2 - - -

0 B 8029ID1 R B C R 1 M A R 3 - - -

0 C R S R R C R M A R 4 R C R - -

0 D C N T R 0 T C R M A R 5 T C R - -

0 E C N T R 1 D C R M A R 6 D C R 8029ASID0 -

0 F C N T R 2 I M R M A R 7 I M R 8029ASID1 -

1 0 - 1 7 R e m o te D M A P o r t 1 8 - 1 F R e s e t P o r t N o te s : " - " d e n o te s r e s e r v e d . R e g is te r s w it h n a m e s t y p e d in bold italic f o r m a t a r e R T L 8 0 2 9 A S d e fin e d r e g is te r s a n d a r e n o t s u p p o r te d in a s t a n d a r d N E 2 0 0 0 a d a p t e r .

LS009.0 1997.01.16 RTL8029AS Preliminary 1 1 Page 0 (PS1=0, PS0=0) No. Name Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 H C R R /W P S 1 P S 0 R D 2 R D 1 R D 0 T X P S T A S T P 0 1 H C L D A 0 R A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 P S T A R T W A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 0 2 H C L D A 1 R A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 P S T O P W A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 0 3 H B N R Y R /W A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 0 4 H T S R R O W C C D H 0 C R S A B T C O L - P T X T P S R W A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 0 5 H N C R R 0 0 0 0 N C 3 N C 2 N C 1 N C 0 T B C R 0 W T B C 7 T B C 6 T B C 5 T B C 4 T B C 3 T B C 2 T B C 1 T B C 0 0 6 H F I F O R D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 T B C R 1 W T B C 1 5 T B C 1 4 T B C 1 3 T B C 1 2 T B C 1 1 T B C 1 0 T B C 9 T B C 8 0 7 H I S R R /W R S T R D C C N T O V W T X E R X E P T X P R X 0 8 H C R D A 0 R A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 R S A R 0 W A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 0 9 H C R D A 1 R A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 R S A R 1 W A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8

0 A H 8 0 2 9 I D 0 R 0 1 0 1 0 0 0 0

R B C R 0 W R B C 7 R B C 6 R B C 5 R B C 4 R B C 3 R B C 2 R B C 1 R B C 0

0 B H 8 0 2 9 I D 1 R 0 1 0 0 0 0 1 1

R B C R 1 W R B C 1 5 R B C 1 4 R B C 1 3 R B C 1 2 R B C 1 1 R B C 1 0 R B C 9 R B C 8

0 C H R S R R D F R D I S P H Y M P A 0 F A E C R C P R X

R C R W - - M O N P R O A M A B A R S E P

0 D H C N T R 0 R C N T 7 C N T 6 C N T 5 C N T 4 C N T 3 C N T 2 C N T 1 C N T 0

T C R W - - - O F S T A T D L B 1 L B 0 C R C

0 E H C N T R 1 R C N T 7 C N T 6 C N T 5 C N T 4 C N T 3 C N T 2 C N T 1 C N T 0

D C R W - F T 1 F T 0 A R M L S L A S B O S W T S

0 F H C N T R 2 R C N T 7 C N T 6 C N T 5 C N T 4 C N T 3 C N T 2 C N T 1 C N T 0

I M R W - R D C E C N T E O V W E T X E E R X E E P T X E P R X E Page 1 (PS1=0, PS0=1) No. Name Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 H C R R /W P S 1 P S 0 R D 2 R D 1 R D 0 T X P S T A S T P 0 1 H P A R 0 R /W D A 7 D A 6 D A 5 D A 4 D A 3 D A 2 D A 1 D A 0 0 2 H P A R 1 R /W D A 1 5 D A 1 4 D A 1 3 D A 1 2 D A 1 1 D A 1 0 D A 9 D A 8 0 3 H P A R 2 R /W D A 2 3 D A 2 2 D A 2 1 D A 2 0 D A 1 9 D A 1 8 D A 1 7 D A 1 6 0 4 H P A R 3 R /W D A 3 1 D A 3 0 D A 2 9 D A 2 8 D A 2 7 D A 2 6 D A 2 5 D A 2 4 0 5 H P A R 4 R /W D A 3 9 D A 3 8 D A 3 7 D A 3 6 D A 3 5 D A 3 4 D A 3 3 D A 3 2 0 6 H P A R 5 R /W D A 4 7 D A 4 6 D A 4 5 D A 4 4 D A 4 3 D A 4 2 D A 4 1 D A 4 0 0 7 H C U R R R /W A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 0 8 H M A R 0 R /W F B 7 F B 6 F B 5 F B 4 F B 3 F B 2 F B 1 F B 0 0 9 H M A R 1 R /W F B 1 5 F B 1 4 F B 1 3 F B 1 2 F B 1 1 F B 1 0 F B 9 F B 8

0 A H M A R 2 R /W F B 2 3 F B 2 2 F B 2 1 F B 2 0 F B 1 9 F B 1 8 F B 1 7 F B 1 6

0 B H M A R 3 R /W F B 3 1 F B 3 0 F B 2 9 F B 2 8 F B 2 7 F B 2 6 F B 2 5 F B 2 4

0 C H M A R 4 R /W F B 3 9 F B 3 8 F B 3 7 F B 3 6 F B 3 5 F B 3 4 F B 3 3 F B 3 2

0 D H M A R 5 R /W F B 4 7 F B 4 6 F B 4 5 F B 4 4 F B 4 3 F B 4 2 F B 4 1 F B 4 0

0 E H M A R 6 R /W F B 5 5 F B 5 4 F B 5 3 F B 5 2 F B 5 1 F B 5 0 F B 4 9 F B 4 8

0 F H M A R 7 R /W F B 6 3 F B 6 2 F B 6 1 F B 6 0 F B 5 9 F B 5 8 F B 5 7 F B 5 6

LS009.0 1997.01.16 RTL8029AS Preliminary 1 2 Page 2(PS1=1, PS0=0) No. Name Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 H C R R /W P S 1 P S 0 R D 2 R D 1 R D 0 T X P S T A S T P 0 1 H P S T A R T R A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 0 2 H P S T O P R A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 0 3 H - 0 4 H T P S R R A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 0 5 H

0 B H

0 C H R C R R - - M O N P R O A M A B A R S E P

0 D H T C R R - - - O F S T A T D L B 1 L B 0 C R C

0 E H D C R R - F T 1 F T 0 A R M L S L A S B O S W T S

0 F H I M R R - R D C E C N T E O V W E T X E E R X E E P T X E P R X E

Page 3(PS1=1, PS0=1) No. Name Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 H C R R /W P S 1 P S 0 R D 2 R D 1 R D 0 T X P S T A S T P 0 1 H 9 3 4 6 C R R E E M 1 E E M 0 - - E E C S E E S K E E D I E E D O W E E M 1 E E M 0 - - E E C S E E S K E E D I - 0 2 H - 0 3 H C O N F I G 0 R - - - - - B N C 0 0 0 4 H - 0 5 H C O N F I G 2 R P L 1 P L 0 *FCE *PF - - B S 1 B S 0 W * P L 1 P L 0 *FCE - - - - - 0 6 H C O N F I G 3 R - F U D U P L E D S 1 L E D S 0 - S L E E P P W R D N - W * - *FUDUP - - - S L E E P P W R D N - 0 7 H T E S T 1 - R e s e r v e d 0 8 H - - U n u s e d 0 9 H H L T C L K W H L T 7 H L T 6 H L T 5 H L T 4 H L T 3 H L T 2 H L T 1 H L T 0

0 A H T E S T 2 - R e s e r v e d

0 B - 0 D H - - U n u s e d

*0EH 8029ASID0 R 0 0 1 0 1 0 0 1 *0FH 8029ASID1 R 1 0 0 0 0 0 0 0 N o te s : T h e r e g is te r s m a r k e d w ith ty p e = 'W * ' c a n b e w r it t e n o n ly if b it s E E M 1 = E E M 0 = 1 . Notes: "*" denotes the bits or registers which are RTL8029AS defined bits or registers and are not supported in RTL8029. 5.1.2. Register Functions 5.1.2.1. NE2000 Compatible Registers CR: Command Register (00H; Type=R/W) T h is r e g is te r is u s e d to s e le c t r e g is te r p a g e s , e n a b le o r d is a b le r e m o t e D M A o p e r a t io n a n d is s u e c o m m a n d s .

LS009.0 1997.01.16 RTL8029AS Preliminary 1 3 Bit Symbol Description 7 , 6 P S 1 , P S 0 PS1 PS0 Register Page Remark 0 0 0 N E 2 0 0 0 c o m p a tib le 0 1 1 N E 2 0 0 0 c o m p a tib le 1 0 2 N E 2 0 0 0 c o m p a tib le 1 1 3 R T L 8 0 2 9 A S C o n f ig u r a tio n 5 - 3 R D 2 - 0 RD2 RD1 RD0 Function 0 0 0 N o t a llo w e d 0 0 1 R e m o te R e a d 0 1 0 R e m o te W r ite 0 1 1 S e n d P a c k e t 1 * * A b o r t/C o m p le te r e m o te D M A 2 T X P T h is b it m u s t b e s e t to tr a n s m it a p a c k e t. I t is in te r n a lly r e s e t e ith e r a f te r th e tr a n s m is s io n is c o m p le te d o r a b o r te d . W r itin g a 0 h a s n o e f f e c t. 1 S T A T h e S T A b it c o n tr o ls n o th in g . I t o n ly r e f le c ts th e v a lu e w r itte n to th is b it. P O W E R U P = 0 . 0 S T P T h is b it is th e S T O P c o m m a n d . W h e n it is s e t, n o p a c k e ts w ill b e r e c e iv e d o r tr a n s m itte d . P O W E R U P = 1 . STA STP Function 1 0 S ta r t C o m m a n d 0 1 S to p C o m m a n d ISR: Interrupt Status Register (07H; Type=R/W in Page0) T h is r e g is te r r e fle c ts th e N I C s ta tu s . T h e h o s t r e a d s it t o d e t e r m in e t h e c a u s e o f a n in t e r r u p t . I n d iv id u a l b its a r e c le a r e d b y w r itin g a " 1 " in t o t h e c o r r e s p o n d in g b it . I t m u s t b e c le a r e d a f t e r p o w e r u p . Bit Symbol Description 7 R S T T h is b it is s e t w h e n N I C e n te r s r e s e t s ta te a n d is c le a r e d w h e n a s ta r t c o m m a n d is is s u e d to th e C R . I t is a ls o s e t w h e n r e c e iv e b u f f e r o v e r f lo w s a n d is c le a r e d w h e n o n e o r m o r e p a c k e ts h a v e b e e n r e a d f r o m th e b u f f e r . 6 R D C S e t w h e n r e m o te D M A o p e r a tio n h a s b e e n c o m p le te d . 5 C N T S e t w h e n M S B o f o n e o r m o r e o f th e n e tw o r k ta lly c o u n te r s h a s b e e n s e t. 4 O V W T h is b it is s e t w h e n th e r e c e iv e b u f f e r h a s b e e n e x h a u s te d . 3 T X E T r a n s m it e r r o r b it is s e t w h e n a p a c k e t tr a n s m is s io n is a b o r te d d u e to e x c e s s iv e c o llis io n s . 2 R X E T h is b it is s e t w h e n a p a c k e t r e c e iv e d w ith o n e o r m o r e o f th e f o llo w in g e r r o r s : - C R C e r r o r - F r a m e a lig n m e n t e r r o r - M is s e d p a c k e t 1 P T X T h is b it in d ic a te s p a c k e t tr a n s m itte d w ith n o e r r o r s . 0 P R X T h is b it in d ic a te s p a c k e t r e c e iv e d w ith n o e r r o r s .

LS009.0 1997.01.16 RTL8029AS Preliminary 1 4 IMR: Interrupt Mask Register (0FH; Type=W in Page0, Type=R in Page2) A ll b its c o r r e s p o n d to th e b its in th e I S R r e g is t e r . P O W E R U P = a ll 0 s . S e t t in g in d iv id u a l b it s w ill e n a b le th e c o r r e s p o n d in g in te r r u p t s . DCR: Data Configuration Register (0EH; Type=W in Page0, Type=R in Page2) Bit Symbol Description 7 - A lw a y s 1 6 , 5 F T 1 , F T 0 F I F O th r e s h o ld s e le c t b it 1 a n d 0 .

4 A R M A u to - in itia liz e R e m o te

0 : S e n d P a c k e t C o m m a n d n o t e x e c u te d . 1 : S e n d P a c k e t C o m m a n d e x e c u te d .

3 L S L o o p b a c k S e le c t

0 : L o o p b a c k m o d e s e le c te d . B its 1 a n d 2 o f th e T C R m u s t a ls o b e p r o g r a m m e d f o r L o o p b a c k o p e r a tio n . 1 : N o r m a l O p e r a tio n 2 L A S T h is b it m u s t b e s e t to z e r o . N I C o n ly s u p p o r ts d u a l 1 6 - b it D M A m o d e . P O W E R U P = 1

1 B O S B y te O r d e r S e le c t

0 : M S b y te p la c e d o n M D 1 5 - 8 a n d L S b y te o n M D 7 - 0 . ( 3 2 x x x ,8 0 x 8 6 ) 1 : M S b y te p la c e d o n M D 7 - 0 a n d L S b y te o n M D 1 5 - 8 . ( 6 8 0 x 0 )

0 W T S W o r d T r a n s f e r S e le c t

0 : b y te - w id e D M A tr a n s f e r 1 : w o r d - w id e D M A tr a n s f e r TCR: Transmit Configuration Register (0DH; Type=W in Page0, Type=R in Page2) Bit Symbol Description 7 - 5 - A lw a y s 1 . 4 O F S T C o llis io n O f f s e t E n a b le . 3 A T D A u to T r a n s m it D is a b le . 0 : n o r m a l o p e r a tio n 1 : r e c e p tio n o f m u ltic a s t a d d r e s s h a s h in g to b it 6 2 d is a b le s tr a n s m itte r , r e c e p tio n o f m u ltic a s t a d d r e s s h a s h in g to b it 6 3 e n a b le s tr a n s m itte r . 2 , 1 L B 1 , L B 0 LB1 LB0 Mode Remark 0 0 0 N o r m a l O p e r a tio n 0 1 1 I n te r n a l L o o p b a c k 1 0 2 E x te r n a l L o o p b a c k 1 1 3 E x te r n a l L o o p b a c k 0 C R C T h e N I C C R C lo g ic c o m p r is e s a C R C g e n e r a to r f o r tr a n s m itte r a n d a C R C c h e c k e r f o r r e c e iv e r . T h is b it c o n tr o ls th e a c tiv ity o f th e C R C lo g ic . I f th is b it s e t, C R C is in h ib ite d b y tr a n s m itte r . O th e r w is e C R C is a p p e n d e d b y tr a n s m itte r . Conditions CRC Logic Activities CRC Bit Mode CRC Generator CRC Checker 0 n o r m a l e n a b le d e n a b le d 1 n o r m a l d is a b le d e n a b le d 0 lo o p b a c k e n a b le d d is a b le d 1 lo o p b a c k d is a b le d e n a b le d

LS009.0 1997.01.16 RTL8029AS Preliminary 1 5 TSR: Transmit Status Register (04H; Type=R in Page0) T h is r e g is te r in d ic a te s th e s ta tu s o f a p a c k e t t r a n s m is s io n . Bit Symbol Description 7 O W C O u t o f W in d o w C o llis io n . I t is s e t w h e n a c o llis io n is d e te c te d a f te r a s lo t tim e ( 5 1 .2 u s ) . T r a n s m is s io n s a r e r e s c h e d u le d a s in n o r m a l c o llis io n s . 6 C D H C D H e a r tb e a t. T h e N I C w a tc h e s f o r a c o llis io n s ig n a l ( i.e ., C D H e a r tb e a t s ig n a l) d u r in g th e f ir s t 6 .4 u s o f th e in te r f r a m e g a p f o llo w in g a tr a n s m is s io n . T h is b it is s e t if th e tr a n s c e iv e r f a ils to s e n d th is s ig n a l. 5 - A lw a y s 0 . 4 C R S C a r r ie r S e n s e lo s t b it is s e t w h e n th e c a r r ie r is lo s t d u r in g tr a n s m ittin g a p a c k e t. 3 A B T I t in d ic a te s th e N I C a b o r te d th e tr a n s m is s io n b e c a u s e o f e x c e s s iv e c o llis io n s . 2 C O L I t in d ic a te s th e tr a n s m is s io n c o llid e d w ith s o m e o th e r s ta tio n o n th e n e tw o r k . 1 - A lw a y s 1 . 0 P T X T h is b it in d ic a te s th e tr a n s m is s io n c o m p le te s w ith n o e r r o r s . RCR: Receive Configuration Register (0CH; Type=W in Page0, Type=R in Page2) Bit Symbol Description 7 , 6 - A lw a y s 1 . 5 M O N W h e n m o n ito r m o d e b it is s e t, r e c e iv e d p a c k e ts a r e c h e c k e d f o r a d d r e s s m a tc h , g o o d C R C a n d f r a m e a lig n m e n t b u t n o t b u f f e r e d to m e m o r y . O th e r w is e , p a c k e ts w ill b e b u f f e r e d to m e m o r y . 4 P R O I f P R O = 1 , a ll p a c k e ts w ith p h y s ic a l d e s tin a tio n a d d r e s s a c c e p te d . I f P R O = 0 , p h y s ic a l d e s tin a tio n a d d r e s s m u s t m a tc h th e n o d e a d d r e s s p r o g r a m m e d in P A R 0 - 5 . 3 A M I f A M = 1 , p a c k e ts w ith m u ltic a s t d e s tin a tio n a d d r e s s a r e a c c e p te d . I f A M = 0 , p a c k e ts w ith m u ltic a s t d e s tin a tio n a d d r e s s a r e r e je c te d . 2 A B I f A B = 1 , p a c k e ts w ith b r o a d c a s t d e s tin a tio n a d d r e s s a r e a c c e p te d . I f A B = 0 , p a c k e ts w ith b r o a d c a s t d e s tin a tio n a d d r e s s a r e r e je c te d . 1 A R I f A R = 1 , p a c k e ts w ith le n g th f e w e r th a n 6 4 b y te s a r e a c c e p te d . I f A R = 0 , p a c k e ts w ith le n g th f e w e r th a n 6 4 b y te s a r e r e je c te d . 0 S E P I f S E P = 1 , p a c k e ts w ith r e c e iv e e r r o r s a r e a c c e p te d . I f S E P = 0 , p a c k e ts w ith r e c e iv e e r r o r s a r e r e je c te d . RSR: Receive Status Register (0CH; Type=R in Page0) Bit Symbol Description 7 D F R D e f e r r in g . S e t w h e n a c a r r ie r o r a c o llis io n is d e te c te d . 6 D I S R e c e iv e r D is a b le d . W h e n th e N I C e n te r s th e m o n ito r m o d e , th is b it is s e t a n d r e c e iv e r is d is a b le d . R e s e t w h e n r e c e iv e r is e n a b le d a f te r le a v in g th e m o n ito r m o d e . 5 P H Y P H Y b it is s e t w h e n th e r e c e iv e d p a c k e t h a s a m u ltic a s t o r b r o a d c a s t d e s tin a tio n a d d r e s s . I t is r e s e t w h e n th e r e c e iv e d p a c k e t h a s a p h y s ic a l d e s tin a tio n a d d r e s s . 4 M P A M is s e d P a c k e t b it is s e t w h e n th e in c o m in g p a c k e t c a n n o t b e a c c e p te d b y N I C b e c a u s e o f a la c k o f r e c e iv e b u f f e r o r if N I C is in m o n ito r m o d e . I n c r e m e n t C N T R 2 ta lly c o u n te r . 3 - A lw a y s 0 . 2 F A E F r a m e A lig n m e n t E r r o r b it r e f le c ts th e in c o m in g p a c k e t d id n 't e n d o n a b y te b o u n d a r y a n d C R C d id n o t m a tc h a t la s t b y te b o u n d a r y . I n c r e m e n t C N T R 0 ta lly c o u n te r .

LS009.0 1997.01.16 RTL8029AS Preliminary 1 6 1 C R C C R C e r r o r b it r e f le c ts p a c k e t r e c e iv e d w ith C R C e r r o r . T h is b it w ill a ls o b e s e t f o r F A E e r r o r s . I n c r e m e n t C N T R 1 ta lly c o u n te r . 0 P R X T h is b it in d ic a te s p a c k e t r e c e iv e d w ith n o e r r o r s . CLDA0,1: Current Local DMA Registers (01H & 02H; Type=R in Page0) T h e s e tw o r e g is te r s c a n b e r e a d t o g e t t h e c u r r e n t lo c a l D M A a d d r e s s . PSTART: Page Start Register (01H; Type=W in Page0, Type=R in Page 2) T h e P a g e S ta r t r e g is te r s e ts th e s t a r t p a g e a d d r e s s o f t h e r e c e iv e b u f f e r r in g . PSTOP: Page Stop Register (02H; Type=W in Page0, Type=R in Page2) T h e P a g e S to p r e g is te r s e ts th e s t o p p a g e a d d r e s s o f t h e r e c e iv e b u f f e r r in g . BNRY: Boundary Register (03H; Type=R/W in Page0) T h is r e g is te r is u s e d to p r e v e n t o v e r w r it e o f t h e r e c e iv e b u f f e r r in g . I t is t y p ic a lly u s e d a s a p o in te r in d ic a tin g th e la s t r e c e iv e b u f f e r p a g e t h e h o s t h a s r e a d . TPSR: Transmit Page Start Register (04H; Type=W in Page0) T h is r e g is te r s e ts th e s ta r t p a g e a d d r e s s o f t h e p a c k e t t o t h e t r a n s m it t e d . TBCR0,1: Transmit Byte Count Registers (05H & 06H; Type=W in Page0) T h e s e tw o r e g is te r s s e t th e b y t e c o u n t s o f t h e p a c k e t t o b e t r a n s m it t e d . NCR: Number of Collisions Register (05H; Type=R in Page0) T h e r e g is te r r e c o r d s th e n u m b e r o f c o llis io n s a n o d e e x p e r ie n c e s d u r in g a p a c k e t tr a n s m is s io n . FIFO: First In First Out Register (06H; Type=R in Page0) T h is r e g is te r a llo w s th e h o s t to e x a m in e t h e c o n t e n t s o f t h e F I F O a f t e r lo o p b a c k . CRDA0,1: Current Remote DMA Address registers (08H & 09H; Type=R in Page0) T h e s e tw o r e g is te r s c o n ta in th e c u r r e n t a d d r e s s o f r e m o t e D M A . RSAR0,1: Remote Start Address Registers (08H & 09H; Type=W in Page0) T h e s e tw o r e g is te r s s e t th e s ta r t a d d r e s s o f r e m o t e D M A . RBCR0,1: Remote Byte Count Registers (0AH & 0BH; Type=W in Page0) T h e s e tw o r e g is te r s s e t th e d a t a b y t e c o u n t s o f r e m o t e D M A . CNTR0: Frame Alignment Error Tally Counter Register (0DH; Type=R in Page0)

LS009.0 1997.01.16 RTL8029AS Preliminary 1 7 CNTR1: CRC Error Tally Counter Register (0EH; Type=R in Page0) CNTR2: Missed Packet Tally Counter Register (0FH; Type=R in Page0) PAR0-5: Physical Address Registers (01H - 06H; Type=R/W in Page1) T h e s e r e g is te r s c o n ta in m y E t h e r n e t n o d e a d d r e s s a n d a r e u s e d t o c o m p a r e t h e d e s tin a tio n a d d r e s s o f in c o m in g p a c k e t s f o r a c c e p t a t io n o r r e je c t io n . CURR: Current Page Register (07H; Type=R/W in Page1) T h is r e g is te r p o in ts to th e p a g e a d d r e s s o f t h e f ir s t r e c e iv e b u f f e r p a g e t o b e u s e d f o r a p a c k e t r e c e p tio n . MAR0-7: Multicast Address Register (08H - 0FH; Type=R/W in Page1) T h e s e r e g is te r s p r o v id e filte r in g b it s o f m u lt ic a s t a d d r e s s e s h a s h e d b y t h e C R C lo g ic . 5.1.2.2. RTL8029AS Defined Registers Page 0 (PS1=0, PS0=0) T w o r e g is te r s a r e d e fin e d to c o n ta in th e R T L 8 0 2 9 A S c h ip I D a n d R e a d S e q u e n c e C o m m a n d is N O L O N G E R s u p p o r te d in R T L 8 0 2 9 A S . No. Name Type Bit7-0

0 A H 8 0 2 9 I D 0 R 5 0 H ( A S C I I c o d e o f " P " )

0 B H 8 0 2 9 I D 1 R 4 3 H ( A S C I I c o d e o f " C " )

Page 3(PS1=1, PS0=1) Page3 Power Up Values before loading 9346 contents No. Name Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 H C R R /W 0 0 1 0 0 0 0 1 0 1 H 9 3 4 6 C R R /W 0 0 - - * * * * 0 2 H - 0 3 H C O N F I G 0 R - - - - - * 0 0 0 4 H - 0 5 H C O N F I G 2 R /W * * * 0 0 - - * * 0 6 H C O N F I G 3 R /W * - * * * - 0 0 - 0 7 H - 0 8 H - 0 9 H H L T C L K W 1 1 1 1 1 1 1 1

0 A H -

0 B H -

0 C H -

0 D H -

0EH 8029ASID0 R 0 0 1 0 1 0 0 1 0FH 8029ASID1 R 1 0 0 0 0 0 0 0

LS009.0 1997.01.16 RTL8029AS Preliminary 1 8 Page3 Content Descriptions 9346CR: 9346 Command Register (01H; Type=R/W except Bit0=R) Bit Symbol Description 7 - 6 E E M 1 - 0 T h e s e 2 b its s e le c t th e R T L 8 0 2 9 A S o p e r a tin g m o d e . EEM1 EEM0 Operating Mode 0 0 N o r m a l ( D P 8 3 9 0 c o m p a tib le ) 0 1 A u to - lo a d : E n te r in g th is m o d e w ill m a k e th e R T L 8 0 2 9 A S lo a d th e c o n te n ts o f 9 3 4 6 lik e w h e n th e R S T B s ig n a l is a s s e r te d . T h is a u to - lo a d o p e r a tio n w ill ta k e a b o u t 2 m s . A f te r it is c o m p le te d , th e R T L 8 0 2 9 A S g o e s b a c k to th e n o r m a l m o d e a u to m a tic a lly ( E E M 1 = E E M 0 = 0 ) a n d th e C R r e g is te r is r e s e t to 2 1 H . 1 0 9 3 4 6 p r o g r a m m in g : I n th is m o d e , b o th th e lo c a l & r e m o te D M A o p e r a tio n s o f 8 3 9 0 a r e d is a b le d . T h e 9 3 4 6 c a n b e d ir e c tly a c c e s s e d v ia b it3 - 0 w h ic h n o w r e f le c t th e s ta te s o f E E C S , E E S K , E E D I , & E E D O p in s r e s p e c tiv e ly . 1 1 C o n f ig r e g is te r w r ite e n a b le : B e f o r e w r itin g to th e P a g e 3 C O N F I G 2 ,3 r e g is te r s , th e R T L 8 0 2 9 A S m u s t b e p la c e d in th is m o d e . T h is w ill p r e v e n t R T L 8 0 2 9 A S 's c o n f ig u r a tio n s f r o m a c c id e n ta l c h a n g e . 5 - 4 - N o t u s e d . 3 E E C S T h e s e b its r e f le c t th e s ta te o f E E C S , E E S K , E E D I & E E D O p in s in a u to - lo a d o r 2 E E S K 9 3 4 6 p r o g r a m m in g m o d e .

1 E E D I

0 E E D O

CONFIG0: RTL8029AS Configuration Register 0 (03H; Type=R) Bit Symbol Description 7 - 3 - N o t u s e d 2 B N C W h e n s e t, th is b it in d ic a te s th a t th e R T L 8 0 2 9 A S is u s in g th e 1 0 B a s e 2 th in c a b le a s its n e tw o r k in g m e d iu m . T h is b it w ill b e s e t in th e f o llo w in g 2 c a s e s : ( 1 ) P L 1 = P L 0 = 0 ( a u to - d e te c t) a n d lin k te s t f a ils ( 2 ) P L 1 = P L 0 = 1 ( 1 0 B a s e 2 ) 1 - 0 - A lw a y s 0 s . CONFIG1: Reserved CONFIG2: RTL8029AS Configuration Register 2 (05H; Type=R except Bit[7:5]=R/W) Bit Symbol Description 7 - 6 P L 1 - 0 S e le c t n e tw o r k m e d iu m ty p e s .

LS009.0 1997.01.16 RTL8029AS Preliminary 1 9 PL1 PL0 Medium Type 0 0 T P /C X a u to - d e te c t ( 1 0 B a s e T lin k te s t is e n a b le d ) 0 1 1 0 B a s e T w ith lin k te s t d is a b le d 1 0 1 0 B a s e 5 1 1 1 0 B a s e 2

5 FCE Flow Control Enable: The flow control is enabled in full-duplex mode

only.

4 PF Pause Flag: Set when RTL8029AS is in backoff state because a pause

packet is received. 3 - 2 - N o t u s e d 1 - 0 B S 1 - 0 S e le c t B o o t R O M s iz e BS1 BS0 BROM size 0 0 N o B o o t R O M 0 1 8 K B o o t R O M 1 0 1 6 K B o o t R O M 1 1 3 2 K B o o t R O M CONFIG3: RTL8029AS Configuration Register 3 (06H; Type=R except Bit[6,2:1]=R/W) Bit Symbol Description 7 - U n u s e d 6 F U D U P W h e n th is b it is s e t, R T L 8 0 2 9 A S is s e t to th e f u ll- d u p le x m o d e w h ic h e n a b le s s im u lta n e o u s ly tr a n s m is s io n a n d r e c e p tio n o n th e tw is te d - p a ir lin k to a f u ll- d u p le x E th e r n e t s w itc h in g h u b . T h is f e a tu r e n o t o n ly in c r e a s e s th e c h a n n e l b a n d w id th f r o m 1 0 to 2 0 M b p s b u t a ls o a v o id s th e p e r f o r m a n c e d e g r a d in g p r o b le m d u e to th e c h a n n e l c o n te n tio n c h a r a c te r is tic s o f th e E th e r n e t C S M A /C D p r o to c o l. 5 - 4 L E D S 1 - 0 T h e s e tw o b its s e le c t th e o u tp u ts to L E D 2 - 0 p in s . LEDS0 LED0 Pin

0 L E D _ C O L

1 L E D _ L I N K

0 L E D _ R X L E D _ T X

1 L E D _ C R S M C S B

P le a s e r e f e r to s e c tio n 6 .4 f o r th e b e h a v io r o f L E D s . T h e M C S B s ig n a l is d e f in e d to p u t th e lo c a l b u f f e r S R A M in to s ta n d b y m o d e w h ile D M A is n o t in p r o g r e s s a n d th u s s a v e s p o w e r s . 3 - R e s e r v e d . Must not w r ite a 1 to th is b it. 2 S L E E P T h is b it, w h e n s e t, p u ts R T L 8 0 2 9 A S in to s le e p m o d e . I n s le e p m o d e , a ll L E D s ig n a ls ( P .S . M C S B is n o t a n L E D s ig n a l) e x c e p t L E D _ B N C a r e f o r c e d h ig h to tu r n o f f th e L E D s . T h e R T L 8 0 2 9 A S s till h a n d le s th e n e tw o r k tr a n s m is s io n a n d r e c e p tio n lik e in n o r m a l m o d e . T h e L E D _ B N C is n o t a f f e c te d b y th is b it. T h is b it's p o w e r - u p in itia l v a lu e is 0 a n d c a n b e m o d if ie d b y s o f tw a r e w h e n E E M 1 = E E M 0 = 1 .

LS009.0 1997.01.16 RTL8029AS Preliminary 2 0 1 P W R D N T h is b it, w h e n s e t, p u ts R T L 8 0 2 9 A S in to p o w e r d o w n m o d e . R T L 8 0 2 9 A S s u p p o r ts tw o k in d s o f p o w e r d o w n m o d e s , w h ic h is s e le c te d b y th e c o n te n ts o f th e H L T C L K r e g is te r : ( 1 ) m o d e 1 : p o w e r d o w n w ith c lo c k r u n n in g ( 2 ) m o d e 2 : p o w e r d o w n w ith c lo c k h a lte d I n b o th p o w e r d o w n m o d e s , th e R T L 8 0 2 9 A S 's s e r ia l n e tw o r k in te r f a c e a n d tr a n s c e iv e r a r e tu r n e d o f f . A ll n e tw o r k a c tiv itie s a r e ig n o r e d . A ll L E D s ig n a ls e x c e p t L E D _ B N C a r e f o r c e d h ig h . T h e L E D _ B N C is f o r c e d lo w to d is a b le th e D C c o n v e r te r f o r c o a x ia l tr a n s c e iv e r . I n p o w e r d o w n m o d e 2 , th e R T L 8 0 2 9 A S s to p s its in te r n a l c lo c k f o r m in im a l p o w e r c o n s u m p tio n . R e g is te r s e x c e p t H L T C L K a r e ty p ic a lly n o t a c c e s s ib le in th is m o d e . T h is b it's in itia l v a lu e c o m e s f r o m 9 3 4 6 a n d c a n b e m o d if ie d if E E M 1 = E E M 0 = 1 in 9 3 4 6 C R r e g is te r . 0 - U n u s e d HLTCLK: Halt Clock Register (09H; Type=W) T h is is th e o n ly a c tiv e o n e o f G r o u p 1 r e g is t e r s w h e n R T L 8 0 2 9 A S is in a c t iv a t e d . W r it in g t o t h is r e g is te r is in v a lid if R T L 8 0 2 9 A S is n o t in p o w e r d o w n m o d e . ( i.e ., I f P W R D N b it in C O N F I G 3 r e g is te r is z e r o .) T h e d a ta w r itte n to th is r e g is t e r d e t e r m in e s t h e R T L 8 0 2 9 A S 's p o w e r d o w n m o d e . Data Power Down Mode 5 2 H ( A S C I I c o d e o f 'R ') M o d e 1 - c lo c k Ru n n in g 4 8 H ( A S C I I c o d e o f 'H ') M o d e 2 - c lo c k Ha lte d O th e r v a lu e s I g n o r e d 8029ASID0,1: RTL8029AS ID = 8029H (0E,0FH; Type=R) 5.2. Group 2: PCI Configuration Space Registers 5.2.1. PCI Configuration Space Table No. Name Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 H V I D R V I D 7 V I D 6 V I D 5 V I D 4 V I D 3 V I D 2 V I D 1 V I D 0 0 1 H R V I D 1 5 V I D 1 4 V I D 1 3 V I D 1 2 V I D 1 1 V I D 1 0 V I D 9 V I D 8 0 2 H D I D R D I D 7 D I D 6 D I D 5 D I D 4 D I D 3 D I D 2 D I D 1 D I D 0 0 3 H R D I D 1 5 D I D 1 4 D I D 1 3 D I D 1 2 D I D 1 1 D I D 1 0 D I D 9 D I D 8 0 4 H C o m m a n d R 0 0 0 0 0 0 M E M E N I O E N W - - - - - - M E M E N I O E N 0 5 H R 0 0 0 0 0 0 0 0 W - - - - - - - - 0 6 H S ta tu s R 0 0 0 0 0 0 0 0 0 7 H R 0 0 0 0 0 D S T 1 D S T 0 0 0 8 H R I D R 0 0 0 0 0 0 0 0 0 9 H P I F R R 0 0 0 0 0 0 0 0

0 A H S C R R 0 0 0 0 0 0 0 0

0 B H B C R R 0 0 0 0 0 0 1 0

0 C H - R e s e r v e d

LS009.0 1997.01.16 RTL8029AS Preliminary 2 1

0 D H L T R R 0 0 0 0 0 0 0 0

0 E H H T R R 0 0 0 0 0 0 0 0

0 F H - R e s e r v e d

1 0 H B A R R B A R 7 B A R 6 B A R 5 0 0 0 0 I O I N W B A R 7 B A R 6 B A R 5 - - - - - 1 1 H R /W B A R 1 5 B A R 1 4 B A R 1 3 B A R 1 2 B A R 1 1 B A R 1 0 B A R 9 B A R 8 1 2 H R /W B A R 2 3 B A R 2 2 B A R 2 1 B A R 2 0 B A R 1 9 B A R 1 8 B A R 1 7 B A R 1 6 1 3 H R /W B A R 3 1 B A R 3 0 B A R 2 9 B A R 2 8 B A R 2 7 B A R 2 6 B A R 2 5 B A R 2 4 1 4 H

2 B H

• R e s e r v e d 2CH SVID R SVID7 SVID6 SVID5 SVID4 SVID3 SVID2 SVID1 SVID0 2DH R SVID15 SVID14 SVID13 SVID12 SVID11 SVID10 SVID9 SVID8 2EH SID R SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 2FH R SID15 SID14 SID13 SID12 SID11 SID10 SID9 SID8 3 0 H B R O M B A R R 0 0 0 0 0 0 0 B R O M E N W - - - - - - - B R O M E N 3 1 H R B M R 1 5 B M R 1 4 B M R 1 3 B M R 1 2 B M R 1 1 0 0 0 W B M R 1 5 B M R 1 4 B M R 1 3 B M R 1 2 B M R 1 1 - - - 3 2 H R /W B M R 2 3 B M R 2 2 B M R 2 1 B M R 2 0 B M R 1 9 B M R 1 8 B M R 1 7 B M R 1 6 3 3 H R /W B M R 3 1 B M R 3 0 B M R 2 9 B M R 2 8 B M R 2 7 B M R 2 6 B M R 2 5 B M R 2 4 3 4 H

3 B H

• R e s e r v e d

3 C H I L R R - - - - I L R 3 I L R 2 I L R 1 I L R 0

W - - - - I L R 3 I L R 2 I L R 1 I L R 0

3 D H I P R R 0 0 0 0 0 0 0 1

3 E H

• R e s e r v e d 5.2.2. PCI Configuration Space functions T h e P C I c o n fig u r a tio n s p a c e is in te n d e d f o r c o n f ig u r a t io n , in it ia liz a t io n , a n d c a t a s t r o p h ic e r r o r h a n d lin g fu n c tio n s . T h e fu n c tio n s o f R T L 8 0 2 9 A S 's c o n f ig u r a t io n s p a c e a r e d e s c r ib e d b e lo w . VID: Vendor ID Register (01-00H; Type=R) T h e V e n d o r I D r e g is te r is a 1 6 - b it r e g is t e r t h a t id e n t if ie s t h e m a n u f a c t u r e r o f t h e R T L 8 0 2 9 A S c o n tr o lle r . R e a lte k V e n d o r I D = 1 0 E C H ( d e f a u lt v a lu e ) DID: Device ID Register (03-02H; Type=R) T h e D e v ic e I D r e g is te r is a 1 6 - b it r e g is te r t h a t s h o w s t h e d e v ic e I D o f t h e R T L 8 0 2 9 A S c o n t r o lle r . R T L 8 0 2 9 A S D e v ic e I D = 8 0 2 9 H ( d e fa u lt v a lu e )

LS009.0 1997.01.16 RTL8029AS Preliminary 2 2 Command: Command Register (05-04H; Type=R except Bit1, 0=R/W) T h e C o m m a n d r e g is te r is a 1 6 - b it r e g is te r u s e d t o p r o v id e c o a r s e c o n t r o l o v e r a d e v ic e 's a b ility t o g e n e r a te a n d r e s p o n d to P C I c y c le s . Bit Symbol Description 1 5 - 1 0 - R e s e r v e d a r e a . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 9 F B T B E N F a s t B a c k - T o - B a c k E N a b le . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. T h e R T L 8 0 2 9 A S w ill n o t g e n e r a te F a s t B a c k - to - B a c k c y c le s . 8 S E R R E N S E R R E N a b le . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 7 A D S T E P A d d r e s s /D a ta S T E P p in g . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. T h e R T L 8 0 2 9 A S n e v e r d o a d d r e s s /d a ta s te p p in g . 6 P E R R E N T h is b it c o n tr o ls th e d e v ic e 's r e s p o n s e to p a r ity e r r o r s . W h e n th e v a lu e o f th is b it is 0 , th e d e v ic e m u s t ig n o r e a n y p a r ity e r r o r s th a t it d e te c ts a n d c o n tin u e s n o r m a l o p e r a tio n . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 5 V G A S N O O P V G A p a le tte S N O O P . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 4 M W I E N M e m o r y W r ite a n d I n v a lid a te c y c le E N a b le . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 3 S C Y C E N S p e c ia l C Y C le E N a b le . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. T h e R T L 8 0 2 9 A S ig n o r e s a ll s p e c ia l c y c le o p e r a tio n . 2 B M E N B u s M a s te r E N a b le . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 1 M E M E N C o n tr o ls a d e v ic e 's r e s p o n s e to m e m o r y s p a c e a c c e s s e s . 0 : D is a b le th e d e v ic e r e s p o n s e 1 : E n a b le th e d e v ic e r e s p o n s e 0 I O E N C o n tr o ls a d e v ic e 's r e s p o n s e to I /O s p a c e a c c e s s e s . 0 : D is a b le th e d e v ic e r e s p o n s e 1 : E n a b le th e d e v ic e r e s p o n s e Status: Status Register (07-06H; Type=R) T h e S ta tu s r e g is te r is a 1 6 - b it r e g is te r u s e d t o r e c o r d s t a t u s in f o r m a t io n f o r P C I b u s r e la t e d e v e n t s . R e a d s to th is r e g is te r b e h a v e n o r m a lly . W r it e s a r e s lig h t ly d if f e r e n t in t h a t b it s c a n b e r e s e t , b u t n o t s e t. Bit Symbol Description 1 5 D P E D e te c te d P a r ity E r r o r . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 1 4 S S E S ig n a le d S y s te m E r r o r . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 1 3 R M A R e c e iv e d M a s te r A b o r t. R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 1 2 R T A R e c e iv e d T a r g e t A b o r t. R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 1 1 S T A S ig n a le d T a r g e t A b o r t. R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 1 0 - 9 D S T 1 - 0 T h e s e b its e n c o d e th e tim in g o f D E V S E L B . T h e y a r e s e t to 0 1 b ( m e d iu m ) , in d ic a tin g th e R T L 8 0 2 9 A S c o n tr o lle r w ill a s s e r t D E V S E L B tw o c lo c k s a f te r F R A M E B is a s s e r te d . 8 D P D D a ta P a r ity D e te c te d . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 7 F B B C F a s t B a c k - to - B a c k C a p a b le . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 6 - 0 - R e s e r v e d a r e a . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. RID: Revision ID Register (08H; Type=R) T h e R e v is io n I D r e g is te r is a n 8 - b it r e g is t e r t h a t s p e c if ie s t h e R T L 8 0 2 9 A S c o n t r o lle r r e v is io n n u m b e r . R e v is io n I D = 0 0 H

LS009.0 1997.01.16 RTL8029AS Preliminary 2 3 PIFR: Programming InterFace Register (09H; Type=R) T h e P r o g r a m m in g in te r fa c e r e g is te r is a n 8 - b it r e g is t e r t h a t id e n t if ie s t h e p r o g r a m m in g in t e r f a c e o f R T L 8 0 2 9 A S c o n tr o lle r . P C I d o e s n 't d e fin e a n y o t h e r s p e c if ic r e g is t e r le v e l p r o g r a m m in g in t e r f a c e f o r n e tw o r k d e v ic e s . S o P I F R = 0 0 H . SCR: Sub-Class Register (0AH; Type=R) T h e S u b - c la s s r e g is te r is a n 8 - b it r e g is te r t h a t id e n t if ie s s p e c ia lly t h e f u n c t io n o f t h e R T L 8 0 2 9 A S c o n tr o lle r . S C R = 0 0 H in d ic a te s th a t th e R T L 8 0 2 9 A S c o n t r o lle r is a n E t h e r n e t c o n t r o lle r . BCR: Base-Class Register (0BH; Type=R) T h e B a s e - c la s s r e g is te r is a n 8 - b it r e g is te r t h a t b r o a d ly c la s s if ie s t h e f u n c t io n o f t h e R T L 8 0 2 9 A S c o n tr o lle r . B C R = 0 2 H in d ic a te s th a t th e R T L 8 0 2 9 A S c o n t r o lle r is a n e t w o r k c o n t r o lle r . HTR: Header Type Register (0EH; Type=R) T h e h e a d e r ty p e r e g is te r is a n 8 - b it r e g is te r t h a t d e s c r ib e s t h e la y o u t o f b y t e s 1 0 H t h r o u g h 3 F H in c o n fig u r a tio n s p a c e a n d a ls o w h e th e r o r n o t t h e d e v ic e c o n t a in s m u lt ip le f u n c t io n s . H T R = 0 0 H Bit Symbol Description 7 F U N C s in g le /m u lti F U N C tio n . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 0 : s in g le f u n c tio n d e v ic e 1 : m u ltip le f u n c tio n s d e v ic e T h e R T L 8 0 2 9 A S c o n tr o lle r is a s in g le f u n c tio n d e v ic e 6 - 0 L A Y O U T P C I c o n f ig u r a tio n s p a c e la y o u t. T h e s e b its s p e c if y th e la y o u t o f b y te s 1 0 H th r o u g h 3 F H . O n e e n c o d in g , 0 0 H is d e f in e d a n d s p e c if ie s th e la y o u t s h o w in s e c tio n 5 .2 .1 . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. LTR: Latency Timer Register (0DH; Type=R) T h is r e g is te r is a n 8 - b it r e g is te r . L T R = 0 0 H in d ic a t e s w h e n t h e R T L 8 0 2 9 A S c o n t r o lle r is p r e e m p te d , it w ill r e le a s e th e b u s im m e d ia t e ly a f t e r f in is h in g t h e c u r r e n t d a t a t r a n s f e r . BAR: Base Address Register (13-10H; Type=R/W except Bit4-0=R) T h e B a s e A d d r e s s r e g is te r is a 3 2 - b it r e g is t e r t h a t d e t e r m in e s t h e I /O s p a c e m a p p in g o f t h e R T L 8 0 2 9 A S c o n tr o lle r . Bit Symbol Description 3 1 - 5 B A R 3 1 - 5 T h e s e b its a r e u s e d to s e t I /O b a s e a d d r e s s f o r I /O o p e r a tio n . 4 - 2 I O S I Z E T h e s e b its in d ic a te h o w m a n y I /O s p a c e s to b e u s e d . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 1 - R e s e r v e d a r e a . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 0 I O I N I /O s p a c e I N d ic a to r . R e a d a s 1 , w r ite o p e r a tio n h a s n o e f f e c t. I n d ic a tin g th a t th e b a s e a d d r e s s is a n I /O b a s e a d d r e s s .

LS009.0 1997.01.16 RTL8029AS Preliminary 2 4 SVID: Subsystem Vendor ID Register (2C-2DH; Type=R) T h e S u b s y s te m V e n d o r ID r e g is te r is a 1 6 - b it r e g is te r th a t u n iq u e ly id e n tifie s th e a d d - in b o a r d o r s u b s y s te m w h e r e th e P C I d e v ic e r e s id e s . T h e d e fa u lt v a lu e is 10ECH . SID: Subsystem ID Register (2E-2FH; Type=R) T h e S u b s y s te m ID r e g is te r is a 1 6 - b it r e g is te r th a t a r e v e n d o r s p e c ific . T h e d e fa u lt v a lu e is 8029H . BROMBAR: Boot ROM Base Address Register (33-30H; Type=R/W except Bit12-1=R) T h e B a s e B o o t R O M A d d r e s s r e g is te r is a 3 2 - b it r e g is t e r t h a t d e t e r m in e s t h e B o o t R O M s p a c e m a p p in g o f th e R T L 8 0 2 9 A S c o n tr o lle r . Bit Symbol Description 3 1 - 1 5 B M R 3 1 - 1 5 T h e s e b its a r e u s e d to s e t B o o t R O M b a s e a d d r e s s f o r B o o t R O M a c c e s s . 1 4 - 1 1 B R O M S I Z E T h e s e b its in d ic a te h o w m a n y B o o t R O M s p a c e s to b e s u p p o r te d . BS1 BS0 Description 0 0 N o B R O M : B R O M E N = 0 ( R ) B M R 1 1 ,1 2 = 0 ,0 ( R ) 0 1 8 K B R O M : B R O M E N = 0 ( R /W ) B M R 1 1 ,1 2 = 0 ,0 ( R ) B M R 1 3 = 0 ( R /W ) B M R 1 4 = 0 ( R /W ) 1 0 1 6 K B R O M : B R O M E N = 0 ( R /W ) B M R 1 1 ,1 2 = 0 ,0 ( R ) B M R 1 3 = 0 ( R ) B M R 1 4 = 0 ( R /W ) 1 1 3 2 K B R O M : B R O M E N = 0 ( R /W ) B M R 1 1 ,1 2 = 0 ,0 ( R ) B M R 1 3 = 0 ( R ) B M R 1 4 = 0 ( R ) 1 0 - 1 - R e s e r v e d a r e a . R e a d a s 0 , w r ite o p e r a tio n h a s n o e f f e c t. 0 B R O M E N B R O M E N a b le b it. 0 : d is a b le 1 : e n a b le ILR: Interrupt Line Register (3CH; Type=R/W) T h e I n te r r u p t L in e r e g is te r is a n 8 - b it r e g is t e r u s e d t o c o m m u n ic a t e w it h t h e r o u t in g o f t h e in te r r u p t. I t is w r itte n b y th e P O S T s o ftw a r e t o s e t in t e r r u p t lin e f o r t h e R T L 8 0 2 9 A S c o n t r o lle r . I L R = 0 0 - 0 F H IPR: Interrupt Pin Register (3DH; Type=R) T h e I n te r r u p t P in r e g is te r is a n 8 - b it r e g is t e r in d ic a t in g t h e in t e r r u p t p in u s e d b y t h e R T L 8 0 2 9 A S c o n tr o lle r . T h e R T L 8 0 2 9 A S c o n tr o lle r u s e s t h e I N T A in t e r r u p t p in . I P R = 0 1 H

LS009.0 1997.01.16 RTL8029AS Preliminary 2 5 6. FUNCTION DESCRIPTION 6.1. RTL8029AS Configuration Process T h e R T L 8 0 2 9 A S c o n tr o lle r s u p p o r ts P C I c o n f ig u r a t io n o p e r a t io n . I n P C I s y s t e m , t h e in it ia l p r o c e s s is c o m p le te d b y th e s y s te m B I O S s o f t w a r e . T h e s y s t e m B I O S h a s t o f in d w h e r e t h e s y s t e m r e s o u r c e s a r e a v a ila b le , s u c h a s I /O b a s e a d d r e s s , B R O M m e m o r y b a s e a d d r e s s , a n d in t e r r u p t r e q u e s t lin e , a n d a s s ig n s th e r e s o u r c e s to t h e r e q u ir e d d e v ic e s . A t t h e s a m e t im e t h e R T L 8 0 2 9 A S c o n tr o lle r p e r fo r m s a s e r ie s o f E E P R O M r e a d o p e r a t io n a f t e r p o w e r - u p t o s e t E t h e r n e t I D , m e d ia t y p e , o p e r a tio n m o d e ¡K, e tc . T h e R T L 8 0 2 9 A S 's r e s o u r c e c o n f ig u r a t io n in f o r m a t io n is s t o r e d in t h e P C I c o n fig u r a t io n s p a c e a s w e ll a s C O N F I G r e g is t e r s in G r o u p 1 P a g e 3 . T h e C O N F I G r e g is t e r s p o w e r - u p d e fa u lt v a lu e s a lw a y s c o m e fr o m t h e c o n t e n t s o f 9 3 4 6 a n d t h e v a lu e s c a n b e m o d if ie d b y s o ftw a r e . T h e u p d a te c o n fig u r a tio n is o n ly v a lid t e m p o r a r ily a n d w ill b e lo s t a f t e r a n a u t o - lo a d c o m m a n d , a n a c tiv e R S T B , o r P C p o w e r o f f . P e r m a n e n t c h a n g e s o f c o n f ig u r a t io n m u s t b e d o n e b y c h a n g in g th e c o n te n ts o f 9 3 4 6 . N o te th a t th e B R O M s iz e c a n n o t b e m o d if ie d t e m p o r a r ily .

LS009.0 1997.01.16 RTL8029AS Preliminary 2 6 6.2. 9346 Contents T h e 9 3 4 6 is a 1 K - b it E E P R O M . A lth o u g h it is a c t u a lly a d d r e s s e d b y w o r d s , w e lis t it s c o n t e n ts b y b y te s b e lo w fo r c o n v e n ie n c e . Bytes Contents Comments 00H - 01H (2 bytes) Power-up initial value of Page3 0 0 H C O N F I G 2 B o a r d C o n f ig u r a tio n s 0 1 H C O N F I G 3 02H - 0FH (14 bytes) NE2000 ID PROM 0 2 H - 0 7 H E th e r n e t I D 0 - 5 E th e r n e t n o d e a d d r e s s 0 8 H - 0 F H P r o d u c t I D 0 - 7 A s s ig n e d b y c a r d m a k e r s ; n e g lig ib le 10H - 17H (8 bytes) Flow Control 1 0 H - 1 1 H P a u s e T y p e 0 - 1 1 2 H - 1 7 H P a u s e M u ltic a s t ID 0 - 5 18H-75H Unused 76H-77H (2 bytes) 8029ASID The value is 8029H which is programmed by PG8029. 78H-7FH (8 bytes) PCI ID PCI VID, DID, SVID and SID 7 8 H - 7 9 H V ID 0 - 1

7 A H - 7 B H D ID 0 - 1

7 C H - 7 D H S V ID 0 - 1

7 E H - 7 F H S ID 0 - 1

6.2.1 Detail values of 9346 CONFIG2-3 & 8029ASID0-1 bytes

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CONFIG2 P L 1 P L 0 FCE * * * B S 1 B S 0 CONFIG3 * F U D U P L E D S 1 L E D S 0 * * P W R D N * 8029ASID0 0 0 1 0 1 0 0 1 8029ASID1 1 0 0 0 0 0 0 0 P .S . '* ' d e n o te s d o n 't c a r e . Note: RTL8029AS checks the 8029ASID word in 9346 when power up. If the value matches “8029h”, the RTL8029AS works in RTL8029AS mode. You can use all new features defined by RTL8029AS, such as Flow Control, Programmable Vendor ID ¼ etc. If the value doesn‘t match, the RTL8029AS works like RTL8029. All enhanced functions and registers are not available. Also the PCI IDs in 9346 are ignored and the RTL8029’s ID(10ECh, 8029h) will be used instead.

LS009.0 1997.01.16 RTL8029AS Preliminary 2 7

6.2.2 ID PROM Contents

T h e R T L 8 0 2 9 A S e m u la te s th e I D P R O M o f N E 2 0 0 0 in t e r n a lly . A f t e r 9 3 4 6 is lo a d e d , t h e c o n te n t s o f I D P R O M a r e a s fo llo w s . o f f s e t B it7 - 0 0 0 H E th e r n e t I D 0 0 1 H E th e r n e t I D 1 0 2 H E th e r n e t I D 2 0 3 H E th e r n e t I D 3 0 4 H E th e r n e t I D 4 0 5 H E th e r n e t I D 5 0 6 H P I D 0 0 7 H P I D 1 0 8 H P I D 2 0 9 H P I D 3

0 A H P I D 4

0 B H P I D 5

0 C H P I D 6

0 D H P I D 7

0 E H 5 7 ( A S C I I C o d e o f " W " )

0 F H 5 7 ( A S C I I C o d e o f " W " )

1 0 H E th e r n e t I D 0 1 1 H E th e r n e t I D 1 1 2 H E th e r n e t I D 2 1 3 H E th e r n e t I D 3 1 4 H E th e r n e t I D 4 1 5 H E th e r n e t I D 5 1 6 H P I D 0 1 7 H P I D 1 1 8 H P I D 2 1 9 H P I D 3

1 A H P I D 4

1 B H P I D 5

1 C H P I D 6

1 D H P I D 7

1 E H 4 2 ( A S C I I C o d e o f " B " )

1 F H 4 2 ( A S C I I C o d e o f " B " )

d ia g r a m d e m o n s tr a te s th e ir c o n n e c tio n r e la t io n s h ip . Figure 1. Local Memory Bus Block Diagram m o d e . It d e te c ts P A U S E p a c k e t to a c h ie v e flo w c o n tr o l ta s k . packet with pause_time(=0000h) to w a k e u p th e s o u r c e s ta tio n to r e s ta r t tr a n s m is s io n . PAUSE packet with pause_time(=0000h) o r th e backoff timer(=n*51.2us) e la p s e s .

LS009.0 1997.01.16 RTL8029AS Preliminary 2 9 6.5. LED Behaviors T h is s e c tio n d e s c r ib e s th e lig h tin g b e h a v io r s o f t h e L E D o u t p u t s ig n a ls w h ic h m a y b e s e le c t e d b y L E D S 1 a n d L E D S 0 b its in th e P a g e 3 C O N F I G 3 r e g is t e r . P .S . I t is a s s u m e d th a t th e L E D is o n w h e n t h e s ig n a l g o e s lo w .

6.5.1 LED_TX: Tx LED

LED=low Transmitting Packet? LED=high for (100 10) ms LED=low for (6 2) ms Yes No

6.5.2 LED_RX: Rx LED

LED=low Receiving Packet? LED=high for (100 10) ms LED=low for (6 2) ms Yes No

LS009.0 1997.01.16 RTL8029AS Preliminary 3 0

6.5.3 LED_CRS=LED_TX+LED_RX: Carrier Sense LED

LED=low Tx or Rx Packet? LED=high for (100 10) ms LED=low for (6 2) ms Yes No

6.5.4 LED_COL: Collision LED

LED=high Collision (except Heartbeat)? LED=low for (10 5) ms + Yes No

LS009.0 1997.01.16 RTL8029AS Preliminary 3 1

6.5.5 LED Output States in Power Down Modes

LED Output Normal Mode / Idle Sleep Mode Power Down Mode L E D _ B N C - - L o w L E D _ L I N K - H ig h H ig h L E D _ C O L H ig h H ig h H ig h L E D _ T X L o w H ig h H ig h L E D _ R X L o w H ig h H ig h L E D _ C R S L o w H ig h H ig h 6.6. Loopback Diagnostic Operation 6.6.1. Loopback operation T h e R T L 8 0 2 9 A S p r o v id e s 3 lo o p b a c k m o d e s . B y lo o p b a c k t e s t , w e c a n v e r if y t h e in t e g r it y o f d a t a p a th , C R C lo g ic , a d d r e s s r e c o g n itio n lo g ic a n d c a b le c o n n e c t io n s t a t u s . Mode 1: L o o p b a c k th r o u g h th e N I C ( L B 1 = 0 , L B 0 = 1 in T C R ) . T h e N R Z d a ta is n o t tr a n s m itte d t o t h e S N I b u t in s t e a d it 's lo o p b a c k e d t o t h e N I C 's R x d e s e r ia liz e r . T h e tr a ffic o n th e c a b le is ig n o r e d . SNI 83910 NIC 8390Ref: Mode 2: L o o p b a c k th r o u g h th e S N I ( L B 1 = 1 , L B 0 = 0 in T C R ) T h e M a n c h e s te r e n c o d e d d a ta is n o t t r a n s m it t e d t o t h e M A U . I t 's lo o p b a c k e d t h r o u g h th e S N I to N I C . T h e tr a ffic o n th e c a b le is ig n o r e d . SNI 83910 NIC 8390 MAU 8392/RTL8005Ref: Mode 3: L o o p b a c k th r o u g h th e c a b le ( L B 1 = 1 , L B 0 = 1 in T C R ) T h e p a c k e ts a r e tr a n s m itte d v ia t h e M A U o n t o t h e n e t w o r k a n d R T L 8 0 2 9 A S r e c e iv e s a ll in c o m in g p a c k e ts ( n o t o n ly th e M A U - lo o p b a c k e d T x d a t a ) in t h e m e a n t im e . SNI 83910 NIC 8390 MAU 8392/RTL8005 CABLE Ref:

LS009.0 1997.01.16 RTL8029AS Preliminary 3 2 q Alignment of the Reception FIFO T h e r e c e p tio n F I F O is a n 8 - b y te r in g s tr u c t u r e . T h e f ir s t r e c e iv e d b y t e is p u t a t lo c a t io n z e r o . W h e n th e lo c a t io n p o in te r g o e s to th e e n d o f t h e F I F O , it w r a p s t o t h e b e g in n in g o f t h e F I F O a n d o v e r w r ite s th e p r e v io u s d a ta . A t th e e n d o f t h e p a c k e t r e c e p t io n , t h e F I F O c o n t e n t s a r e in t h e " o r d e r " ( fr o m th e r in g s tr u c tu r e 's v ie w ) a s s h o w n b e lo w . (1) CRC enabled (CRC bit in TCR=0) s 1 - b y te r e c e iv e d p a c k e t d a ta s 4 - b y te C R C s 1 - b y te lo w e r b y te c o u n t s 1 - b y te u p p e r b y te c o u n t s 1 - b y te u p p e r b y te c o u n t (2) CRC disabled (CRC bit in TCR=1) s 5 - b y te r e c e iv e d p a c k e t d a ta s 1 - b y te lo w e r b y te c o u n t s 1 - b y te u p p e r b y te c o u n t s 1 - b y te u p p e r b y te c o u n t 6.6.2. To Implement Loopback Test (1) To verify the integrity of data path s s e t R C R = 0 0 H to a c c e p t p h y s ic a l p a c k e t s s e t P A R 0 - 5 to a c c e p t p a c k e t s s e t D C R = 4 3 H s s e t T C R = 0 2 H , 0 4 H , 0 6 H to d o lo o p b a c k t e s t 1 , 2 , 3 r e s p e c t iv e ly s s e t C R C e n a b le d ( C R C = 0 0 H in T C R ) s c le a r I S R s T x a p a c k e t a n d c h e c k I S R s c h e c k F I F O a fte r lo o p b a c k N o te s : L o o p b a c k m o d e 3 is s e n s itiv e t o t h e n e t w o r k t r a f f ic , s o t h e v a lu e s o f F I F O m a y b e n o t c o r r e c t. (2) To verify CRC logic q Select a loopback mode (e.g. mode 2) to test A. To test CRC generator s s e t R C R = 0 0 H to a c c e p t p h y s ic a l p a c k e t s s e t P A R 0 - 5 to a c c e p t p a c k e t s s e t T C R = 0 4 H ( C R C e n a b le d ) s s e t D C R = 4 3 H s c le a r I S R s T x a p a c k e t s c h e c k C R C b y te s in F I F O a fte r lo o p b a c k B. To test CRC checker

LS009.0 1997.01.16 RTL8029AS Preliminary 3 3 s s e t R C R = 0 0 H to a c c e p t p h y s ic a l p a c k e t s s e t P A R 0 - 5 to a c c e p t p a c k e t s s e t T C R = 0 5 H ( C R C d is a b le d ) s s e t D C R = 4 3 H s c le a r I S R s T x a p a c k e t w ith g o o d o r b a d C R C a p p e n d e d b y p r o g r a m s c h e c k F I F O , I S R & R S R a fte r lo o p b a c k F o r b a d C R C , e x p e c te d : I S R = 0 6 H , R S R = 0 2 H ( T x :O K , R x :C R C e r r o r ) F o r g o o d C R C , e x p e c te d : I S R = 0 2 H , R S R = 0 1 H ( T x :O K , R x :O K ) N o te s : I n lo o p b a c k m o d e , th e r e c e iv e d p a c k e t s a r e n o t s t o r e d t o S R A M , s o P R X b it in I S R is n 't s e t. (3) To verify the address recognition function q Select a loopback mode (e.g. mode 2) to test A. Right physical destination address s s e t R C R = 0 0 H to a c c e p t p h y s ic a l p a c k e t s s e t P A R 0 - 5 to a c c e p t p a c k e t s s e t T C R = 0 4 H ( C R C e n a b le d ) s s e t D C R = 4 3 H s c le a r I S R s T x a p a c k e t s c h e c k I S R a fte r lo o p b a c k E x p e c te d : I S R = 0 6 H ( p a c k e ts a c c e p te d , R x C R C e r r o r ) B. Wrong physical destination address s s e t R C R = 0 0 H to a c c e p t p h y s ic a l p a c k e t s s e t P A R 0 - 5 to r e je c t p a c k e t s s e t T C R = 0 4 H ( C R C e n a b le d ) s s e t D C R = 4 3 H s c le a r I S R s T x a p a c k e t s c h e c k I S R a fte r lo o p b a c k E x p e c te d : I S R = 0 2 H ( p a c k e ts r e je c t e d , R x n o r e s p o n s e ) (4) To Test Cable Connection q There are four physical medium types in RTL8029AS. We perform loopback mode 3 to test the cable connection status. s s e t R C R = 0 0 H to a c c e p t p h y s ic a l p a c k e t s s e t P A R 0 - 5 to a c c e p t p a c k e t s s e t T C R = 0 6 H ( C R C e n a b le d ) s s e t D C R = 4 3 H s c le a r I S R s T x a p a c k e t s c h e c k T S R a fte r lo o p b a c k

LS009.0 1997.01.16 RTL8029AS Preliminary 3 4 A. 10Base2 I f c a b le O K , g e t T S R = 0 1 H ( T x O K ) . I f c a b le F A I L , g e t T S R = 0 C H ( C o llis io n a n d T x a b o r t e d ) . B. 10Base5 I f c a b le O K , g e t T S R = 0 1 H ( T x O K ) . I f M A U c o n n e c te d b u t c a b le F A I L , g e t T S R = 0 C H ( T x c o llis io n a n d T x a b o r t e d ) . I f M A U n o t c o n n e c te d , g e t T S R = 5 1 H ( C a r r ie r s e n s e is lo s t d u r in g t r a n s m is s io n a n d C D h e a r tb e a t fa ils .) . C. 10BaseT with link test disabled R T L 8 0 2 9 A S d is a b le s lin k te s t in th is c a s e , s o c a b le O K o r F A I L d o e s n 't a f f e c t T S R ; g e t T S R = 0 1 H . D. Auto-detection (10BaseT with link test enabled) R T L 8 0 2 9 A S a u to m a tic a lly s w itc h e s fr o m 1 0 B a s e T t o 1 0 B a s e 2 if t h e t w is t e d - p a ir w ir e is n o t c o n n e c te d ( 1 0 B a s e T lin k te s t fa ils ) . I f tw is te d - p a ir w ir e O K , g e t T S R = 0 1 H ( T x O K ) & B N C = 0 in C O N F I G 2 . I f tw is te d - p a ir w ir e F A I L b u t c o a x ia l c a b le O K , g e t T S R = 0 1 H ( T x O K ) & B N C = 1 in C O N F I G 2 . O th e r w is e , g e t T S R = 0 C H ( s a m e a s 1 0 B a s e 2 c o n n e c t io n f a il) .

LS009.0 1997.01.16 RTL8029AS Preliminary 3 5 7. ELECTRICAL SPECIFICATIONS AND TIMINGS 7.1. Absolute Maximum Ratings 1 4 0 ¢J 7 V Warning: S tr e s s e s b e y o n d th o s e lis te d u n d e r " A b s o lu t e M a x im u m R a t in g s " m a y c a u s e p e r m a n e n t d a m a g e t o t h e d e v ic e . T h e s e a r e s tr e s s r a tin g s o n ly . F u n c tio n a lity a t o r a b o v e th e s e lim its is n o t r e c o m m e n d e d a n d e x t e n d e d e x p o s u r e t o " A b s o lu t e M a x im u m R a tin g s " m a y a ffe c t d e v ic e r e lia b ilit y . 7.2. D.C. Characteristics (Tc=0 ¢J to 70 ¢J, Vcc=5V+5%) Symbol Parameter Min. Typ. Max. Unit Conditions V il I n p u t L o w V o lta g e 0 .8 V V ih I n p u t H ig h V o lta g e 2 .0 5 .5 V V o l L o w - le v e l o u tp u t v o lta g e 0 .5 5 V I o = 3 m A , 6 m A V o h H ig h - le v e l o u tp u t v o lta g e 2 .4 I o h = - 2 m A I I I n p u t L e a k a g e C u r r e n t 1 0 µA V = G N D to V D D 7.3. A.C. Timing Characteristics 7.3.1. PCI Configuration Read/Write

LS009.0 1997.01.16 RTL8029AS Preliminary 3 6 7.3.1.1. Configuration Read CLK FRAMEB IDSEL AD31-0 CBE3-0B TRDYB IRDYB DEVSELB PAR ADDR DATA ADDR DATA CMD BE CMD BE 7.3.1.2. Configuration Write CLK FRAMEB IDSEL AD31-0 CBE3-0B TRDYB IRDYB DEVSELB ADDR CMD DATA BE ADDR CMD DATA BE

LS009.0 1997.01.16 RTL8029AS Preliminary 3 7 7.3.2. PCI I/O Read/Write 7.3.2.1. PCI I/O Read CLK FRAMEB AD31-0 CBE3-0B TRDYB IRDYB DEVSELB PAR ADDR ADDR CMD DATA BE CMD BE DATA 7.3.2.2. PCI I/O Write CLK FRAMEB AD31-0 CBE3-0B TRDYB IRDYB DEVSELB ADDR ADDRDATA DATA CMD CMD BEBE

LS009.0 1997.01.16 RTL8029AS Preliminary 3 8 7.3.3. BROM Read CLK FRAMEB AD31-0 CBE3-0B TRDYB IRDYB DEVSELB PAR ADDR CMD BE DATA BE 7.3.4. Output Timing for PCI Interface T_val T_on T_off CLK OUTPUT DELAY Tri-State OUTPUT 7.3.5. Input Timing for PCI Interface CLK INPUT inputs valid T_hT_su

LS009.0 1997.01.16 RTL8029AS Preliminary 3 9 Symbol Parameter Min. Typ. Max. Unit tv a l C L K to S ig n a l V a lid D e la y - b u s s e d s ig n a ls 2 1 1 n s to n F lo a t to A c tiv e D e la y 1 1 n s to f f A c tiv e to F lo a t D e la y 1 1 n s ts u I n p u t S e t u p T im e to C L K - b u s s e d s ig n a ls 7 n s th I n p u t H o ld T im e f r o m C L K 0 n s 7.3.6. Serial EEPROM (9346) Auto-load 00 0 011 EESK EECS EEDI EEDO EESK EECS EEDI EEDO T7 T8 T5 T6 T2T1 T3 T4 D15 D14 A0A1A2 D1 D0 Symbol Parameter Min. Typ. Max. Unit T 1 E E S K h ig h w id th 3 .2 n s T 2 E E S K lo w w id th 3 .2 n s T 3 E E D I s e tu p to E E S K r is in g e d g e 3 .0 n s T 4 E E D I h o ld f r o m E E S K f a llin g e d g e 3 .0 n s T 5 E E C S g o e s h ig h to E E S K r is in g e d g e 3 .0 n s T 6 E E C S g o e s lo w f r o m E E S K f a llin g e d g e n s T 7 E E D O s e tu p to E E S K f a llin g e d g e 2 0 n s T 8 E E D O h o ld f r o m E E S K f a llin g e d g e 1 0 n s

LS009.0 1997.01.16 RTL8029AS Preliminary 4 0 REALTEK Semiconductor Co., Ltd. r e s e r v e d a ll r ig h t s o f t h is d o c u m e n t . N o p a r t o f t h is d o c u m e n t m a y b e c o p ie d o r r e p r o d u c e d in a n y f o r m o r b y a n y m e a n s o r t r a n s f e r r e d t o a n y t h ir d p a r ty w ith o u t th e p r io r w r itte n c o n s e n t o f REALTEK Semiconductor Co., Ltd. REALTEK r e s e r v e s th e r ig h t to c h a n g e p r o d u c ts o r s p e c if ic a t io n s w it h o u t n o t ic e . T h is d o c u m e n t h a s b e e n c a r e fu lly c h e c k e d a n d is b e lie v e d to b e a c c u r a t e . H o w e v e r REALTEK Semiconductor Co., Ltd. a s s u m e s n o r e s p o n s ib ility fo r in a c c u r a c ie s .

LS009.0 1997.01.16 RTL8029AS Preliminary 4 1 N o t e : S y m b o l D im e n s io n in m il D im e n s io n in m m 1 .D im e n s io n D & E d o n o t in c lu d e in te r le a d f la s h . M in T y p M a x M in T y p M a x 2 .D im e n s io n b d o e s n o t in c lu d e d a m b a r p r o tr u s io n /in tr u s io n . y ¡Ð ¡Ð 3 .9 ¡Ð ¡Ð 0 .1 0 S H T N O . 1 O F £c 0 ¢X ¡Ð 1 2 ¢X 0 ¢X ¡Ð 1 2 ¢X REALTEK SEMI-CONDUCTOR CO., LTD