RRP58000

RRP58000 RENESAS

Document overview

• Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
• PDF pages: 19

Technical content

Datasheet sections

• 1.1 Block Diagram
• 2.1 Pin Assignments
• 2.2 Pin Descriptions
• 3.1 Absolute Maximum Ratings
• 3.2 Recommended Operating Conditions
• 3.3 Thermal Specifications
• 3.4 Electrical Specifications
• 5.1 Overview
• 5.2 Theory of Operation of PMOS LDOs
• 6.1 UVLO
• 6.2 Enable Control
• 6.3 Short-Circuit Current Limit Protection
• 6.4 Over-Temperature Shutdown (OTSD) Protection
• 6.5 Voltage Requirements
• 6.5.1 Input Voltage
• 6.5.2 Output Voltage
• 6.6 External Capacitor Selection
• 6.6.1 Input Capacitor
• 6.6.2 Output Capacitor
• 6.7 Power Dissipation and Thermals
• 6.7.1 Power Dissipation
• 6.7.2 The Junction Temperature and Thermal Resistance

Features

▪ Wide input voltage range: up to 80V ▪ Adjustable output voltage (1.24V - 15V) ▪ Typical low-quiescent current: 5.8µA at no load ▪ Max output current: 50mA ▪ Excellent line and load regulation over temperature with Output voltage accuracy: ±2.5% ▪ Typical shutdown current: ≤0.2µA ▪ Stable with 2.2µF minimum ceramic output capacitor ▪ Typical dropout voltage: ≤0.8V at 50mA ▪ Overcurrent and over-temperature protection ▪ Junction temperature range: -40°C to 125°C

Applications

▪ Portable and battery-powered equipment ▪ Notebook computers ▪ Motor drives Figure 1. Typical Application Schematics

1.1 Block Diagram

Figure 2. Block Diagram

2.1 Pin Assignments

2.2 Pin Descriptions

Figure 3. Pin Assignments - Top View pin and GND. Place the capacitor as close to the output of the regulator as possible.

2 ADJ

output voltage is set to the minimum 1.23V. 4 GND Ground reference. This pin must be tied to the PCB ground plane. connected to VIN for automatic turn on. with 0.1µF or larger high frequency ceramic capacitor to GND.

R16DS0441EU0101 Rev.1.01 Page 5 Jun 17, 2024 RRP58000 Datasheet 3. Specifications

3.1 Absolute Maximum Ratings

Caution: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.

3.2 Recommended Operating Conditions

3.3 Thermal Specifications

Parameter[1] 1. All voltages referenced to GND unless otherwise specified. Minimum Maximum Unit VIN, VEN -0.3 +85 V VOUT -0.3 +20 V ADJ -0.3 +4 V Maximum Junction Temperature - +125 °C Maximum Storage Temperature Range -65 +150 °C Human Body Model (Tested per JS-001-2023) - 2 kV Charged Device Model (Tested per JS-002-2022) - 750 V Latch-Up (Tested per JESD78E) - 100 mA Parameter[1] 1. All voltages referenced to GND unless otherwise specified. Minimum Maximum Unit Supply Voltage, VIN 3.5 80 V Enable Voltage, VEN 3.5 80 V Output Voltage, VOUT 1.24 15 V Output Current, IOUT 0 50 mA Output Capacitor, COUT 2.2 200 µF Junction Temperature -40 +125 °C Parameter Package Symbol Conditions Typical Value Unit Thermal Resistance[1] 1. Specified at published junction to ambient thermal resistance for a junction temperature of +150°C. See footnote 2 for test conditions to establish junction to ambient thermal resistance. 8-Ld HMSOP θJA[2] 2. θ JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379. Junction to ambient 56 °C/W θJA(EVB)[3] 3. θ JA(EVB) is measured in free air with the component mounted on a 2-layer PCB (2oz Cu finish all layers) evaluation board. Junction to EVB 39.6 °C/W θJC[4] 4. For θ JC, the case temperature location is the center of the exposed metal pad on the package underside. Junction to case 14 °C/W

R16DS0441EU0101 Rev.1.01 Page 6 Jun 17, 2024 RRP58000 Datasheet

3.4 Electrical Specifications

Operating conditions unless otherwise noted: TJ = -40°C to +125°C, VIN = 3.5V, VOUT = Vadj, IOUT = 1mA, VEN = 5V, COUT = 2.2µF MLCC. Typical values are at TA = +25°C, unless otherwise specified. P arameter Symbol Test Conditions Min[1] 1. Compliance to datasheet limits is established by one or more methods: production test, characterization, and/or design. Typ. Max [1] Unit Input Input Voltage Range VIN VIN - 3.5 - 80 V Input UVLO Rising Threshold - VIN Rising 2.09 2.39 2.71 V Input UVLO Falling Threshold - VIN Falling 1.90 2.20 2.50 V Quiescent Current IQ IOUT = 0mA, VOUT = VADJ - 5 10 µA Ground Current IGND IOUT = 10mA, VOUT = VADJ - 51 100 µA IOUT = 50mA, VOUT = VADJ - 131 200 Shutdown Current ISHDN VEN = 0V - 0.2 1.0 µA Output Output Voltage V OUT - 1.24 - 15 V Adjust Pin Voltage VADJ - 1.21 1.24 1.27 V Output Current IOUT - 0 - 50 mA Dropout Voltage VDO IOUT = 10mA, VOUT = 3.3V - 0.16 0.40 VIOUT = 20mA, VOUT = 3.3V - 0.31 0.60 IOUT = 50mA, VOUT = 3.3V - 0.77 1.40 Load Regulation ΔVOUT/ΔIOUT - I OUT = 100µA < IOUT < 50mA - 0.0001 0.010 %/mA Line Regulation ΔVOUT/ΔVIN - V IN = 3.5 - 80V - 0.001 0.050 %/V Start-Up Time TST Time from VIN = VOUT + 1.7V to 95% of VOUT, IOUT = 0mA 281 655 1206 µs Power Supply Ripple Rejection Ratio PSRR FREQ = 10Hz - 80 - dB FREQ = 100Hz - 75 - dB FREQ = 1kHz - 60 - dB Output Voltage Noise Vn BW = 100Hz to 100kHz VOUT = VADJ - 200 - µVRMS EN VEN Rising Threshold - IOUT = 1mA 1.21 1.47 1.70 V VEN Falling Threshold - 1.00 1.27 1.50 V EN Leakage Current IEN VIN = VEN = 80V - 0.1 0.2 µA Protection Output Current Limit ICL - 70 97 150 mA Thermal Shutdown TOTSD Temperature Rising - 155 - °C Thermal Shutdown Hysteresis T OTSD(HYST) - - 20 - °C

5.1 Overview

current limit, and over-temperature shutdown protection. choice for portable devices and battery-powered equipment.

5.2 Theory of Operation of PMOS LDOs

VOUT is set by the internal resistors. between VFB and VREF by changing the gate voltage of the PMOS pass transistor and therefore the rDS(ON). output voltage bringing it back into regulation. source to increase the rDS(ON), which decreases the output voltage bringing it back into regulation. Figure 24. Simple PMOS LDO Regulator Block Diagram

Fundamental Theory of PMOS Low-Dropout Voltage Regulators.

6.1 UVLO

the UVLO threshold. This prevents the parts from turning on in an unpredictable state. and draws current. Figure 25 illustrates the UVLO operation.

6.2 Enable Control

typically 0.2µA. When the LDO is enabled the quiescent current is typically 0.1µA no load. voltage through a resistor divider. Figure 25. UVLO Operation b The LDO is enabled and the output starts to rise. c The LDO remains enabled because the Input Voltage is still higher than the UVLO falling threshold.

R16DS0441EU0101 Rev.1.01 Page 13 Jun 17, 2024 RRP58000 Datasheet

6.3 Short-Circuit Current Limit Protection

The short-circuit protection circuitry (ILIM) limits the maximum output current that the LDO can source during fault conditions such as short-circuits or start-up inrush current. During a short-circuit fault, the LDO becomes a constant current source resulting from a decrease in load resistance that causes a decrease in the output voltage. This relationship is summarized in Equation 2. When the short or overcurrent condition is removed, the LDO returns to normal output voltage regulation. Because of the high-power dissipation caused by overcurrent faults, the LDO can begin to cycle ON and OFF because the die junction temperature (T J) is exceeding thermal fault conditions (typical: +155°C) and subsequently cooling down to +135°C when the LDO is disabled.

6.4 Over-Temperature Shutdown (OTSD) Protection

The RRP58000 is protected against thermal overloads caused by current limit protection or high ambient temperature (T A). When the die junction temperature (TJ) exceeds the typical +155°C, the thermal shutdown circuit disables the LDO reducing the output current (IOUT) to 0A, therefore, reducing the output voltage (VOUT) to 0V and allowing the LDO to cool. A 20°C hysteresis is included to prevent the LDO from uncontrollably heating and cooling. Prolonged exposure to a T J exceeding +125°C reduces the long-term stability and life of the LDO. Therefore, it is important that the design considers the TA the LDO works in, the thermal resistance between TJ and TA (θJA), and any fault conditions that can cause the TJ to exceed the recommended operating range. In some applications, a heat sink might be required for implementation.

6.5 Voltage Requirements

6.5.1 Input Voltage

The RRP58000 operates with an input voltage of 3.5V to 80V on the VIN pin. The input supply must be able to supply enough current to keep the input voltage from drooping during load steps or high load currents. For proper voltage regulation, the input voltage must be chosen so that it is higher than the sum of the output voltage and the maximum dropout voltage expected for a given application as expressed in Equation 3. The difference between VIN and VOUT required for proper regulation is commonly called the headroom voltage (VHEADROOM). (EQ. 2) (EQ. 3) VOUT ILIM R FAULT= VIN VOUT VDROPOUT MAX +

6.5.2 Output Voltage

VOUT is the required output voltage and can be calculated using Equation 4, where 1.24V is the reference voltage. Resistors shown on Table 1 are commercially available in a 0.1% tolerance. Figure 26. Setting the Output Voltage Table 1. Recommended R1 and R2 Resistor Values for Typical VOUT applications

R16DS0441EU0101 Rev.1.01 Page 15 Jun 17, 2024 RRP58000 Datasheet

6.6 External Capacitor Selection

The RRP58000 is stable with 2.2µF CIN and COUT capacitors. For better load transient performance, a 4.7µF or higher output capacitor is recommended. Multilayer ceramic capacitors (MLCC) are an excellent choice because of their small size, low ESR, low ESL, and wide operating temperature; although, they are not without their problems. Ceramic capacitor values can vary with the DC bias voltage, temperature, and tolerance. Therefore, Renesas recommends using de-rated capacitors. X5R, X7R, and C0G capacitors are recommended. To ensure the performance of the RRP58000, it is important that the effects of DC bias voltage, temperature, and tolerances for a chosen capacitor are evaluated. The X7R type is recommended because it has lower capacitance variation over-temperature. Place the bypass capacitors as close as is practical to their respective pins to minimize trace inductance.

6.6.1 Input Capacitor

The minimum input capacitor that is recommended is 2.2µF to reduce the negative effects of large input impedances because of long input traces of high source impedances. Renesas recommends connecting this capacitor between VIN and GND. A larger bulk capacitor such as a 10µF might be required to be added to minimize input voltage droops during large changes in load currents, such as during load transients or start-up to not affect stability. Larger input capacitors also improve the line transient response.

6.6.2 Output Capacitor

The RRP58000 is stable with a 2.2µF minimum output ceramic capacitor. A large value output capacitor can help minimize the overshoot and undershoot transient response due to large changes in load current. Larger or multiple output capacitors can also be used to improve high-frequency PSRR.

6.7 Power Dissipation and Thermals

To ensure reliable operation, the die junction temperature (TJ) of the RRP58000 must not exceed +125°C. In applications with high ambient temperature (TA), large headroom voltages (VHEADROOM), and large load currents (IOUT), the heat dissipated in the package can become large enough to cause the TJ to exceed the maximum operating temperature of +125°C.

6.7.1 Power Dissipation

The Power Dissipation (PD) is calculated using Equation 6. Because the power dissipation contribution from the quiescent (or ground current) is typically small compared to the current, the LDO must supply to a load; it can be ignored, and Equation 6 simplifies to Equation 7. Therefore, to lower the power dissipated inside the die, the V HEADROOM and/or the IOUT can be decreased.

6.7.2 The Junction Temperature and Thermal Resistance

The junction temperature (TJ) is the sum of the environmental ambient temperature (TA) and the temperature rise in the TJ because of power dissipation, which is calculated using Equation 8. θJA is the thermal resistance between the junction temperature and ambient temperature and is dependent on the device package and the PCB design. (EQ. 6) (EQ. 7) (EQ. 8) PD VIN VOUT–  IOUT VIN IGND+= PD VIN VOUT–  IOUT= TJ TA JA PD+ =

R16DS0441EU0101 Rev.1.01 Page 16 Jun 17, 2024 RRP58000 Datasheet 7. Layout Guidelines The following are recommendations for the RRP58000 to achieve optimal performance: ▪ Place all the required components for the RRP58000 on the same layer as the IC. ▪ Place a minimum capacitance of 2.2µF ceramic input capacitor to the VIN and GND pins of the LDO as close as practical. ▪ Place a minimum capacitance of 2.2µF ceramic output capacitor to the VOUT and GND pins of the LDO as close as practical. ▪ The package thermal EPAD is the largest heat conduction path for the package. Solder it to a copper pad on the PCB underneath the part. The PCB thermal pad should have as many plated vias to increase the heat flow from the package thermal EPAD to the inner PCB areas and/or the bottom PCB area. If possible, adding thermal vias around the PCB package helps improve heat spread from the package to other layers of the board. ▪ Keep the vias small but not so small that their inside diameter prevents solder from wicking through the holes during reflow. For efficient heat transfer, the vias must have low thermal resistance. Do not use thermal relief patterns to connect the vias. It is important to have a complete connection of the plated through-hole to each plane. The top copper GND layer that the EPAD is connected to is the least thermally resistant path for heat flow. To this end, minimize the components and traces that cut this layer.

R16DS0441EU0101 Rev.1.01 Page 17 Jun 17, 2024 RRP58000 Datasheet 8. Package Outline Drawing For the most recent package outline drawing, see M8.118C. M8.118C

8 Lead Heat-Sink Mini Small Outline Plastic Package (HMSOP)

Rev 0, 9/2023 Dimensioning and tolerancing conform to JEDEC MO-187-AA Plastic interlead protrusions of 0.15mm max per side are not Dimensions in ( ) are for reference only. Dimensions are measured at Datum Plane "H". Plastic or metal protrusions of 0.15mm max per side are not Dimensions are in millimeters. NOTES: PIN# 1 ID SIDE VIEW 1 TYPICAL RECOMMENDED LAND PATTERN TOP VIEW 0.22 - 0.40 Detail "X" Detail "X" 0.00 - 0.15 SIDE VIEW 2 0.08 - 0.23 3°±3° Gauge Plane 0.25

0.95 Ref

0.60 ±0.20 1 2 0.85 ±0.10 Seating Plane and ASME Y14.5m-1994. included. included. 3.00 ±0.10 A 3.00 ±0.10 4.90 ±0.20 D

0.65 BSC

1.10 Max

H C 0.08 C A-B D 0.10 C B 1.55 ±0.020 1.75 ±0.020 BOTTOM VIEW (3.00)(5.80) (0.40) (0.65) (4.40) 1.55 ±0.020 1.75 ±0.020 (1.40)

R16DS0441EU0101 Rev.1.01 Page 18 Jun 17, 2024 RRP58000 Datasheet 9. Ordering Information 10. Revision History Part Number[1][2] 1. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 2. For the Moisture Sensitivity Level (MSL) rating, see the RRP58000 product page. For more information about MSL, see TB363. Part Marking Output Voltage (V) Package Description[3] (RoHS Compliant) 3. For the Pb-Free reflow profile, see TB493. Pkg. Dwg # Carrier Type Temperature Range RRP58000-SH0 58000 Adj. 8 Ld HMSOP M8.118C Tube -40°C to +125°C RTKA58000DR0000BU Demonstration board Revision Date Description 1.01 Jun 17, 2024 Updated 3.3 Thermal Specifications table: - Added Junction to EVB to the Conditions.

1.00 Jun 5, 2024 Initial release

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www. renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit www.renesas.com /contact-us/ . Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD-PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers who are designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only to develop an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third-party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising from your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Disclaimer Rev.1.01 Jan 2024) © 2024 Renesas Electronics Corporation. All rights reserved.