Power Management

RRB86848

Renesas Technology Corp

Bidirectional Buck-Boost Voltage Regulator with SMBus Interface for General 48V and USB PD May 13, 2025

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RRB86848 RENESAS

Document overview

Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
PDF pages: 59

Technical content

Datasheet sections

1.1 Typical Application Diagram
1.2 Block Diagram
2.1 Pin Assignments
2.2 Pin Descriptions
3.1 Absolute Maximum Ratings
3.2 Recommended Operating Conditions
3.3 Thermal Specifications
3.4 Electrical Specifications
3.5 SMBus Timing Specification
3.6 Gate Driver Timing Diagrams
5.1 Data Validity
5.2 START and STOP Conditions
5.3 Acknowledge
5.4 SMBus Transactions
5.5 Byte Format
5.6 SMBus and I 2C Compatibility
5.7 SMBus Commands
6.1 Register Summary
6.2 DAC Register Summary
6.3 Control Registers
6.4 Information Registers
7.1 RRB86848 Buck-Boost Converter Modes of Operation
7.2 USB On-the-Go (USB OTG)
7.3 Pass-Through Mode
7.4 Modulator Control Loops
7.4.1 Adapter Current Loop and Two-Level Current Limit
7.4.2 Input Voltage Regulation Loop
7.4.3 USB-PD On-the-Go Output Voltage
7.4.4 USB-PD On-the-Go Output Current
7.4.5 Output Voltage Regulation
7.4.6 Output Current Loop
7.5 R3 Modulator
8.1 Soft-Start
8.2 Programming Options
8.3 PGOOD
8.4 Low Power Modes
8.4.1 Forward Sleep Mode
8.4.2 Reverse Sleep Mode
8.5 Diode Emulation Operation
8.6 Monitoring
8.6.1 Current Monitor
8.6.2 ALERT#

Features

▪ Bidirectional buck, boost, and buck-boost operation ▪ Input voltage range: 3.9V to 55V (no dead zone) ▪ Output voltage: 2.4V to 55V ▪ Pass-Through mode in forward direction ▪ Adapter current and output current monitor (AMON/BMON) ▪ Battery charging support ▪ Forward and reverse sleep modes ▪ 4×4 32 Ld TQFN package compatible with the ISL9238, RAA489108, and RAA489118 family of parts

Applications

▪ Voltage regulation for docking stations and other applications using USB-C EPR inputs or outputs ▪ Battery charging for lawnmowers and other lawn tools, eBikes, power tools, power banks Figure 1. Full-Featured Architecture Solutions Enabled by RRB86848

R16DS0426EU0101 Rev.1.01 Page 3 May 13, 2025 RRB86848 Datasheet

1.1 Typical Application Diagram

Figure 2. Typical Application Circuit

Figure 3. Application Circuit for 2-FET Mode

1.2 Block Diagram

Figure 4. Block Diagram

2.1 Pin Assignments

2.2 Pin Descriptions

Figure 5. Pin Assignments ‒ Top View be used as the thermal pad for heat dissipation. negative input. Place a ceramic capacitor between CSOP and CSON to provide differential mode filtering. positive input. Place a ceramic capacitor between CSOP and CSON to provide differential mode filtering. 3 VOUTS1 Provides feedback voltage for OutputVoltage regulation.

4 BOOT2

5V and x50 effective high-side MOSFET gate capacitance. 5 UGATE2 High-side MOSFET Q4 gate drive. high-side MOSFET Q4 source, the low-side MOSFET Q3 drain, and one terminal of the inductor. 7 LGATE2 Low-side MOSFET Q3 gate drive.

8 VDDP

and x1.6 effective capacitance at the BOOT pin at 5V. 9 LGATE1 Low-side MOSFET Q2 gate drive. high-side MOSFET Q1 source, the low-side MOSFET Q2 drain, and one terminal of the inductor. 11 UGATE1 High-side MOSFET Q1 gate drive.

R16DS0426EU0101 Rev.1.01 Page 8 May 13, 2025 RRB86848 Datasheet

12 BOOT1

High-side MOSFET Q1 gate driver supply. Connect an MLCC capacitor across the BOOT1 and PHASE1 pins. The boot capacitor is charged through an internal boot diode connected from the VDDP to BOOT1 pins. Connect a 0.47µF bootstrap capacitor, which must have an effective capacitance higher than 0.25µF at 5V and x50 effective high-side MOSFET gate capacitance. 13 ASGATE Gate drive output to the P-channel adapter FET. The use of ASGATE FETs is optional. If they are not used, leave the ASGATE pin floating. 14 CSIN Forward mode input current sense negative input. Connect to the forward input current sense resistor negative input. Place a ceramic capacitor between CSIP and CSIN to provide differential mode filtering.

15 CSIP

Forward mode input current sense positive input. Connect to the forward input current sense resistor positive input. Place a ceramic capacitor between CSIP and CSIN to provide differential mode filtering. The modulator also uses the CSIP pin for sensing input voltage in forward mode and output voltage in reverse mode. 16 ADP Forward mode input used to sense adapter voltage. ASGATE is turned on when the adapter voltage is higher than 3.2V.

17 DCIN

Internal LDO input that provides power to the IC. Connect a diode OR from the adapter and output. Bypass DCIN with an MLCC capacitor. Connect a 10Ω DCIN resistor between the DCIN pin and the VADP/VOUT diodes, and connect a 4.7µF DCIN capacitor to GND. The capacitor must have an effective capacitance higher than 0.4µF at 30V.

18 VDD

Internal LDO output, which provides the bias power for the internal analog and digital circuit. Connect a 2.2µF (10V) MLCC capacitor to GND. The capacitor must have an effective capacitance higher than 0.4µF at 5V and x1.6 effective capacitance at the BOOT pin at 5V. If VDD is pulled below 2V for more than 1ms, the RRB86848 resets all the SMBus register values to their defaults. An external source can provide VDD power by overdriving the LDO output. 19 ACIN Adapter voltage sense. Use a resistor divider externally to detect adapter voltage. The adapter voltage is valid if the ACIN pin voltage is greater than 0.35V.

20 OTGEN/

Input pin. OTG/reverse mode enable pin, general-purpose comparator input pin. When the reverse mode is enabled and the general-purpose comparator is disabled, pulling this pin high can activate the reverse mode. When the general-purpose comparator is enabled, this pin is the general-purpose comparator input. 21 SDA SMBus data I/O. Connect to the data line from the host controller or smart battery. Connect a 10k pull-up resistor according to the SMBus specification. 22 SCL SMBus clock I/O. Connect to the clock line from the host controller or smart battery. Connect a 10k pull-up resistor according to the SMBus specification. 23 ALERT# Open-drain output. Provides an active-low alert signal if ACOK goes low and/or the general-purpose comparator activates. The ALERT# triggers are enabled using SMBus commands (see Table 7). 24 ACOK Adapter presence indicator output to indicate the adapter is ready. 25 RESERVED Must be connected to GND.

26 PGOOD/

Open-drain output. This pin provides either a power-good indication or the general-purpose comparator output.

27 PROG

A resistor from the PROG pin to GND sets the following configurations: ▪ Default output voltage ▪ Default adapter current limit ▪ Default output current limit See Table 15 for programming options. 28 COMP Error amplifier output. Connect a compensation network externally from COMP to GND.

29 AMON/

Forward input current, reverse output current, forward output current, or reverse input current monitor output. ▪ AMON_FORWARD = 18x (VCSIP - VCSIN) for forward input current monitor ▪ AMON_REVERSE = 18x (VCSIN - VCSIP) for reverse output current monitor ▪ BMON_FORWARD= 36x (VCSOP - VCSON) for forward output current monitor ▪ BMON_REVERSE = 18x (VCSON - VCSOP) for reverse input current monitor 30 RESERVED This pin should not float. Connect to either VDD or GND. 31 VOUTS2 Voltage sense pin for reverse mode. Connect VOUTS1 pin to VOUTS2 pin for Voltage regulator configuration. Connect an optional ceramic capacitor >1µF from VOUTS2 to GND.

32 Unused -

Number Pin Name Description

R16DS0426EU0101 Rev.1.01 Page 9 May 13, 2025 RRB86848 Datasheet 3. Specifications

3.1 Absolute Maximum Ratings

Caution: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.

3.2 Recommended Operating Conditions

Parameter Minimum Maximum Units CSIP, CSIN, DCIN, ADP, ASGATE -0.3 +63 V PHASE1 GND - 0.3 +63 V PHASE1 GND - 2 (<20ns) +63 V BOOT1, UGATE1 GND - 0.3 VDDP+63 V PHASE2 GND - 0.3 63 V PHASE2 GND - 2 (<20ns) 63 V BOOT2, UGATE2 GND - 0.3 VDDP+63 V LGATE1, LGATE2 GND - 0.3 +6.5 V LGATE1, LGATE2 GND - 2 (<20ns) +6.5 V VOUTS2, VOUTS1, CSOP, CSON -0.3 +63 V VDD, VDDP -0.3 +6.5 V COMP -0.3 +6.5 V AMON/BMON, RESERVED@Pin30 -0.3 +6.5 V OTGEN, RESERVED@Pin25 -0.3 +6.5 V ACIN, ALERT#, PGOOD, ACOK -0.3 +6.5 V SCL, SDA -0.3 +6.5 V BOOT1 - PHASE1, BOOT2 - PHASE2 -0.3 +6.5 V CSIP - CSIN, CSOP - CSON -0.3 +0.3 V PGOOD, ACOK - 2 mA Junction Temperature Range (TJ) -10 +125 °C Maximum Storage Temperature Range (TS) -65 +175 °C Human Body Model (Tested per JS-001-2023) - 2 kV Charged Device Model (Tested per JS-002-2022) - 750 V Latch-Up (Tested per JESD78E; Class 2, Level A) - 100 mA Parameter Minimum Maximum Unit Ambient Temperature RRB86848-AT7/AU7 -10 +100 °C RRB86848-AT8/AU8 -40 +100 °C Junction Temperature RRB86848-AT7/AU7 -10 +125 °C RRB86848-AT8/AU8 -40 +125 °C Adapter Voltage - +4 +55 V

R16DS0426EU0101 Rev.1.01 Page 10 May 13, 2025 RRB86848 Datasheet

3.3 Thermal Specifications

3.4 Electrical Specifications

Parameter Package Symbol Conditions Typical Value Unit Thermal Resistance 32 Ld TQFN Package θJA[1] 1. θ JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379. Junction to ambient. 37 °C/W θJC[2] 2. For θ JC, the case temperature location is the center of the exposed metal pad on the package underside. Junction to case. 2 °C/W Operating conditions: ADP = CSIP = CSIN = 5V, 28V, and 48V, VOUTS1 = VOUTS2 = CSOP = CSON = 8V, 29.4V, and 50.4V, unless otherwise noted. Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified. Parameter Symbol Test Conditions Min[1] Typ Max [1] Unit UVLO/ACOK VADP UVLO Rising VADP_UVLO_r - 3.05 3.36 3.7 V VADP UVLO Hysteresis VADP_UVLO_h - - 730 - mV VOUTS2 UVLO Rising VOUTS2_UVLO_r - 3.05 3.27 3.54 V VOUTS2 UVLO Hysteresis VOUTS2_UVLO_h - - 270 - mV VOUTS2 4P5V Rising VOUTS2_4P5_r - 4.2 4.5 4.9 V VOUTS2 4P5V Hysteresis VOUTS2_4P5_h - - 345 - mV VDD 2P7 POR Falling, SMBus and BMON Active Threshold VDD_2P7_f - 2.45 2.7 2.9 V VDD 2P7 POR Hysteresis[2] VDD_2P7_h - - 150 - mV VDD 3P8 POR Rising, Modulator and Gate Driver Active VDD_3P8_r - 3.6 3.8 3.9 V VDD 3P8 POR Hysteresis VDD_3P8_h - - 135 - mV ACIN Rising ACIN_r - 0.33 0.35 0.37 V ACIN Hysteresis ACIN_h - - 22 - mV Linear Regulator VDD Output Voltage (VDD = 5V setting) VDD 6V < V DCIN < 54V 4.5 5.0 5.5 V VDD Output Voltage (VDD = 4.5V setting) VDD 6V < V DCIN < 54V 4.05 4.5 4.95 V VDD Dropout Voltage VDD_dp <22mA, V DCIN = 4V - - 210 mV VDD Overcurrent Threshold VDD_OC AT7/AU7 Junction Temperature: -10 to +125°C 90 120 145 mA AT8/AU8 Junction Temperature: -40 to +125°C 85 120 155 mA Bias Current Forward Supply Current IFWD_SLP GPC OFF, AMON/BMON OFF ADP=CSIN=CSIP=DCIN=VDDP=5V, VOUTS2 tied to VOUTS1, Control5[3] = High - 7 30 µA GPC OFF, AMON/BMON OFF ADP=CSIN=CSIP=DCIN=48V, VDDP=5V, VOUTS2 tied to VOUTS1, Control5[3] = High - 12 35 µA

R16DS0426EU0101 Rev.1.01 Page 11 May 13, 2025 RRB86848 Datasheet Reverse Supply Current IREV_SLP1 No Adapter, GPC OFF, AMON/BMON OFF, VOUT = 50.4V, DCIN current comes from VOUT, RSLP = IVOUTS2 + ICSOP + ICSON + IDCIN + IVOUTS1 - 18 50 µA IREV_SLP2 No Adapter, GPC OFF, AMON/BMON ON, VOUT = 50.4V, DCIN current comes from VOUT, RSLP = IVOUTS2 + ICSOP + ICSON + IDCIN + IVOUTS1 - 84 135 µA Adapter Current Regulation, Rs1 = 10mΩ Adapter Current Accuracy - CSIP - CSIN = 50mV - 5 - A -2.7 - 2.7 % CSIP - CSIN = 40mV - 4 - A -3 - 3 % CSIP - CSIN = 30mV - 3 - A -3.5 - 3.5 % CSIP - CSIN = 25mV - 2.5 - A -4.2 - 4.2 % CSIP - CSIN = 20mV - 2 - A -5 5 % CSIP - CSIN = 15mV - 1.5 - A -6.9 - 6.9 % CSIP - CSIN = 10mV - 1 - A -10 - 10 % CSIP - CSIN = 5mV - 0.5 - A -20 - 20 % CSIP - CSIN = 2.5mV 0.25 A -40 40 % Operating conditions: ADP = CSIP = CSIN = 5V, 28V, and 48V, VOUTS1 = VOUTS2 = CSOP = CSON = 8V, 29.4V, and 50.4V, unless otherwise noted. Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified. Parameter Symbol Test Conditions Min[1] Typ Max [1] Unit

R16DS0426EU0101 Rev.1.01 Page 12 May 13, 2025 RRB86848 Datasheet Output Voltage Regulation Output Voltage Accuracy - OutputVoltage for 48V and 50.4V, AT7/AU7 Junction Temperature: -10 to +125°C -0.7 - 0.7 % OutputVoltage for 42V and 46.2V, AT7/AU7 Junction Temperature: -10 to +125°C -0.7 - 0.7 % OutputVoltage for 33.6V and 37.8V, AT7/AU7 Junction Temperature: -10 to +125°C -0.8 - 0.8 % OutputVoltage for 25.2V and 29.4V, AT7/AU7 Junction Temperature: -10 to +125°C -0.8 - 0.8 % OutputVoltage for 16.8V and 21V, AT7/AU7 Junction Temperature: -10 to +125°C -1.3 - 1.3 % OutputVoltage for 8.4V and 12.6V, AT7/AU7 Junction Temperature: -10 to +125°C -1.5 - 1.5 % OutputVoltage for 48V and 50.4V AT8/AU8 Junction Temperature: -40 to +125°C -0.8 - 0.8 % OutputVoltage for 42V and 46.2V AT8/AU8 Junction Temperature: -40 to +125°C -0.8 - 0.8 % OutputVoltage for 33.6V and 37.8V AT8/AU8 Junction Temperature: -40 to +125°C -0.9 - 0.9 % OutputVoltage for 25.2V and 29.4V AT8/AU8 Junction Temperature: -40 to +125°C -0.9 - 0.9 % OutputVoltage for 16.8V and 21V AT8/AU8 Junction Temperature: -40 to +125°C -1.4 - 1.4 % OutputVoltage for 8.4V and 12.6V AT8/AU8 Junction Temperature: -40 to +125°C -1.6 - 1.6 % Input Voltage Regulation Accuracy - Input Voltage Register = 4.096V 3.85 - 4.3 V Output Current Regulation, Rs2 = 5mΩ (Limits apply across temperature range of 0°C to +85°C) Output Current Accuracy - VCSOP - VCSON = 30mV - 6 - A -3.5 - 3.5 % VCSOP - VCSON = 25mV - 5 - A -3.85 - 3.85 % VCSOP - VCSON = 20mV - 4 - A -4 - 4 % VCSOP - VCSON = 15mV - 3 - A -5.2 - 5.2 % VCSOP - VCSON = 10mV - 2 - A -6 - 6 % VCSOP - VCSON = 5mV - 1 - A -12 - 12 % VCSOP - VCSON = 2.5mV - 0.5 - A -27 - 27 % VCSOP - VCSON = 1.28mV - 0.256 - A -52 - 52 % ASGATE Clamp VADP - VASGATE ON - - - 10 - V VADP - VASGATE OFF - - - 0 - V Operating conditions: ADP = CSIP = CSIN = 5V, 28V, and 48V, VOUTS1 = VOUTS2 = CSOP = CSON = 8V, 29.4V, and 50.4V, unless otherwise noted. Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified. Parameter Symbol Test Conditions Min[1] Typ Max [1] Unit

R16DS0426EU0101 Rev.1.01 Page 13 May 13, 2025 RRB86848 Datasheet AMON/BMON Input Current Sense Amplifier, Rs1 = 10mΩ CSIP/CSIN Input Voltage Range - - 4 - 54 V Forward AMON Gain - - - 17.97 - V/V Forward AMON Accuracy VAMON = 17.97 x (VCSIP - VCSIN) VCSIP - VCSIN = 50mV (5A), CSIP = 5V, 28V, 48V -2.8 - 2.8 % VCSIP - VCSIN = 30mV (3A), VCSIP = 5V, 28V, 48V -5 - 5 % VCSIP - VCSIN = 10mV (1A), VCSIP = 5V, 28V, 48V -10 - 10 % VCSIP - VCSIN = 5mV (0.5A), VCSIP = 5V, 28V, 48V -16.8 16.8 % VCSIP - VCSIN = 1mV (0.1A), VCSIP = 5V, 28V, 48V -78.8 - 78.8 % Reverse AMON Gain - - - 17.9 - V/V Reverse AMON Accuracy VAMON = 17.9 x (VCSIP - VCSIN) VCSIN - VCSIP = 50mV (5A), VCSIP = 5V, 28V, 48V -5 - 5 % VCSIN - VCSIP = 40mV (4A), VCSIP = 5V, 28V, 48V -6 - 6 % VCSIN - VCSIP = 30mV (3A), VCSIP = 5V, 28V, 48V -7 - 7 % VCSIN - VCSIP = 10mV (1A), VCSIP = 5V, 28V, 48V -18 - 18 % VCSIN - VCSIP = 5mV (0.5A), VCSIP = 5V, 28V, 48V -35 - 35 % VCSIN - VCSIP = 2.56mV (0.256A), CSIP = 5V, 28V, 48V -70 - 70 % AMON Minimum Output Voltage - VCSIP - VCSIN = 0V - - 30 mV Output Current Sense Amplifier, Rs2 = 5mΩ Reverse BMON Gain - - - 17.97 - V/V BMON Accuracy VBMON = 17.97× (VCSON - VCSOP) VCSON - VCSOP = 50mV (10A), VCSON - VCSOP = 25mV (5A), VCSON = 8V, 29.4V, 50.4V -5 - 8 % VCSON - VCSOP = 15mV (3A), VCSON = 8V, 29.4V, 50.4V -8 - 12 % VCSON - VCSOP = 10mV (2A), VCSON = 8V, 29.4V, 50.4V -11.5 - 17 % VCSON - VCSOP = 5mV (1A), VCSON = 8V, 29.4V, 50.4V -23 - 34 % VCSON - VCSOP = 3mV (0.6A), VCSON = 8V, 29.4V, 50.4V -39 - 55 % Operating conditions: ADP = CSIP = CSIN = 5V, 28V, and 48V, VOUTS1 = VOUTS2 = CSOP = CSON = 8V, 29.4V, and 50.4V, unless otherwise noted. Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified. Parameter Symbol Test Conditions Min[1] Typ Max [1] Unit

R16DS0426EU0101 Rev.1.01 Page 14 May 13, 2025 RRB86848 Datasheet Output Current Sense Amplifier, Rs2 = 5mΩ (Limits apply across the temperature range of 0°C to +85°C) Forward BMON Gain - - - 35.78 - V/V BMON Accuracy VBMON = 35.78 x (VCSOP - VCSON) VCSOP - VCSON = 30mV (6A), VCSOP - VCSON = 25mV (5A), VCSOP - VCSON = 20mV (4A), VCSON = 8V, 29.4V, 50.4V -5 - 5 % VCSOP - VCSON = 15mV (3A), VCSOP - VCSON = 5mV (1A), VCSON = 8V, 29.4V, 50.4V -16 - 16 % VCSOP - VCSON = 2.5mV (0.5A), VCSON = 8V, 29.4V, 50.4V -30 - 30 % VCSOP - VCSON = 1.28mV (0.256A), VCSON = 8V, 29.4V, 50.4V -60 - 60 % BMON Minimum Output Voltage - VCSOP - VCSON = 0V - - 31 mV AMON/BMON Source Resistance[2] - - - - 5 Ω AMON/BMON Sink Resistance[2] - - - - 5 Ω OTGEN High-Level Input Voltage - - 0.9 - - V Low-Level Input Voltage - - - - 0.4 V Pull-Down Current - OTGEN = 5V - 5 - µA OTG OTG Voltage - OTGVoltage register = 5.004V 4.9 5.03 5.15 V OTG Current - OTGCurrent register = 512mA, (OTGVoltage = 5.004V, 28.008V, 48.024V) 350 512 690 mA OTGCurrent register = 1024mA, (OTGVoltage = 5.004V, 28.008V, 48.024V) 870 1024 1200 mA OTGCurrent register = 1536mA, (OTGVoltage = 5.004V, 28.008V, 48.024V) 1370 1536 1726 mA OTGCurrent register = 3072mA, (OTGVoltage = 5.004V, 28.008V, 48.024V) 2841 3072 3314 mA OTGCurrent register = 4096mA, (OTGVoltage = 5.004V, 28.008V, 48.024V) 3858 4096 4350 mA OTGCurrent register = 5024mA, (OTGVoltage = 5.004V, 28.008V, 48.024V) 4750 5024 5300 mA General Purpose Comparator General Purpose Comparator Rising Threshold Reference = 1.2V 1.15 1.24 1.33 V Reference = 2V 1.93 2 2.05 V General Purpose Comparator Hysteresis - Reference = 1.2V - 55 - mV Reference = 2V - 55 - mV Operating conditions: ADP = CSIP = CSIN = 5V, 28V, and 48V, VOUTS1 = VOUTS2 = CSOP = CSON = 8V, 29.4V, and 50.4V, unless otherwise noted. Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified. Parameter Symbol Test Conditions Min[1] Typ Max [1] Unit

R16DS0426EU0101 Rev.1.01 Page 15 May 13, 2025 RRB86848 Datasheet Protection Control3 Register bit [10:9] = 00, rising 56.9 57.6 58.3 V Control3 Register bit [10:9] = 00, hysteresis - 525 - mV Control3 Register bit [10:9] = 01, rising 44.9 45.6 46.3 V Control3 Register bit [10:9] = 01, hysteresis - 510 - mV Control3 Register bit [10:9] = 10, rising 32.9 33.6 34.3 V Control3 Register bit [10:9] = 10, hysteresis - 500 - mV Control3 Register bit [10:9] = 11, rising 23.3 24 24.7 V Control3 Register bit [10:9] = 11, hysteresis - 490 - mV VOUT Relative Overvoltage Rising Threshold - OutputVoltage register value = 8.4V 9.4 10 10.5 V OutputVoltage register value = 29.4V 30.2 31 31.7 V OutputVoltage register value = 50.4V 51.2 52 52.9 V VOUT Relative Overvoltage Hysteresis - OutputVoltage register value = 8.4V 550 800 1045 mV OutputVoltage register value = 29.4V 600 800 1000 mV OutputVoltage register value = 50.4V 550 800 1050 mV VR PGOOD UV - OutputVoltage register value = 8.4V, falling - 6.8 - V OutputVoltage register value = 8.4V, hysteresis - 780 - mV OutputVoltage register value = 29.4V, falling - 27.8 - V OutputVoltage register value = 29.4V, hysteresis - 800 - mV OutputVoltage register value = 50.4V, falling - 48.8 - V OutputVoltage register value = 50.4V, hysteresis - 830 - mV VOUT UV Falling Threshold - Control6 register Bit[2:0] = 001 - 3 - V Control6 register Bit[2:0] = 010 - 3.9 - V Control6 register Bit[2:0] = 011 - 4.8 - V Control6 register Bit[2:0] = 100 - 5.7 - V Control6 register Bit[2:0] = 101 - 6.6 - V Control6 register Bit[2:0] = 110 - 7.5 - V Control6 register Bit[2:0] = 111 - 8.4 - V VOUT OK Threshold - - 0.45 0.6 0.75 V VOUT OK Source Current - - - 10 - mA Over-Temperature Threshold[2] - - 140 150 160 °C Adapter Overvoltage Rising Threshold - - 56.6 57.6 58.8 V Adapter Overvoltage Hysteresis - - 390 550 760 mV OTG Undervoltage Falling OTG Undervoltage Rising Hysteresis - OTG voltage = 5.004V, 28.008V, 48.024V - 0.9 - V OTG Overvoltage Rising Operating conditions: ADP = CSIP = CSIN = 5V, 28V, and 48V, VOUTS1 = VOUTS2 = CSOP = CSON = 8V, 29.4V, and 50.4V, unless otherwise noted. Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified. Parameter Symbol Test Conditions Min[1] Typ Max [1] Unit

R16DS0426EU0101 Rev.1.01 Page 16 May 13, 2025 RRB86848 Datasheet OTG Overvoltage Falling Hysteresis - OTG voltage = 5.004V, 28.008V, 48.024V - 0.9 - V Adapter Way Overcurrent Rising Threshold - Rs1 = 10mΩ 22.3 23.1 23.9 V Oscillator Oscillator Frequency, Digital Core Only - - 0.85 1 1.15 MHz Digital Debounce Time Accuracy[2] - - -15 - 15 % Miscellaneous Switching Frequency Accuracy - COMP > 1.7V and not in period stretching -15 - 15 % ADP Discharge Current - ADP = 5V to 54V - 10 - mA VOUT Discharge Current - VOUT = 5V to 54V - 10 - mA SMBus SDA/SCL Input Low Voltage - - - - 0.6 V SDA/SCL Input High Voltage - - 1.3 - - V SDA/SCL Input Bias Current - - - - 1 µA SDA, Output Sink Current - SDA = 0.4V 4 - - mA SMBus Frequency fSMB - 10 - 400 kHz Gate Driver[2] UGATE1 Pull-Up Resistance UG1 RPU 100mA source current - 800 1200 mΩ UGATE1 Source Current UG1SRC UGATE1 - PHASE1 = 2.5V 1.3 2 - A UGATE1 Pull-Down Resistance UG1RPD 100mA sink current - 350 475 mΩ UGATE1 Sink Current UG1SNK UGATE1 - PHASE1 = 2.5V 1.9 2.8 - A LGATE1 Pull-Up Resistance LG1 RPU 100mA source current - 800 1200 mΩ LGATE1 Source Current LG1SRC LGATE1 - GND = 2.5V 1.3 2 - A LGATE1 Pull-Down Resistance LG1RPD 100mA sink current - 300 475 mΩ LGATE1 Sink Current LG1SNK LGATE1 - GND = 2.5V 2.3 3.5 - A LGATE2 Pull-Up Resistance LG2 RPU 100mA source current - 800 1200 mΩ LGATE2 Source Current LG2SRC LGATE2 - GND = 2.5V 1.3 2 - A LGATE2 Pull-Down Resistance LG2RPD 100mA sink current - 300 475 mΩ LGATE2 Sink Current LG2SNK LGATE2 - GND = 2.5V 2.3 3.5 - A UGATE2 Pull-Up Resistance UG2 RPU 100mA source current - 800 1200 mΩ UGATE2 Source Current UG2SRC UGATE2 - PHASE2 = 2.5V 1.3 2 - A UGATE2 Pull-Down Resistance UG2RPD 100mA sink current - 350 475 mΩ UGATE2 Sink Current UG2SNK UGATE2 - PHASE2 = 2.5V 1.9 2.8 - A UGATE1 to LGATE1 Dead Time tUG1LG1DEAD - 10 20 40 ns LGATE1 to UGATE1 Dead Time tLG1UG1DEAD - 10 20 40 ns Operating conditions: ADP = CSIP = CSIN = 5V, 28V, and 48V, VOUTS1 = VOUTS2 = CSOP = CSON = 8V, 29.4V, and 50.4V, unless otherwise noted. Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified. Parameter Symbol Test Conditions Min[1] Typ Max [1] Unit

3.5 SMBus Timing Specification

3.6 Gate Driver Timing Diagrams

Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

Values or limits established by characterization and are not production tested.
Limits established by characterization and are not production tested.

Figure 6. Gate Driver Timing Diagram otherwise noted. Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified.

General SMBus Architecture

5.1 Data Validity

condition. The HIGH or LOW state of the data line can change only when the clock signal on the SCL line is LOW.

5.2 START and STOP Conditions

In Figure 25, the START condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. sent before each START condition. Figure 23. General SMBus Figure 24. Data Validity Figure 25. Start and Stop Waveforms

5.3 Acknowledge

5.4 SMBus Transactions

target is not ready to communicate, the data line remains high indicating a not acknowledged condition. RRB86848 receives a register address byte, it responds with an acknowledge.

5.5 Byte Format

the HI Byte data. For example, when writing 0x41A0, 0xA0 is written first and 0x41 is written second.

5.6 SMBus and I 2C Compatibility

Figure 26. Acknowledge On The SMBus Figure 27. SMBus Read and Write Protocol

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5.7 SMBus Commands

The RRB86848 receives control inputs from the SMBus interface after Power-On Reset (POR). The serial interface complies with the System Management Bus Specification. The RRB86848 uses the SMBus Read-word and Write-word protocols (see Figure 27) to communicate with the host system or a smart battery. RRB86848 is an SMBus target device and does not initiate communication on the bus. It responds to the 7-bit address 0b0001001_ as follows: The Read and Write address for RRB86848 is: ▪ Read address = 0b00010011 (0X13H) ▪ Write address = 0b00010010 (0X12H) The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Select pull-up resistors for SDA and SCL to achieve rise times according to the SMBus specifications.

6.1 Register Summary

Table 1. Register Summary

The default value for the VOUT UV depends on whether powering up from the adapter side or from the VOUT side.

6.2 DAC Register Summary

Table 2. DAC Summary Table[1]

Each of the DAC registers accepts any value, but only the valid register bits are written to the register, and the voltage or current value is clamped at the indicated maximum. The RRB86848 accepts a 0V

command for the OutputVoltage register, but the register value does not change.

6.3 Control Registers

appropriate control registers using the Write-word protocol shown in Figure 27. Table 3. Control0 Register 0x39H Bits[15:13] adjust the phase comparator threshold offset for the forward buck mode. boost, and reverse boost modes. Bit[2] enables or disables the input voltage regulation loop.

Table 4. Control1 Register 0x3CH Bits[15:14] configure the general-purpose comparator assertion debounce time. [12] Reserved Must remain in default state of 0. If Control1 register is written, ensure this bit is written as a 0. Bit[11] enables or disables the OTG function. Bit[10] enables or disables the audio filter function. Control1 Bits[9:8] and Control4 Bit[11] configure the switching frequency. Bit[5] enables or disables the current monitor function AMON and BMON. Bit[4] selects AMON or BMON as the AMON/BMON pin output.

Table 5. Control2 Register 0x3DH RRB86848 receives the OTG enable command until OTG switching begins. Bit[12] enables or disables the two-level adapter current limit function. Bit[11] configures the debounce time from adapter insertion to when ACOK is asserted high. Bits[8:6] configure the minimum duration of the ALERT# signal when asserted. Bit[5] turns the ASGATE FET on or off in OTG mode. Bit[4] configures the general-purpose comparator reference voltage. Note: The 2V CMIN reference is not available in forward or reverse sleep modes. Bit[3] enables or disables the general-purpose comparator. reference voltage is connected to the inverting input node. Bit[1:0] configures the Pass-Through Mode (PTM).

Table 6. Control3 Register 0x4CH Bit[15] specifies whether to reread the PROG pin resistor. [14] Reserved Must remain in default state of 0. If Control3 register is written, ensure this bit is written as a 0. Bits[12:11] configure the SMBus output current limit timeout time. Bit[6] configures AC and CC feedback gain for high current. Bit[3] configures the AMON/BMON direction. Bit[2] resets all SMBus registers to their POR default values. Control3 Bit[1] and Control4 Bit[8] configure the Buck-Boost stretch CCM period (T2 time). [0] OTG Start-Up Delay Refer to the description of Control2[13] in Table 5.

Table 7. Control4 Register 0x4EH Bits[15:14] disable or select the switching frequency dithering function. Bit[13] enables or disables the ADP discharge function. Typical 10mA. Bit[12] enables or disables the VOUT discharge function. Typical 10mA. [11] Switching Frequency Refer to the description of Control1 Bits[9:8] in Table 4. Bit[10] selects the minimum T3 time when in the buck-boost mode. Bit[9] selects the buck-boost T2 time in the discontinuous-conduction mode (DCM). Period Refer to the description of Control3 Bit[1] in Table 6. Bit[5] enables or disables ALERT# trigger with ACOK. Bit[4] enables or disables ALERT# trigger with General Purpose Comparator rising. Bits[3:2] configure the debounce time from ACOK falling to ALERT# activation. Bit[0] manually resets ALERT#. Table 8. Control5 Register 0x38H

Bit[7] enables or disables the 0.6V comparator. Bit[6] enables or disables the 10mA current source. Bit[5] selects the signal routed to the PGOOD/CMOUT pin. Bit[4] enables or disables VOUT and OTG overvoltage protections. Table 9. Control6 Register 0x37H Bit[6] enables or disables the slew rate control for output current, output voltage, and OTG voltage. voltage, 0.5mA/µs for output current with Rs2 = 5mΩ, and 1.125mV/µs for OTG voltage. Bit[4] when Control6[3] = 0 (CMOUT Latch is enabled).

6.4 Information Registers

following tables identify the bit locations of the available information. Bit[3] enables or disables the CMOUT latch function. Bits[2:0] set VOUT under voltage threshold. re-reading by setting Control register 3 Bit[15]. Table 10. Control7 Register 0x36H Bit[15] forces the ASGATE driver to turn off the ASFETs when in Forward Mode. external regulator provides the power. Bit[2] disables the High-Power LDO when an over-temperature event is detected. Table 11. Information1 Register 0x3AH Bits[14:13] indicate the active control loop.

Table 12. Information2 Register 0x4DH Bit[15] indicates the state of pin 30 at POR. Bit[14] indicates the ACOK pin status. Bit[13] indicates the general-purpose comparator output after debounce time. Bits[11:8] indicate the RRB86848 state machine status. Bits[7:5] indicate the RRB86848 operation mode. Table 13. Information3 Register 0x90H Bit[1] indicates the Pass-Through Mode (PTM) status.

7.1 RRB86848 Buck-Boost Converter Modes of Operation

from a voltage input lower than the output voltage. changes accordingly to accommodate the duty cycle change because of the power loss on the charger circuit. from Buck-Boost mode to Boost mode. Table 14. Operation Mode Figure 28. Buck-Boost Converter Topology

window, so the RRB86848 operates in Buck-Boost mode when VADP is lower than VOUT + 240mV. recommended in 2-FET Buck mode.

7.2 USB On-the-Go (USB OTG)

Reverse Buck-Boost mode, and Control2 Bit[5] controls ASGATE. Bit[5] can also turn the ASGATE FET off to cut off the OTG output. threshold (OTG Voltage DAC(0x49h) + 1.8V). The CSIP pin is the output sensing point in OTG mode. register 0x4A sets the OTG output current limit, and defaults to 480mA with an Rs1 of 10mΩ. OTG output voltage -1.8V and the OVP threshold is the OTG output voltage +1.8V. Figure 29. Operation Mode

disable PROG pin rereading by setting Control3 register Bit[15].

7.3 Pass-Through Mode

still active. Note: The PGOOD signal is not applicable in PTM. Note: The adapter current comparator is disabled for 1ms after Q1 and Q4 latch on to enter PTM. Forced PTM can only be exited by disabling PTM using Control2 Bits[1:0]. ▪ Enable slew rate limiting by setting Control6 Bit[6] = 1. ▪ Set the OutputVoltage DAC to a value as close to the VADP voltage as possible.

7.4 Modulator Control Loops

provide settings as required for each system. Figure 30. Converter Control Loops

7.4.1 Adapter Current Loop and Two-Level Current Limit

Table 2 for the DAC summary of values. current sense resistor of 10mΩ, the DAC LSB translates to 8mA of adapter current. The AdapterCurrentLimit2 register has the same specification as the AdapterCurrentLimit1 register. temporarily output surge current. The AdapterCurrentLimit1 register value can be higher or lower than the AdapterCurrentLimit2 value. Figure 31. Two-Level Adapter Current Limit

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7.4.2 Input Voltage Regulation Loop

7.4.2.1 Adapter Minimum Voltage

The input voltage regulation register DAC (Table 2) contains the SMBus readable and writable input voltage reference at which the input voltage loop tries to regulate when the input voltage is dropping. When the ADP is browning out or weak, the input voltage can droop. The input voltage loop regulates to the minimum input voltage register setting by reducing the output current. The output voltage might start to drop if the input power is not high enough to support the load.

7.4.2.2 USB-PD On-the-Go Minimum VOUT Voltage

The input voltage regulation register DAC (Table 2) sets a minimum voltage for VOUT when operating in OTG mode. Control5 register Bit[11] enables and disables the VOUT regulation loop. This regulation loop can be used to prevent exceeding the power rating of a source connected to VOUT when operating in OTG mode. The VOUTS2 pin serves as the sensing point for the OTG input voltage regulation loop.

7.4.3 USB-PD On-the-Go Output Voltage

The OTG output voltage regulation register DAC (Table 2) contains the SMBus readable and writable voltage reference for the OTG voltage loop. This loop reuses the input voltage sense amp. This register accepts any voltage value, but only the valid register bits are written to the register. The maximum value is clamped.

7.4.4 USB-PD On-the-Go Output Current

The OTG output current regulation register DAC (Table 2) contains the SMBus readable and writable current reference for the OTG current sense loop. This loop uses the same input current sense amplifier as used in forward mode. The USB-PD Programmable Power Supply (PPS) uses the OTG current sense loop to set the OTG PPS current. Note: Renesas recommends disabling OTG undervoltage protection when OTG current limiting mode is anticipated as part of normal operation.

7.4.5 Output Voltage Regulation

The OutputVoltage DAC sets the regulation target for the output voltage in forward mode. Write a 16-bit OutputVoltage command to register 0x15, using the Write-word protocol shown in Figure 27, to configure the output voltage. The VOUTS1 pin is the output voltage regulation sense point. The OutputVoltage DAC accepts any value, but only the valid register bits are written, and the voltage value is clamped at the maximum described in Table 2.

7.4.6 Output Current Loop

This loop uses the output current DAC (see Table 2) to set the output current limit. To set it, write a 16-bit OutputCurrentLimit command to register address 0x14H (Table 1). RRB86848 limits the output current by limiting the CSOP - CSON voltage. Therefore, the output current depends on the Rs2 resistor value. For example, if the current sense resistor Rs2 is halved, the regulated output current doubles. By using the current sense resistor Rs2 = 5mΩ, the DAC LSB translates to 8mA of output current. The OutputCurrentLimit register accepts any output current value, but only the valid register bits are written to the register.

7.4.6.1 Reverse Mode Input Current

When the converter operates in reverse mode (OTG), there is a reverse-mode input current limit loop that is set to 2x the forward OutputCurrentLimit register (0x14). This reverse-mode input current limit loop is in addition to the voltage regulation loop set by the OTG Voltage register, the current limit loop set by the OTG Current register, and the optional OTG input voltage regulation loop set by the Input Voltage register. The reverse-mode input current limit loop is disabled when OutputCurrentLimit (0x14) is zero. When the output current setting is a non-zero value,

7.5 R3 Modulator

shortcomings. Figure 32 conceptually shows the R3 modulator circuit. Figure 33 shows the operation principles in a steady state. on the PWM pulse when it reaches COMP . lower phase jitter than conventional hysteretic mode modulator. Figure 32. R3 Modulator Figure 33. R3 Modulator Operation Principles in Steady State

increase light-load efficiency.

8.1 Soft-Start

and VOUT voltages, is described in this section. input. Use an R-C filter to generate the VDDP pin voltage from the VDD pin voltage. the input bus short check, ASGATE starts turning on with 10µA of sink current. asserted, RRB86848 starts switching. to the output bus. The RRB86848 actively pulls ACOK low in the absence of the adapter. Figure 36. Period Stretching

to determine the PROG resistor value. The PROG resistor programs the configurations of the RRB86848.

8.2 Programming Options

value, and the OutputCurrentLimit. Table 15 shows the programming options. switching frequency to 377kHz, which decreases the MOSFET gate drive current from VDDP . so the PROG pin voltage can rise to steady state before the RRB86848 reads it. By default, the adapter current sensing resistor Rs1 is 10mΩ and the output current sensing resistor Rs2 is 5mΩ. Using this R1 = 10mΩ and Rs2 = 5mΩ option results in an 8mA/LSB correlation in the SMBus current commands. Table 15. PROG Pin Programming Options

8.3 PGOOD

comparator output, set Control5 register Bit[5] to 1. high when VOUT is back inside the hysteresis window. Figure 38 explains this transition behavior in detail. Figure 37. PGOOD Window Behavior Figure 38. PGOOD VOUT DAC Transition

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8.4 Low Power Modes

8.4.1 Forward Sleep Mode

To achieve low quiescent current when an adapter is attached, enable Forward Sleep Mode by setting Control5 register Bit[3]. This disables switching, the high-power LDO, and many of the internal circuits. To achieve the lowest quiescent current in this state, disable the current monitor and general-purpose comparator as follows: ▪ Disable AMON/BMON ‒ Control1 register (0x3C) Bit[5] = 1 ▪ Disable GP comparator ‒ Control2 register (0x3D) Bit[3] = 1

8.4.2 Reverse Sleep Mode

When no adapter is attached but power is applied at VOUT, switching is disabled by default and many of the internal circuits are not powered. In this Reverse Sleep Mode configuration, the high-power LDO is disabled and the low-power LDO supplies a VDD of 4.5V. To achieve the lowest quiescent current in this state, disable the current monitor and general-purpose comparator as follows: ▪ Disable AMON/BMON ‒ Control1 register (0x3C) Bit[5] = 1 ▪ Disable GP comparator ‒ Control2 register (0x3D) Bit[3] = 1

8.5 Diode Emulation Operation

In Diode Emulation (DE) mode, RRB86848 uses a phase comparator to monitor the PHASE node voltage during the low-side switching FET on-time to detect the inductor current zero crossing. The phase comparator requires a minimum on-time of the low-side switching FET to recognize inductor current zero crossing. If the low-side switching FET on time is too short for the phase comparator to successfully recognize the inductor zero crossing, RRB86848 can lose DE ability. To prevent this, RRB86848 uses a minimum low-side switching FET on time. When the intended low-side switching FET on-time is shorter than the minimum value, RRB86848 stretches the switching period to keep the low-side switching FET on-time at the minimum value, which causes the CCM switching frequency to drop below the set point.

8.6 Monitoring

8.6.1 Current Monitor

RRB86848 provides an adapter current monitor/OTG output current monitor, or a forward output current monitor/OTG input current monitor through the AMON/BMON pin. The AMON output voltage is 18x (CSIP - CSIN) and 18x (CSIN - CSIP) voltage. The BMON output voltage is 36x (CSOP - CSON) and 18x (CSON- CSOP) voltage. The AMON and BMON functions can be enabled or disabled through SMBus Control1 register Bit[5]. AMON or BMON can be selected through SMBus Control1 register Bit[4] and the AMON/BMON direction can be configured through SMBus Control3 register Bit[3] as Table 4 describes.

8.6.2 ALERT#

RRB86848 provides an open-drain ALERT# signal to indicate adapter removal or general-purpose comparator triggering. The ALERT# feature is disabled by default. To enable the adapter removal ALERT#, set Control4 register Bit[5]. With this ALERT# input enabled, the ALERT# signal is asserted (driven low) when ACOK goes low, which indicates no adapter. To enable the general-purpose comparator ALERT#, set Control4 register Bit[4]. With this ALERT# input enabled, the ALERT# signal is asserted (driven low) when the comparator is triggered. The debounce time for the ACOK ALERT# trigger is set by Control4 register Bits[3:2]. While the general-purpose comparator ALERT# signal has no dedicated debounce setting, the comparator itself has a debounce time that

8.7 General-Purpose Comparator

configured through the SMBus register bit. CMOUT = Low if CMIN < Reference. CMOUT = High if CMIN < Reference. general-purpose comparator must be disabled if OTG is to be enabled using the OTGEN/CMIN pin. the 2V comparator reference is not available and should not be configured. Table 16 shows the OTG mode and the general-purpose comparator truth table. Table 16. OTG and Comparator Truth Table without OTG power-good pin indication. Information1 register 0x3A Bit[6:5] = 11. Control1 register Bit[11] = 1.

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8.8 Protections [1]

8.8.1 Adapter Overvoltage Protection

If the ADP pin voltage exceeds 57.6V for more than 10µs, an adapter overvoltage condition occurs. RRB86848 turns off the ASGATE MOSFETs to isolate the adapter from the system, de-asserts the ACOK signal by pulling it low, and stops switching. When the ADP voltage drops below 57.05V from more than 100µs, it starts to turn on ASGATE and start switching.

8.8.2 Output Overvoltage Protection

RRB86848 provides VOUT relative overvoltage protection. If the sensed output voltage VOUTS1 is 1.6V higher than the OutputVoltage register set value, it declares the output overvoltage and stops switching. It resumes switching, with no debounce time, when VOUTS1 drops 800mV below the output overvoltage threshold. RRB86848 also provides VOUT absolute overvoltage protection. The default absolute overvoltage rising threshold is 57.6V. If the sensed output voltage VOUTS1 is higher than 57.6V, switching stops. When VOUTS1 drops to lower than 57.08V, switching restarts. The absolute overvoltage protection threshold can be modified using Control3 register Bits[10:9] to support USB-C voltages of 36V, 28V, or 20V.

8.8.3 Output Voltage Rail Short Protection

The RRB86848 has an output rail short protection (VOUTOK) to prevent powering on the output rail into a short-circuit before switching starts. When the VOUTS1 voltage is below 0.6V, the RRB86848 sources 10mA current (by default) from VDDP to charge VOUT before switching can start. Renesas recommends ensuring that there is no load on VOUT at startup. From the beginning of VOUTOK (VOUT rail short protection) to the start of switching in the VOUT state, the RRB86848 must go through multiple startup and initialization transition states, including turning on ASGATE FET. This initialization transition duration might take longer than it takes to charge the VOUT voltage to 0.6V using a 10mA source by the VOUTOK function. If this initialization transition duration is longer than the duration of charging VOUT above 0.6V, the charger must wait until the transition duration is completed before switching starts, and vice versa. Conversely, the duration of charging VOUT above 0.6V, which depends on the leakage current and capacitance value at VOUT, varies per individual system design. If estimating the duration in a worst-case scenario is required, Renesas recommends testing the design to determine the following: ▪ If the initialization transition duration is longer than the duration of charging VOUT above 0.6V, add a 30% margin (considering ±15% clock tolerance) to estimate worst-case duration. ▪ If the initialization transition duration is shorter than the duration of charging VOUT above 0.6V, check the tolerance of the VOUT capacitance or leakage current from VOUT downstream circuitry and then add a reasonable margin, such as 40% (considering ±20% cap tolerance), to estimate worst-case duration. After switching starts, the charger enters the Fault state if VOUT drops below 0.6V again at any time. After entering the Fault State, the charger stops switching and turns off ASGATE and tries to start again with 1.3s or 150ms debounce time (configured by Control 2[11]). After the initial POR, the VOUT rail short protection check can optionally be bypassed by disabling both the VOUTOK 0.6V Comparator using Control5 Bit[7] and the VOUTOK 10mA current source using Control5 Bit[6].

8.8.4 Output Voltage Undervoltage Protection (for Short-Circuit Protection)

The converter has a fixed undervoltage protection on the output side that can be configured using Control 6[2:0]. The initial value of the VOUT undervoltage is set as follows: ▪ POR from VOUT: VOUT UV is 000 = disabled, ▪ POR from adapter: VOUT UV is 001 = 3.0V. 1. Nominal protection values are provided in this section. Refer to the Electrical Specifications for accurate values.

R16DS0426EU0101 Rev.1.01 Page 47 May 13, 2025 RRB86848 Datasheet When the VOUTS1 voltage falls to the VOUT UV threshold set by Control 6[2:0], there is a 100ms debounce before the converter enters FAULT state. After entering FAULT state, there is no switching, and the converter tries to start switching again after the 150ms or 1.3s debounce time (configurable by Control 2[11]).

8.8.5 Over-Temperature Protection

RRB86848 stops switching for self-protection when the junction temperature exceeds +150°C. When the temperature falls below +130°C and after a 100µs delay, RRB86848 resumes switching.

8.9 Power Source

RRB86848 uses the adapter to provide power in forward mode and uses VOUT to provide power in reverse mode. The ASGATE pin drives a pair of back-to-back common source P-channel MOSFETs to connect/disconnect the adapter. Use of the ASGATE pin is optional. When the output voltage, as detected at VOUTS2, is higher than 2.4V and the adapter voltage VADP is less than 3.4V, RRB86848 operates in reverse sleep mode, during which very little power is consumed. (Refer to the Reverse Supply Current specification.) The OTG input current monitor BMON can be turned on during this mode to monitor the current consumption. From reverse sleep mode, the OTG function can be enabled provided that the output voltage VOUTS2 (OTG input voltage) is higher than 4.5V. After OTG is enabled, reverse sleep mode is exited. See USB On-the-Go (USB OTG) for details. When the adapter voltage VADP is more than 3.4V, RRB86848 turns on ASGATE. If VDD is higher than 3.8V, the RRB86848 enters Forward Buck, Forward Boost, or Forward Buck-Boost mode depending on the ratio of the adapter voltage to the VOUT voltage. The output bus voltage is regulated at the voltage set on the OutputVoltage register. 9. Design Guidelines This design guide provides a high-level explanation of the steps necessary to design a single-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following sections. In addition to this guide, Renesas provides complete reference designs that include schematics, bill of materials, and example board layouts.

9.1 Selecting the LC Output Filter

The duty cycle of an ideal buck converter in CCM is a function of the input and the output voltage. This relationship is written by Equation 1: Use Equation 2 to calculate the output inductor peak-to-peak ripple current: A typical step-down DC/DC converter has an IP-P of 20% to 40% of the maximum DC output load current for a practical design. The value of IP-P is selected based on several criteria such as MOSFET switching loss, inductor core loss, and the resistive loss of the inductor winding. Use Equation 3 to estimate the DC copper loss of the inductor, where ILOAD is the converter output DC current. (EQ. 1) (EQ. 2) (EQ. 3) D VOUT VIN IP-P VOUT 1 D–  fSW L PCOPPER ILOAD

2 DCR=

is its saturation characteristics at elevated temperatures. A saturated inductor can destroy circuit components. the rated value of a capacitor can fade as much as 50% as the DC voltage across it increases.

9.2 Selecting the Input Capacitor

cycle and is adjusted for converter efficiency. Figure 39. Normalized RMS Input Current at EFF = 1

8 C O f

R16DS0426EU0101 Rev.1.01 Page 49 May 13, 2025 RRB86848 Datasheet Use Equation 6 to calculate the normalized RMS ripple current calculation: where: ▪ I MAX is the maximum continuous ILOAD of the converter. ▪ k is a multiplier (0 to 1) corresponding to the inductor peak-to peak ripple amplitude expressed as a ratio of IMAX (0 to 1) ▪ D is the duty cycle that is adjusted to consider the efficiency of the converter, which is calculated using Equation 7: In addition to any bulk capacitance, some low ESL ceramic capacitance is recommended to decouple between the drain of the high-side MOSFET and the source of the low-side MOSFET.

9.3 Selecting the Switching Power MOSFET

Typically, a MOSFET cannot tolerate even brief excursions beyond its maximum drain-to-source voltage rating. The MOSFETs used in the power stage of the converter should have a maximum VDS rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltage spike that occurs when the MOSFET switches off. Several power MOSFETs that are optimized for DC/DC converter applications are readily available. The preferred high-side MOSFET emphasizes low gate charge so that the device spends the least amount of time dissipating power in the linear region. Unlike the low-side MOSFET, which has the drain-to-source voltage clamped by its body diode during turn off, the high-side MOSFET turns off with a VDS of approximately VIN - VOUT, plus the spike across it. The preferred low-side MOSFET emphasizes low rDS(ON) when fully saturated to minimize conduction loss. Note: This is an optimal configuration of MOSFET selection for low duty cycle applications (D < 50%). For higher output, low input voltage solutions, a more balanced MOSFET selection for high-side and low-side devices might be required. The power loss of the Low-Side (LS) MOSFET can be assumed to be conductive only and is calculated using Equation 8: Use Equation 9 to calculate the conduction loss of the High-Side (HS) MOSFET: Use Equation 10 to calculate the switching loss of the HS MOSFET: where: ▪ I VALLEY is the difference of the DC component of the inductor current minus 1/2 of the inductor ripple current. ▪ I PEAK is the sum of the DC component of the inductor current plus 1/2 of the inductor ripple current. ▪ t SW(ON) is the time required to drive the device into saturation. ▪ t SW(OFF) is the time required to drive the device into cut-off. (EQ. 6) (EQ. 7) (EQ. 8) (EQ. 9) (EQ. 10) ICIN RMS NORMALIZED,  IMAX D VOUT PCON_LS ILOAD PCON_HS ILOAD PSW_HS VIN IVALLEY tSWON f SW VIN IPEAK tSWOFF f SW

R16DS0426EU0101 Rev.1.01 Page 50 May 13, 2025 RRB86848 Datasheet

9.4 Selecting the Bootstrap Capacitor

The selection of the bootstrap capacitor is written by Equation 11: where: ▪ Q g is the total gate charge required to turn on the high-side MOSFET ▪ ∆V BOOT is the maximum allowed voltage decay across the boot capacitor each time the high-side MOSFET is switched on. As an example, suppose the HS MOSFET has a total gate charge Qg, of 25nC at VGS = 5V and a ∆VBOOT of 200mV. The calculated bootstrap capacitance is 0.125µF; for a comfortable margin, select a capacitor that is double the calculated capacitance. In this example, 0.22µF is sufficient. Use an X7R or X5R ceramic capacitor. Renesas recommends using a bootstrap capacitor of 0.47µF (25V), which has an effective capacitance higher than 0.25µF at 5V and x50 effective high-side MOSFET gate capacitance.

9.5 Switching Power MOSFET Gate Capacitance

The RRB86848 includes an internal 5V LDO output at the VDD pin, which can provide the switching MOSFET gate driver power through the VDDP pin with an RC filter. The 5V LDO output overcurrent protection threshold is 85mA, minimal (check EC table for the accurate value). When selecting the switching power MOSFET, consider the MOSFET gate capacitance carefully to avoid overloading the 5V LDO, especially in Buck-Boost mode when four MOSFETs are switching at the same time. For one MOSFET, use Equation 12 to estimate the gate drive current: where: ▪ Q g is the total gate charge, which can be found in the MOSFET datasheet. ▪ f SW is the switching frequency. Renesas recommends using a 2.2µF (10V) VDD/VDDP capacitor, which has an effective capacitance higher than 0.4µF at 5V and x1.6 effective capacitance at the BOOT pin at 5V.

9.6 VDD Voltage Supply

When high voltages, such as 36V or more, are expected at VADP or VOUT, Renesas recommends generating a 5.5V bias voltage using a DC/DC supply external to the RRB86848. When overdriving VDD with such a bias voltage, the LDO output should be set to 4.5V using Control7 register Bit[3]. This approach provides a highly efficient bias supply. For applications with low expected VADP and VOUT voltages, the DCIN input pin can be driven from an external OR-ing diode circuit having VADP and VOUT as inputs, and the internal LDO can supply VDD and VDDP . Such an approach requires minimal external components. When using the internal LDO, the DCIN input should be filtered by connecting a 10Ω resistor between the DCIN pin and the VADP/VOUT diodes, and connecting a 4.7µF DCIN capacitor to GND, which has an effective capacitance higher than 0.4µF at 48V.

9.7 Adapter Input Filter

The adapter cable parasitic inductance and capacitance can cause some voltage ringing or an overshoot spike at the adapter connector node when the adapter is hot plugged in. This voltage spike can damage the ASGATE MOSFET or the RRB86848 pins connecting to the adapter connector node. One low-cost solution is to add an R-C snubber circuit at the adapter connector node to clamp the voltage spike as shown in Figure 40. A practical value of the R-C snubber is 2.2Ω to 2.2µF, while the appropriate values and power rating should be carefully (EQ. 11) (EQ. 12) CBOOT Qg VBOOT Idriver Qg f SW=

current path parasitic inductance. Figure 40. Adapter Input R-C Snubber Circuit connect to the PCB ground planes to ensure sufficient thermal dissipation directly under the IC. common-mode RC filter components in the general proximity of the controller. routing current sensing traces.

2 CSOP

3 VOUTS1

an external Schottky diode from VDDP to BOOT2.

R16DS0426EU0101 Rev.1.01 Page 52 May 13, 2025 RRB86848 Datasheet 5 UGATE2 Run these two traces in parallel fashion with sufficient width. Avoid any sensitive analog signal traces from crossing over or getting close. Route the PHASE2 trace to the high-side MOSFET source pin instead of general copper. Place the IC close to the gate terminals of the switching MOSFETs and keep the gate drive signal traces short for a clean MOSFET drive. The IC can be placed on the opposite side of the switching MOSFETs. Place the output capacitors as close as possible to the switching high-side MOSFET drain and the low-side MOSFET source, and use the shortest PCB trace connection. Place these capacitors on the same PCB layer with the MOSFETs instead of on different layers and using vias to make the connection. Place the inductor terminal to the switching high-side MOSFET source and low-side MOSFET drain terminal as close as possible. Minimize this phase node area to lower the electrical and magnetic field radiation but make this phase node area large enough to carry the current. Place the inductor and the switching MOSFETs on the same layer of the PCB.

6 PHASE2

7 LGATE2 Switching pin. Use sufficient width. Avoid any sensitive analog signal traces from crossing over or getting close. 8 VDDP Place the decoupling capacitor in the general proximity of the controller. Run the trace connecting to the VDD pin with sufficient width. 9 LGATE1 Switching pin. Use sufficient width. Avoid any sensitive analog signal traces from crossing over or getting close. 10 PHASE1 Run these two traces in parallel fashion with sufficient width. Avoid any sensitive analog signal traces from crossing over or getting close. Route the PHASE1 trace to the high-side MOSFET source pin instead of general copper. Place the IC close to the gate terminals of the switching MOSFETs and keep the gate drive signal traces short for a clean MOSFET drive. The IC can be placed on the opposite side of the switching MOSFETs. Place the input capacitors as close as possible to the switching high-side MOSFET drain and the low-side MOSFET source, and use the shortest PCB trace connection. Place these capacitors on the same PCB layer with the MOSFETs instead of on different layers and using vias to make the connection. Place the inductor terminal to the switching high-side MOSFET source and low-side MOSFET drain terminal as close as possible. Minimize this phase node area to lower the electrical and magnetic field radiation but make this phase node area big enough to carry the current. Place the inductor and the switching MOSFETs on the same layer of the PCB.

11 UGATE1

Switching pin. Place the bootstrap capacitor in the general proximity of the controller. Use sufficiently wide traces. Avoid any sensitive analog signal traces from crossing over or getting close. Allocate a footprint for an external Schottky diode from VDDP to BOOT1. 13 ASGATE Run this trace with sufficient width in parallel fashion with the ADP pin trace. 14 CSIN Run two dedicated traces with sufficient width in parallel (close to each other to minimize the loop area) from the two terminals of the adapter current sensing resistor to the IC. Place the Differential mode and common-mode RC filter components in the general proximity of the controller. Route the current sensing traces through vias to connect the center of the pads or route the traces into the pads from the inside of the current sensing resistor. The following drawings show the two preferred ways of routing current sensing traces. 16 ADP Run this trace with sufficient width in parallel fashion with the ASGATE pin trace. 17 DCIN Place the OR diodes and the RC filter in the general proximity of the controller. Run the VADP trace and VOUT trace to the OR diodes with sufficient width. 18 VDD Place the RC filter connecting with the VDDP pin in the general proximity of the controller. Run the trace connecting to the VDDP pin with sufficient width. Pin Number Pin Name Layout Guidelines Current Sensing Traces Vias Current Sensing Traces

R16DS0426EU0101 Rev.1.01 Page 53 May 13, 2025 RRB86848 Datasheet 11. Package Outline Drawing The package outline drawing is located at the end of this document and is accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document. 12. Ordering Information 19 ACIN Place the voltage divider resistors and the optional decoupling capacitor in the general proximity of the controller. 20 OTGEN/CMIN No special consideration.

21 SDA

Digital pins. Avoid running these traces near noisy traces. Run the SDA and SCL traces in parallel.

22 SCL

23 ALERT#

Digital pin, open-drain output. No special consideration.

24 ACOK

25 RESERVED Connect to GND. CMOUT Digital pin, open-drain output. No special consideration. 27 PROG Signal pin. Place the PROG programming resistor in the general proximity of the controller. 28 COMP Place the compensation components in the general proximity of the controller. Avoid any switching signal from crossing over or getting close. 29 AMON/BMON No special consideration. Place the optional RC filter in the general proximity of the controller. 30 RESERVED This pin should not float. Connect to either VDD or GND. 31 VOUTS2 Place the optional R-C filter in the general proximity of the controller. Run a dedicated trace from the output voltage node VOUT to the IC. Part Number[1][2] 1. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 2. The Moisture Sensitivity Level (MSL) rating is 3. For more information about MSL, see TB363. Part Marking Package Description[3] (RoHS Compliant) 3. For the Pb-Free Reflow Profile, see TB493. Pkg. Dwg # Carrier Type[4] 4. See TB347 for details about reel specifications. Temp. Range RRB86848-AT7 86848A7 32 Ld 4x4 TQFN L32.4x4D Reel, 6k -10 to +100°C RRB86848-AU7 Reel, 1k RRB86848-AT8 86848A8 Reel, 6k -40 to +100°C RRB86848-AU8 Reel, 1k RTKRB86848DE0000BU RRB86848 Evaluation Board Pin Number Pin Name Layout Guidelines

R16DS0426EU0101 Rev.1.01 Page 54 May 13, 2025 RRB86848 Datasheet 13. Revision History Revision Date Description

1.01 May 13, 2025

Updated Input Voltage maximum from 54V to 55V. Updated Output Voltage maximum from 54V to 55V. Updated Figure 4, Block Diagram. Updated Pin 31 description. In Recommend Operating Conditions, updated Adapter Voltage maximum from 54V to 55V. In Electrical Specifications, updated Test Conditions for OTG Current, OTG Undervoltage Falling Threshold, OTG Undervoltage Rising Hysteresis, OTG Overvoltage Rising Threshold, and OTG Overvoltage Falling Hysteresis. Updated 8.1, Soft-Start. Added evaluation board to the Ordering Information section.

1.00 Feb 21, 2025 Initial release

R16DS0426EU0101 Rev.1.01 Page 55 May 13, 2025 RRB86848 Datasheet A. ECAD Design Information This information supports the development of the PCB ECAD model for this device. It is intended to be used by PCB designers. A.1 Part Number Indexing A.2 Symbol Pin Information A.2.1 32-TQFN Orderable Part Number Number of Pins Package Type Package Code/POD Number RRB86848-AT7 32 TQFN L32.4x4D RRB86848-AU7 32 TQFN L32.4x4D RRB86848-AT8 32 TQFN L32.4x4D RRB86848-AU8 32 TQFN L32.4x4D Pin Number Primary Pin Name Primary Electrical Type Alternate Pin Name(s)

1 CSON Input -

2 CSOP Input -

3 VOUTS1 Input -

4 BOOT2 Power -

5 UGATE2 Output -

6 PHASE2 Power -

7 LGATE2 Output -

8 VDDP Power -

9 LGATE1 Output -

10 PHASE1 Power -

11 UGATE1 Output -

12 BOOT1 Power -

13 ASGATE Output -

14 CSIN Input -

15 CSIP Input -

16 ADP Input -

17 DCIN Power -

18 VDD Power -

19 ACIN Input -

20 OTGEN Input CMIN

21 SDA I/O -

22 SCL I/O -

23 ALERT# Output -

24 ACOK Output -

25 RESERVED Input -

26 PGOOD Output CMOUT

27 PROG Input -

28 COMP Output -

29 AMON Output BMON

30 RESERVED Input -

31 VOUTS2 Input -

32 NC Passive -

R16DS0426EU0101 Rev.1.01Page 56 May 13, 2025 RRB86848 Datasheet A.3 Symbol Parameters Orderable Part Number Qualification Mounting Type Min Input Voltage Max Input Voltage Min Output Voltage Max Output Voltage Min Operating Temperature Max Operating Temperature Max Junction Temperature (Tj) RoHS Typ Switching Frequency Switcher Configuration RRB86848-AT7 Consumer SMD 3.9 V 55 V 2.4 V 55 V -10 °C +100 °C +125 °C Yes 377 kHz Buck, Boost, and Buck-Boost RRB86848-AU7 Consumer SMD 3.9 V 55 V 2.4 V 55 V -10 °C +100 °C +125 °C Yes 377 kHz Buck, Boost, and Buck-Boost RRB86848-AT8 Industrial SMD 3.9 V 55 V 2.4 V 55 V -40 °C +100 °C +125 °C Yes 377 kHz Buck, Boost, and Buck-Boost RRB86848-AU8 Industrial SMD 3.9 V 55 V 2.4 V 55 V -40 °C +100 °C +125 °C Yes 377 kHz Buck, Boost, and Buck-Boost

R16DS0426EU0101 Rev.1.01 Page 57 May 13, 2025 RRB86848 Datasheet A.4 Footprint Design Information A.4.1 32-TQFN IPC Footprint Type Package Code/ POD number Number of Pins QFN L32.4x4D 32 Description Dimension Value (mm) Diagram Minimum body span (vertical side) Dmin 3.90 Maximum body span (vertical side) Dmax 4.10 Minimum body span (horizontal side) Emin 3.90 Maximum body span (horizontal side) Emax 4.10 Minimum Lead Width Bmin 0.15 Maximum Lead Width Bmax 0.25 Minimum Lead Length Lmin 0.25 Maximum Lead Length Lmax 0.35 Number of pins (vertical side) PinCountD 8 Number of pins (horizontal side) PinCountE 8 Distance between the center of any two adjacent pins (vertical side) PitchD 0.4 Distance between the center of any two adjacent pins (horizontal side) PitchE 0.4 Location of pin 1; S2 = corner of D side, C1 = center of E side Pin1 S2 Minimum thermal pad size (vertical side) D2min 2.6 Maximum thermal pad size (vertical side) D2max 2.8 Minimum thermal pad size (horizontal side) E2min 2.6 Maximum thermal pad size (horizontal side) E2max 2.8 Maximum Height Amax 0.8 Minimum Standoff Height A1min 0 Minimum Lead Thickness cmin 0.15 Maximum Lead Thickness cmax 0.25 Recommended Land Pattern Description Dimension Value (mm) Diagram Distance between left pad toe to right pad toe (horizontal side) ZE 4.4 Distance between top pad toe to bottom pad toe (vertical side) ZD 4.4 Distance between left pad heel to right pad heel (horizontal side) GE 3.4 Distance between top pad heel to bottom pad heel (vertical side) GD 3.4 Pad Width X 0.2 Pad Length Y 0.5 DD2 E L B PitchD PitchE Amax A1min c GE ZE GDZD Y X P

Typical Recommended Land Pattern Top View 2.70 ±0.10 2.70 ±0.10 0.08C 4.00 ±0.10 4.00 ±0.10 0.200.30 0.40 2.70 2.70 4.303.40 Package Outline 891617 2425 32 0.75 ±0.10C0.20 Ref. 0.20 0.30 © Renesas Electronics Corporation

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit www.renesas.com /contact-us/ . Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD-PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers who are designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only to develop an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third-party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising from your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Disclaimer Rev.1.01) © 2025 Renesas Electronics Corporation. All rights reserved.

Selected Specification

Renesas Technology Corp RRB86848 overview.

Summary

Bidirectional Buck-Boost Voltage Regulator with SMBus Interface for General 48V and USB PD May 13, 2025

Description

Bidirectional Buck-Boost Voltage Regulator with SMBus Interface for General 48V and USB PD May 13, 2025

Source title RRB86848 Datasheet(PDF) - Renesas Technology Corp

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