RH101A_15 LINER
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. RH101A DICE RH101A DWF DICE ELECTRICAL TEST LI ITSW TA = 25°C. VS = ±20V unless otherwise noted. PAD FUNCTION BAL/COMP –IN +IN V BAL OUT COMP 80 × 59 mils Backside (substrate) is an alloyed gold layer. May be connected to V– or no connection. 2 3 TA = 25°C SYMBOL PARAMETER CONDITIONS MIN MAX UNITS Pre-Irradiation (Note 1) VOS Input Offset Voltage R S ≤ 50k 2 mV IOS Input Offset Current 10 nA IB Input Bias Current V CM = 0V 75 nA AVOL Large Signal Voltage Gain V S = ±15V, VOUT = ±10V, RL ≥ 2k 50 V/mV CMRR Common Mode Rejection Ratio R S ≤ 50k 80 dB PSRR Power Supply Rejection Ratio R S ≤ 50k 80 dB Input Voltage Range V S = ±20V ±15 V VOUT Output Voltage Swing V S = ±15V, RL ≥ 10k ±12 V VS = ±15V, RL ≥ 2k ±10 V IS Supply Current V S = ±20V 3 mA
DICE ELECTRICAL TEST LI ITSW © LINEAR TECHNOLOGY CORPORATION 2003 Wafer level testing is performed per the indicated specifications for dice. Considerable differences in performance can often be observed for dice versus packaged units due to the influences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information on dice performance and lot qualifications via lot sampling test procedures. Dice data sheet subject to change. Please consult factory for current revision in production. I.D.No. 66-13-0101 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LT/LT 0203 PRINTED IN USA TA = 25°C. VS = ±20V unless otherwise noted. 10Krad(SI) 20Krad(SI) 50Krad(SI) 100Krad(SI) 200Krad(SI) SYMBOL PARAMETER CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS Post-Irradiation (Note 4) VOS Input Offset Voltage R S ≤ 5 0 k 22223 m V IOS Input Offset Current 10 10 10 10 20 nA IB Input Bias Current 75 75 100 200 400 nA CMRR Common Mode V CM = ±15V, RS ≤ 50k 80 80 80 80 80 dB Rejection Ratio PSRR Power Supply V CM = ±5V to ±2 0 V , 8 08 08 08 08 0 d B Rejection Ratio R S ≤ 50k AVOL Large Signal Voltage Gain R L = ±2k, VO = ±1 0 V , 5 05 05 05 02 5V / m V VS = ±15V VOUT Maximumm Output V S = ±15V, RL ≥ 10k ±12 ±12 ±12 ±12 ±12 V Voltage Swing V S = ±15V, RL ≥ 2k ±10 ±10 ±10 ±10 ±10 V IS Supply Current V S = ±2 0 V 33333 m A Note 1: Unless otherwise noted, all measurements are made with unity gain compensation (C1 = 30pF); these specifications apply for ±5V ≤ VS ≤ 20V. Note 2: For supply voltages less than ±15V, the maximum input voltage is equal to the supply voltage. Note 3: Refer to LTC standard product data sheet for all other applicable information. Note 4: The post-irradiation table is for lot qualification based on sample lot assembly and testing only. Contact LTC marketing for more detail.