RH1016 LINER
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 56mils × 58mils Backside Connection is V– DIE CROSS REFERENCE LTC Finished Part Number Order Part Number RH1016M RH1016M RH1016 DICE RH1016 DWF* *DWF = DICE in wafer form. UltraFast™ Precision 10ns Comparator DICE ELECTRICAL TEST LIMITS TA = 25°C. V+ = 5V , V– = –5V , VOUT(Q) = 1.4V , VLATCH = 0V , unless otherwise specifi ed. SYMBOL PARAMETER CONDITIONS MIN MAX UNITS VOS Input Offset Voltage R S ≤ 100Ω (Note 1) ±3 mV IOS Input Offset Current (Note 1) 1 μA IB Input Bias Current (Note 2) 10 μA Input Voltage Range (Note 3) Single 5V Supply (Note 3) –3.75 1.25 3.5 3.5 V V CMRR Common Mode Rejection –3.75V ≤ V CM ≤ 3.5V 80 dB PSRR Supply Voltage Rejection Positive Supply 4.6V ≤ V + ≤5.4V Negative Supply –7V ≤ V– ≤ –2V dB dB AV Small-Signal Voltage Gain 1V ≤ V OUT ≤ 2V 1400 V/V VOH Output High Voltage V + ≥ 4.6V , IOUT = 1mA IOUT = 10mA 2.80 2.60 V V VOL Output Low Voltage I SINK = 4mA 0.5 V I+ Positive Supply Current 35 mA I– Negative Supply Current 5m A VIH Latch Pin High Input Voltage 2.0 V VIL Latch Pin Low Input Voltage 0.8 V IIL Latch Pin Current V LATCH = 0V 500 μA PAD FUNCTION V +IN –IN V LATCH ENABLE GND Q OUT Q OUT L, L T , L TC and L TM are registered trademarks of Linear Technology Corporation. UltraFast is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Note 1: Input offset voltage is defi ned as the average of the two voltages measured by forcing fi rst one output, then the other to 1.4V . Input offset current is defi ned in the same way. Note 2: Input bias current (I B) is defi ned as the average of the two input currents. Note 3: Input voltage range is guaranteed in part by CMRR testing and in part by design and characterization. See the L T1016 data sheet for discussion of input voltage range for supplies other than ±5V or 5V .
Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008 LT 1008 • PRINTED IN USA Wafer level testing is performed per the indicated specifi cations for dice. Considerable differences in performance can often be observed for dice versus packaged units due to the infl uences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information on dice performance and lot qualifi cations via lot sampling test procedures. Dice data sheet subject to change. Please consult factory for current revision in production. I.D.No. 66-13-1016 Rad Hard die require special handling as compared to standard IC chips. Rad Hard die are susceptible to surface damage because there is no silicon nitride passivation as on standard die. Silicon nitride protects the die surface from scratches by its hard and dense properties. The passivation on Rad Hard die is silicon dioxide that is much “softer” than silicon nitride. L TC recommends that die handling be performed with extreme care so as to protect the die surface from scratches. If the need arises to move the die around from the chip tray, use a Tefl on-tipped vacuum wand. This wand can be made by pushing a small diameter Tefl on tubing onto the tip of a steel-tipped wand. The inside diameter of the Tefl on tip should match the die size for effi cient pickup. The tip of the Tefl on should be cut square and fl at to ensure good vacuum to die surface. Ensure the Tefl on tip remains clean from debris by inspecting under stereoscope. During die attach, care must be exercised to ensure no tweezers touch the top of the die.