REF50

REF50xx Low-Noise, Very Low Drift, Wide VIN Precision Voltage Reference datasheet (Rev. O)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SBOS410,O]
• PDF pages: 52

Technical content

REF50xx Low-Noise, Very Low Drift, Wide VIN Precision Voltage Reference

1 Features

• Low temperature drift (maximum): – Enhanced-grade (new): 2.5ppm/°C – High-grade: 3ppm/°C – Standard-grade: 8ppm/°C
• High accuracy (maximum): – Enhanced-grade: 0.025% – High-grade: 0.05% – Standard-grade: 0.1%
• Low noise: – Enhanced-grade: 0.5μVPP/V – High/standard-grade: 3μVPP/V
• Excellent long-term stability: – 22ppm after first 1000 hours (SOIC-8) – 50ppm after first 1000 hours (VSSOP-8)
• Wide input voltage support: – Enhanced-grade: 42V – High/standard-grade: 18V
• High-output current: ±10mA
• Temperature range: -40°C to 125°C

2 Applications

• Precision data acquisition systems
• Semiconductor test equipment
• Industrial process controls
• Medical instrumentation
• Pressure and temperature transmitters
• Lab and field instrumentation

3 Description

The REF50xx is a family of low-noise, low-drift, very high precision voltage references. The references are capable of both sinking and sourcing current, and have excellent line and load regulation. Achieve excellent temperature drift (2.5ppm/°C) and high accuracy (0.025%) using proprietary design techniques. These features, combined with very low flicker noise (0.5 μVPP/V), make the REF50xx family an excellent choice for use in high-precision data acquisition systems. REF50 family is available in enhanced grade (REF50xxEI), high grade (REF50xxI), and standard grade (REF50xxAI). The reference voltages are offered in 8-pin SOIC and VSSOP packages and are specified from –40°C to 125°C. For detailed comparison across various grades, refer to Table 4-2.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) REF50xxI REF50xxAI D (SOIC, 8) 4.90mm × 3.91mm DGK (VSSOP, 8) 3.00mm × 3.00mm REF50xxEI D (SOIC, 8) 4.90mm × 3.91mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. OPA365 ADS8326 REF5040 Input Signal,

0 V to 4 V

124 Ÿ 1 nF IN IN VDD GNDREF VIN VOUT GND +5V CBYPASS 1 µF C2 22 µF 5 V Copyright © 2016, Texas Instruments Incorporated Simplified Schematic REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

6.5 Electrical Characteristics REF50xxI and

10.2 Receiving Notification of Documentation Updates..31

12 Mechanical, Packaging, and Orderable

REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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4 Device Comparison Table

Table 4-1. Device VOUT Comparison PRODUCT Voltage SOIC (8) VSSOP (8) N/A REF5020ID REF5020AID REF5020IDGK REF5020AIDGK 2.048V REF5025EID REF5025ID REF5025AID REF5025IDGK REF5025AIDGK 2.5V REF5030EID REF5030ID REF5030AID REF5030IDGK REF5030AIDGK 3V REF5040EID REF5040ID REF5040AID REF5040IDGK REF5040AIDGK 4.096V REF5045EID REF5045ID REF5045AID REF5045IDGK REF5045AIDGK 4.5V REF5050EID REF5050ID REF5050AID REF5050IDGK REF5050AIDGK 5.0V N/A REF5010ID REF5010AID REF5010IDGK REF5010AIDGK 10.0V Table 4-2. Device Performance Comparison Device Grade Temperature Coefficient Initial Accuracy Noise VIN Max Quiescent Current Max REF50xxEI Enhanced 2.5ppm/ºC ±0.025% 0.5μVPP/V 42V 480μA REF50xxI High 3ppm/ºC ±0.05% 3μVPP/V 18V 1.2mA REF50xxAI Standard 8ppm/ºC ±0.1% 3μVPP/V 18V 1.2mA www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: REF50 REF50E

5 Pin Configuration and Functions

Figure 5-1. REF50xxAI, REF50xxI 8-Pin SOIC, VSSOP Top View VOUT DNC VIN TEMP GND EN 1 3 6 NR NC7 Not to scale Figure 5-2. REF50xxEI 8-Pin SOIC Top View Table 5-1. Pin Functions PIN

DESCRIPTION

NAME REF50xxI, REF50xxAI REF50xxEI DNC 1, 8 8 Do not connect EN - 1 Device enable control. Low level input disables the reference output and device enters shutdown mode. Device can be enabled by driving voltage > 1.6V or leaving the EN pin floating. GND 4 4 Ground NC 7 No internal connection NC 7 Leave floating or connect to GND NR - 5 Noise reduction pin TEMP 3 3 Temperature monitoring pin. Provides a temperature-dependent output voltage TRIM/NR 5 - Output adjustment or noise reduction pin VIN 2 2 Input supply voltage VOUT 6 6 Reference voltage output REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input voltage VIN (2) -0.3 18 V VIN (3) -0.3 48 Output Voltage VOUT -0.3 5.5 V Operating temperature (TA) –55 125 °CJunction temperature (TJ max) 150 Storage temperature range (Tstg) -65 150 (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Specification for REF5xxI and REF50xxAI. (3) Specification for REF50xxEI.

6.2 ESD Ratings

V(ESD) Electrostatic discharge (3) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ± 3000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ± 1000 Electrostatic discharge (4) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ± 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ± 500 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. (3) Specification for REF50xxI and REF50xxAI. (4) Specification for REF50xxEI.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage (2) VOUT + 0.2(1) 18 V Input voltage (3) VOUT + 0.2 42 V NR Noise reduction (3) 0 6 V IOUT Output current –10 10 mA TA Operating ambient temperature –40 25 125 °C (1) Except for the REF5020, where VIN (minimum) = 2.7V. (2) Specification for REF50xxI and REF50xxAI. (3) Specification for REF50xxEI. www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: REF50 REF50E

6.4 Thermal Information

THERMAL METRIC(1) REF50xxEI REF50xxI , REF50xxAI UNITD (SOIC) D (SOIC) DGK (VSSOP)

8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 120 115 160.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 52 63.4 53.9 °C/W RθJB Junction-to-board thermal resistance 66 57.1 82.9 °C/W ΨJT Junction-to-top characterization parameter 9.8 15.4 5.1 °C/W ΨJB Junction-to-board characterization parameter 64.7 56.2 80.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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6.5 Electrical Characteristics REF50xxI and REF50xxAI

At TA = 25°C, ILOAD = 0, CL = 1μF and VIN = (VOUT + 0.2V) to 18V, unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT OUTPUT VOLTAGE VOUT Output Voltage REF5020 (VOUT = 2.048V) (1), 2.7V < VIN < 18V 2.048 V REF5025 2.5 REF5030 3.0 REF5040 4.096 REF5045 4.5 REF5050 5 REF5010 10 Initial Accuracy High Grade All voltage options (1) -0.05 0.05 % Standard Grade All voltage options (1) –0.1 0.1 % NOISE enpp Low Frequency noise ƒ = 0.1Hz to 10Hz 3 µVPP/V en Output Voltage Noise ƒ = 10Hz to 1kHz 0.9 µVrms/V OUTPUT VOLTAGE TEMPERATURE DRIFT dVOUT/dT High grade TA = –40°C to 125°C 2.5 3 pm/℃ Standard grade 3 8 LINE REGULATION ΔVO(ΔVI) Line regulation VIN = (VOUT + 0.2V) to 18V(1) 1 3 ppm/VVIN = (VOUT + 0.2V) TO 18V, TA = –40°C to 125°C(1) 1 5 LOAD REGULATION ΔVO(ΔIL) Load regulation –10mA < IOUT < 10mA, VIN = VOUT + 0.75V(2) 20 30 ppm/mA10mA < IOUT < 10mA, VIN = VOUT + 0.75V(2), TA = –40°C to 125°C 50 SHORT-CIRCUIT CURRENT ISC Short circuit current VOUT = 0 25 mA THERMAL HYSTERESIS High grade VSSOP-8 Cycle 1 50 ppm Cycle 2 40 SOIC-8 Cycle 1 70 Cycle 2 50 Standard grade VSSOP-8 Cycle 1 70 Cycle 2 40 SOIC-8 Cycle 1 90 Cycle 2 50 LONG-TERM STABILITY ΔVOUT_LTD VSSOP-8 0 to 1000 hours 50 ppm 1000 to 2000 hours 25 SOIC-8 0 to 1000 hours 22 1000 to 2000 hours 18 TEMP PIN Voltage output 575 mV Temperature sensitivity TA = -40°C to 125°C 2.64 mV/℃ www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: REF50 REF50E

6.5 Electrical Characteristics REF50xxI and REF50xxAI (continued)

At TA = 25°C, ILOAD = 0, CL = 1μF and VIN = (VOUT + 0.2V) to 18V, unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT TURN-ON SETTLING TIME Turn-on settling time To 0.1% with CL = 1μF 200 μs POWER SUPPLY VS Supply voltage See note (1) VOUT + 0.2 18 V Quiescent current 0.8 1 mA TEMPERATURE RANGE Specified range –40 125 °C Operating range –55 125 °C (1) For VOUT ≤ 2.5V, the minimum supply voltage is 2.7V. (2) Except for REF5020, where VIN = 3V. REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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6.6 Electrical Characteristics REF50xxEI

At TA = 25°C, ILOAD = 0, CL = 1μF and VIN = VEN = (VOUT + 0.25V) , unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT OUTPUT VOLTAGE VOUT Output Voltage REF5025E 2.5 V REF5030E 3.0 V REF5040E 4.096 V REF5045E 4.5 V REF5050E 5 V IA Initial accuracy All voltage options –0.025 0.025 % dVOUT/dT TA = –40°C to 125°C 2.5 ppm/℃ NOISE enpp Low Frequency noise ƒ = 0.1Hz to 10Hz 0.5 µVPP/V en Output Voltage Noise ƒ = 10Hz to 1kHz 0.8 µVrms/V LINE REGULATION ΔVO(ΔVI) Line regulation VIN = (VOUT + 0.2V) to 42V 1 3 ppm/V VIN = VOUT + 0.2V to 42V, TA = –40°C to 125°C 1 5 LOAD REGULATION ΔVO(ΔIL) Load regulation –10mA < IOUT < 10mA, VIN = VOUT + 0.75V 5 25 ppm/mA10mA < IOUT < 10mA, VIN = VOUT + 0.75V, TA = –40°C to 125°C 35 SHORT-CIRCUIT CURRENT ISC Short circuit current VOUT = 0 21 mA THERMAL HYSTERESIS AND LONG-TERM STABILITY TH SOIC-8 Cycle 1 80 ppm SOIC-8 Cycle 2 20 ppm LONG-TERM STABILITY ΔVOUT_LTD SOIC-8 0 to 1000 hours 25 ppm 1000 to 2000 hours 10 ppm TEMP PIN Voltage output 625 mV Temperature sensitivity TA = -40°C to 125°C 2.64 mV/°C TURN-ON SETTLING TIME Turn-on settling time To 0.1% with CL = 1μF 400 μs CAPACITIVE LOAD CIN Stable input capacitor range –40℃ ≤ TA ≤ 125℃ 0.1 µF CL Stable output capacitor range –40℃ ≤ TA ≤ 125℃ 1 100 µF POWER SUPPLY VS Supply voltage See note VOUT + 0.2 42 V Quiescent current 340 μA –40°C ≤ TA ≤ 125°C 480 μA Quiescent current Shunt down current VEN = 0V 10 μA Enable Voltage VEN Active mode (EN = 1) 1.6 V Shutdown Mode (EN = 0) 0.5 V TEMPERATURE RANGE www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: REF50 REF50E

6.6 Electrical Characteristics REF50xxEI (continued)

At TA = 25°C, ILOAD = 0, CL = 1μF and VIN = VEN = (VOUT + 0.25V) , unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT Specified range –40 125 °C REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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6.7 Typical Characteristics: REF50xxI, REF50xxAI

At TA = 25°C, ILOAD = 0, and VS = VOUT + 0.2V, unless otherwise noted. For VOUT ≤ 2.5V, the minimum supply voltage is 2.7 V. Drift□(ppm/ C)/c176 Population□(%) 0°C to 85°C Figure 6-1. Temperature Drift Drift□(ppm/ C)/c176 Population□(%) –40°C to 125°C Figure 6-2. Temperature Drift Output□Initial□Accuracy□(%) Population□(%) Figure 6-3. Output Voltage Initial Accuracy -0.02 -0.015 -0.01 -0.005 0.005 0.01 0.015 0.02 ±50 ±25 0 25 50 75 100 125 Output Voltage Accuracy (%) Temperature (ºC) C001 Figure 6-4. Output Voltage Accuracy vs Temperature Frequency□(Hz) 160 140 120 100 PSRR□(dB) 100k100 1k 10k Figure 6-5. Power-Supply Rejection Ratio vs Frequency /c45 15 /c45 10 /c45 5 Load□Current□(mA) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Dropout□Voltage□(V) 150 5 10 +125 C/c176 +25 C/c176 /c45 /c176 40 C Figure 6-6. Dropout Voltage vs Load Current www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: REF50 REF50E

6.7 Typical Characteristics: REF50xxI, REF50xxAI (continued)

At TA = 25°C, ILOAD = 0, and VS = VOUT + 0.2V, unless otherwise noted. For VOUT ≤ 2.5V, the minimum supply voltage is 2.7 V. /c45 10 /c45 5 Load□Current□(mA) 2.50125 2.50100 2.50075 2.50050 2.50025 2.50000 2.49975 2.49950 2.49925 2.49900 2.49875 Output□Voltage□(V) 100 5 +125 C/c176 +25 C/c176 /c45 /c176 40 C Figure 6-7. REF5025 Output Voltage vs Load Current /c45 50 /c45 25 T emperature□( C)/c176 0.9 0.8 0.7 0.6 0.5 0.4 0.3 TEMP□Pin□Output□Voltage□(V) 1250 25 50 75 100 Figure 6-8. Temp Pin Output Voltage vs Temperature /c45 50 /c45 25 T emperature□( C)/c176 1050 1000 950 900 850 800 750 700 650 600 Quiescent□Current□( /c109A) 1250 25 50 75 100 Figure 6-9. Quiescent Current vs Temperature 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 V (V)IN 1000 950 900 850 800 750 700 650 600 I ( A) /c109 Q +125 C/c63 +25 C/c63 /c45 40 C/c63 Figure 6-10. Quiescent Current vs Input Voltage /c45 50 /c45 25 T emperature□( C)/c176 0.5 0.4 0.3 0.2 0.1 /c45 0.1 /c45 0.2 /c45 0.3 /c45 0.4 /c45 0.5 Line□Regulation□(ppm/V) 1250 25 50 75 100 Figure 6-11. Line Regulation vs Temperature /c45 50 /c45 25 T emperature□( C)/c176 Short-Circuit□Current□(mA) 1250 25 50 75 100 Sourcing Sinking Figure 6-12. Short Circuit Current vs Temperature REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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At TA = 25°C, ILOAD = 0, and VS = VOUT + 0.2V, unless otherwise noted. For VOUT ≤ 2.5V, the minimum supply voltage is 2.7 V. 1s/div

1 V/div/c109

Figure 6-13. 0.1Hz to 10Hz Noise F r e q u e n c y ( H z ) Noise Density (nV/V /Hz) 1 0 2 0 3 0 5 0 1 0 0 2 0 0 5 0 0 1 0 0 0 2 0 0 0 1 0 0 0 0 3 0 0 0 03 0 0 0 0 2 0 4 0 6 0 8 0 1 0 0 Figure 6-14. Noise Spectral Density 40 s/div/c109 2V/div 1V/div VOUT VIN REF5025, CL = 1μF Figure 6-15. Start-Up 400 s/div/c109 5V/div 1V/div VOUT VIN REF5025, CL = 10μF Figure 6-16. Start-Up T i m e ( 2 0 0 u s / D i v ) I L O A D + 1 m A - 1 m A 5 m V / d i v 1 m A . d i v CL = 1μF, IOUT = 1mA Figure 6-17. Load Transient 2 0 0  s / d i v I L O A D + 1 0 m A - 1 0 m A 1 0 m V / d i v 1 0 m A / d i v CL = 1μF, IOUT = 10mA Figure 6-18. Load Transient www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: REF50 REF50E

At TA = 25°C, ILOAD = 0, and VS = VOUT + 0.2V, unless otherwise noted. For VOUT ≤ 2.5V, the minimum supply voltage is 2.7 V. CL = 10μF, IOUT = 1mA Figure 6-19. Load Transient 2 0 0  s / d i v I L O A D - 1 0 m A + 1 0 m A 1 0 m A / d i v 1 0 m V / d i v CL = 10μF, IOUT = 10mA Figure 6-20. Load Transient 20/c109s/div VOUT VIN 5mV/div 500mV/div CL = 1μF Figure 6-21. Line Transient 100 s/div/c109 VOUT VIN 5mV/div 500mV/div CL = 10μF Figure 6-22. Line Transient Hours Output Voltage Stability (ppm) 0 100 200 300 400 500 600 700 800 900 1000 -100 -50 100 150 200 250 VSSOP-8 Figure 6-23. REF50xx Long-Term Stability (First 1000 Hours) Hours Output Voltage Stability (ppm) 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 -100 -50 100 150 200 250 VSSOP-8 Figure 6-24. REF50xx Long-Term Stability (Second 1000 Hours) REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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At TA = 25°C, ILOAD = 0, and VS = VOUT + 0.2V, unless otherwise noted. For VOUT ≤ 2.5V, the minimum supply voltage is 2.7 V. Hours Output Voltage Stability (ppm) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 -100 -50 100 150 200 250 VSSOP-8 Figure 6-25. REF50xx Long-Term Stability (First 2000 Hours) Hours Output Voltage Stability (ppm) 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000 -100 -50 100 150 200 250 VSSOP-8 Figure 6-26. REF50xx Long-Term Stability (Second 2000 Hours) Hours Output Voltage Stability (ppm) 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 -100 -50 100 150 200 250 VSSOP-8 Figure 6-27. REF50xx Long-Term Stability (4000 Hours) SOIC-8 Figure 6-28. REF50xx Long-Term Stability (First 1000 Hours) SOIC-8 Figure 6-29. REF50xx Long-Term Stability (Second 1000 Hours) H o u r s Output Voltage Stability (ppm) 0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 1 2 0 0 1 4 0 0 1 6 0 0 1 8 0 0 2 0 0 0 - 1 5 0 - 1 0 0 - 5 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 SOIC-8 Figure 6-30. REF50xx Long-Term Stability (2000 Hours) www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: REF50 REF50E

6.8 Typical Characteristics: REF50xxEI

at TA = 25°C, VIN = VEN = VOUT + 0.5V, IL = 0mA, COut = 10μF, CNR = Open, CIN = 0.1μF, T e m p e r a t u r e (  C ) Output Voltage Accuracy (%) - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 - 0 . 0 2 - 0 . 0 1 5 - 0 . 0 1 - 0 . 0 0 5 0 . 0 0 5 0 . 0 1 0 . 0 1 5 0 . 0 2 Figure 6-31. Output Voltage Vs Free-Air Temperature T e m p d r i f t ( p p m /  C ) Population (%) 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 Output Initial Accuracy (%) Population (%) -0.02 -0.016 -0.012 -0.008 -0.004 0.004 0.008 0.012 0.016 0.02 10% 20% 30% 40% 50% Figure 6-33. Accuracy Distribution Figure 6-34. Line Regulation vs Temperature T e m p e r a t u r e (  C ) Load Regulation Sourcing (ppm/mA) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 2 1 6 2 0 Figure 6-35. Load Regulation (Sourcing) vs Temperature T e m p e r a t u r e (  C ) Load Regulation Sinking (ppm/mA) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 2 1 6 2 0 Figure 6-36. Load Regulation (Sinking) vs Temperature REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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6.8 Typical Characteristics: REF50xxEI (continued)

at TA = 25°C, VIN = VEN = VOUT + 0.5V, IL = 0mA, COut = 10μF, CNR = Open, CIN = 0.1μF, 1 m s / d i v V I N = 4 2 V V I N = 2 . 7 5 V V O U T ( 1 0 0 m V / d i v ) Figure 6-37. Line Transient Response Figure 6-38. Load Transient Response (COUT = 10μF) 1 m s / d i v V R E F ( 1 0 m V / d i v ) I L = - 1 0 m A I L = 1 0 m A Figure 6-39. Load Transient Response (COUT = 1μF) F r e q u e n c y ( H z ) Dynamic Impedance () 1 0 2 0 5 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 . 4 0 . 8 1 . 2 1 . 6 2 . 4 2 . 8 C O U T = 1 0 0 u F C O U T = 1 0 u F C O U T = 1 u F Figure 6-40. Output Impedance T e m p e r a t u r e (  C ) Quiescent Current (A) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 Figure 6-41. Quiescent Current vs Temperature Figure 6-42. Shutdown Current vs Temperature www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: REF50 REF50E

at TA = 25°C, VIN = VEN = VOUT + 0.5V, IL = 0mA, COut = 10μF, CNR = Open, CIN = 0.1μF, Input Voltage (V) Voltage (V) 0 4 8 12 16 20 0.3 0.6 0.9 1.2 1.5 VEN_HIGH VEN_LOW Figure 6-43. Enable Threshold vs VIN T e m p e r a t u r e (  C ) Dropout Voltage (mV) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 I L = 1 0 m A I L = 5 m A I L = 0 m A Figure 6-44. Dropout Voltage vs Temperature F l i c k e r N o i s e ( p p m p - p ) Population (%) 2 0 4 0 6 0 8 0 1 0 0 Figure 6-45. 0.1Hz to 10Hz Voltage Noise Distribution (CNR = Open) Figure 6-46. Noise Performance 10Hz to 100kHz (CNR = Open) F r e q u e n c y ( H z ) Power Supply Rejection Ratio (dB) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 2 5 5 0 7 5 1 0 0 1 2 5 C O U T = 1 µ F C O U T = 1 0 µ F C O U T = 1 0 0 µ F Figure 6-47. Power-Supply Rejection Ratio vs Frequency H y s t e r e s i s ( p p m ) Population (%) 1 0 1 5 2 0 2 5 3 0 3 5 100 120 140 160 Figure 6-48. Thermal Hysteresis Distribution: Cycle 1 (-40°C to 125°C) REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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at TA = 25°C, VIN = VEN = VOUT + 0.5V, IL = 0mA, COut = 10μF, CNR = Open, CIN = 0.1μF, T h e r m a l H y s t e r e s i s ( p p m ) Population (%) 2 5 5 0 7 5 1 0 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 0 Figure 6-49. Thermal Hysteresis Distribution: Cycle 2 (-40°C to 125°C) T i m e ( H r . ) Long term stability (ppm) 0 4 0 0 8 0 0 1 2 0 0 1 6 0 0 2 0 0 0 - 1 5 0 - 1 0 0 - 5 0 5 0 1 0 0 1 5 0 Figure 6-50. Long-Term Stability (First 2000 Hours) T i m e ( H r . ) Long term stability (ppm) 0 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0 0 0 6 0 0 0 7 0 0 0 8 0 0 0 - 1 5 0 - 1 0 0 - 5 0 5 0 1 0 0 1 5 0 Figure 6-51. Long-Term Stability (7500 hours) www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: REF50 REF50E

7 Parameter Measurement Information

7.1 Solder Heat Shift

The materials used in manufacturing the REF50xx have differing coefficients of thermal expansion, resulting in stress on the device die when the part is heated. Mechanical and thermal stress on the device can cause the output voltages to shift, degrading the initial accuracy and drift specifications of the product. Reflow soldering is a common cause of this error. To illustrate this effect, 36 devices are soldered on printed-circuit-boards using lead-free solder paste and the paste manufacturer suggested reflow profile. Figure 7-1 shows the reflow profile. The printed-circuit-board is comprised of FR4 material. The board thickness is 0.8mm and the area is 13mm × 13mm. The reference voltage is measured before and after the reflow process across temperature; the typical shift of accuracy and drift is displayed in Figure 7-2 for REF50xxEI and Figure 7-3 through Figure 7-10 for REF50xx. Although all tested units exhibit very low shifts, higher shifts are also possible depending on the size, thickness, and material of the printed-circuit-board. An important note is that the histograms display the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is common on printed circuit boards (PCBs) with surface-mount components on both sides, causes additional shifts in the output bias voltage. If the PCB is exposed to multiple reflows, then solder the device in the last pass to minimize device exposure to thermal stress. 100 150 200 250 300 0 50 100 150 200 250 300 350 400 Temperature (ƒC) Time (seconds) C01 Figure 7-1. Reflow Profile Figure 7-2. Solder Heat Shift Distribution (%), REF50xxEI REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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-3 -2 -1 0 1 2 3 Population (%) Drift Shift Distribution (ppm/ƒC) - SOIC Package C008 Figure 7-9. Drift Shift Distribution, SOIC Package -3 -2 -1 0 1 2 3 Population (%) Drift Shift Distribution due to Soldering (ppm/ƒC) - MSOP Package C001 Figure 7-10. Drift Shift Distribution, VSSOP Package REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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8 Detailed Description

8.1 Overview

The REF50xx is family of low-noise, precision band-gap voltage references designed for excellent initial voltage accuracy and drift. See Section 8.2 for a simplified block diagram of the REF50xx.

8.2 Functional Block Diagram

/c97T /c97T (10 A/c109 at□+25 C)/c176 R2 R1 10k/c87 1k/c871.2V Figure 8-1. REF50xxI, REF50xxAI Block Diagram 62k VOUT T (10µ A at +25°C) Bandgap 13k VIN EN NR GND TMP Figure 8-2. REF50xxEI Block Diagram www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: REF50 REF50E

8.3 Feature Description

8.3.1 Temperature Monitoring

The temperature output terminal (TEMP, pin 3) provides a temperature-dependent voltage output with approximately 60k Ω source impedance. As illustrated in Figure 6-8 , the output voltage follows the nominal relationship: REF50xxI, REF50xxAI: VTEMP PIN = 509mV + 2.64 × T(°C) (1) REF50xxEI: VTEMP PIN = 625mV + 2.64 × T(°C) (2) The TEMP pin indicates general chip temperature, accurate to approximately ±15°C. Although not generally suitable for accurate temperature measurements, use the TEMP pin to indicate temperature changes or for temperature compensation of analog circuitry. A temperature change of 30°C corresponds to an approximate 79mV change in voltage at the TEMP pin. The TEMP pin has high-output impedance (see Section 8.2). Loading the TEMP pin with a low-impedance circuit induces a measurement error; however, the pin does not have any effect on VOUT accuracy. To avoid errors caused by low-impedance loading, buffer the TEMP pin output with a suitable low-temperature drift op amp, such as the OPA333, OPA335, or OPA376, as shown in Figure 8-3. DNC TEMP VOUT VIN GND DNC NC TRIM/NR REF50xx VTEMP 2.6mV/ C/c176 OPA(1) NOTE:□(1)□Low□drift□op□amp,□such□as□the□OPA333,□OPA335,□or□OPA376. Figure 8-3. Buffering the TEMP Pin Output

8.3.2 Temperature Drift

The REF50xx is designed for minimal drift error, which is defined as the change in output voltage over temperature. The drift is calculated using the box method, as calculated in Equation 3. Dr if t = V OUTMA X − V O UT M IN V O U T × Temper at ure Rang e × 10 6 ppm (3) The REF50xx features a maximum drift coefficient of 2.5ppm/°C for the enhanced-grade version, 3ppm/°C for the high-grade version, and 8ppm/°C for the standard-grade version. REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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8.3.3 Thermal Hysteresis

Thermal hysteresis for the REF50xx is the change in output voltage after operating the device at 25°C, cycling the device through the specified temperature range, and returning to 25°C. Equation 4 shows thermal hysteresis. V HY ST = V PRE − V POST V NOM × 10 6 p pm (4) where

• VHYST = thermal hysteresis (ppm)
• VNOM = the specified output voltage
• VPRE = output voltage measured at 25°C pre-temperature cycling
• VPOST = output voltage measurement after the device cycles from 25°C through the specified temperature range of –40°C to 125°C and returns to 25°C

8.3.4 Noise Performance

Typical 0.1Hz to 10Hz voltage noise for each member of the REF50xx family is specified Section 6.5 and Section 6.6. The noise voltage increases with output voltage and operating temperature. Use additional filtering to improve output noise levels. If using additional filtering, verify that the output impedance does not degrade performance. For additional information about minimizing noise and maximizing performance in mixed-signal applications, such as data converters, refer to the How a Voltage Reference Affects ADC Performance Part 1 , How a Voltage Reference Affects ADC Performance Part 2 , and How a Voltage Reference Affects ADC Performance Part 3 analog design journals. DNC TEMP VOUT VIN GND DNC NC TRIM/NR REF50xx

1 F/c109

+VSUPPL Y Figure 8-4. Noise Reduction Using the TRIM/NR Pin

8.3.5 Long-Term Stability

Due to aging and environmental effects, all semiconductor devices experience physical changes of the semiconductor die and the packaging material over time. Over time, the changes and the associated package stress on the die cause the output voltage in precision voltage references to deviate. The value of such change is specified in the data sheet by a parameter called the long-term stability (also known as the long-term drift (LTD)). Equation 5 shows how LTD is calculated. Note that the LTD value is positive if the output voltage drifts higher over time and negative if the voltage drifts lower over time. Figure 6-23 through Figure 6-30 show the drift of the output voltage for REF50xx over the first 4000 operating hours. LT D ppm t = n = V O U T t = 0 − V O UT t = n V OUT t = 0 × 10 6 (5) where

• LTD(ppm)|t=n = long-term stability (ppm)
• VOUT|t=0 = output voltage at time = 0 hr
• VOUT|t=n = output voltage at time = n hr www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: REF50 REF50E

8.3.6 Output Adjustment Using the TRIM/NR Pin

The REF50xxI, REF50xxAI provides a very accurate, factory-trimmed voltage output. Adjust V OUT using the trim and noise reduction pin (TRIM/NR, pin 5). Figure 8-5 shows a typical circuit that allows an output adjustment of ±15mV. GND TRIM/NR TEMP VOUT VIN NC DNCDNC REF50XX 1M R1 = 10k R2 = 2k VSUPPLY Figure 8-5. VOUT Adjustment Using the TRIM/NR Pin The REF50xx allows access to the band-gap through the TRIM/NR pin. Placing a capacitor from the TRIM/NR pin to GND ( Figure 8-4 ) in combination with the internal R 3 and R 4 resistors creates a low-pass filter. A capacitance of 1 μF creates a low-pass filter with the corner frequency from 10Hz to 20Hz. A low-pass filter decreases the overall noise measured on the V OUT pin by half. A higher capacitance results in a lower filter cutoff frequency, further reducing output noise. Using this capacitor increases start-up time.

8.4 Device Functional Modes

8.4.1 Basic Connections

Figure 8-6 shows the typical connections for the REF50xx. TI recommends a supply bypass capacitor ranging from 1 μF to 10 μF. Confirm that a output capacitor (C L) is connected from V OUT to GND. For output stability, verify that the equivalent series resistance (ESR) value of C L less than or equal to 1.5 Ω. To minimize noise, the recommended ESR of CL is from 1Ω and 1.5Ω. GND VOUT TRIM/NR GND REF50 TEMP VIN +VSupply DNC DNC NC CBYPASS 1µF to 10µF CL GND CL = 1µF to 50µF for REF50xxI, REF50xxAI CL = 1µF to 100µF for REF50xxEI Figure 8-6. Basic Connections

8.4.2 Supply Voltage

The REF50xx family of voltage references features extremely low dropout voltage. With the exception of the REF5020, which has a minimum supply requirement of 2.7V, operate the family of references with a supply of REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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200mV more than the output voltage in an unloaded condition. For loaded conditions, Figure 6-6 shows a typical dropout voltage versus load plot.

8.4.3 Negative Reference Voltage

For applications requiring a negative and positive reference voltage, use REF50xx and OPA735 to provide a dual-supply reference from a 5V supply. Figure 8-7 shows the REF5025 used to provide a 2.5V supply reference voltage. The low-drift performance of the REF50xx complements the low offset voltage and zero drift of the OPA735 to provide an accurate solution for split-supply applications. Verify that the temperature coefficients of R1 and R2 match. /c45 2.5V +2.5V +5V NOTE:□Bypass□capacitors□not□shown. 10k/c87 R2 10k/c87 /c45 5V OPA735 +5V DNC TEMP VOUT VIN GND DNC NC TRIM/NR REF5025 Figure 8-7. REF5025 and OPA735 Create Positive and Negative Reference Voltages www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: REF50 REF50E

9 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

Data acquisition systems often require stable voltage references to maintain accuracy. The REF50xx family features low noise, very low drift, and high initial accuracy for high-performance data converters. Figure 9-1 shows the REF5040 in a basic data acquisition system.

9.2 Typical Applications

9.2.1 16-bit, 250KSPS Data Acquisition System ADS8326 REF5040 OPA365 ESR 47µF 10µF REFIN CS CLK SDO 1nF 0-4V 124Ÿ Figure 9-1. Complete Data Acquisition System Using the REF50xx

9.2.1.1 Design Requirements

When using the REF50xx in the design, select a proper output capacitor that does not create gain peaking, thereby increasing total system noise. At the same time, select a capacitor that provides the required filtering performance for the system. Add input bypass capacitor and noise reduction capacitors for peak performances. During the design of the data acquisition system, give equal consideration to the buffering analog input signal and the reference voltage. Having a properly designed input buffer with an associated RC filter is a necessary requirement for good performance of the data acquisition system.

9.2.1.2 Detailed Design Procedure

The OPA365 is used to drive the 16-bit analog-to-digital converter (ADS8326). The RC filter at the output of the OPA365 is used to reduce the charge kick-back created by the opening and closing of the sampling switch inside the ADC. Design the RC filter such that the voltage at the sampling capacitor settles to 16-bit accuracy within the acquisition time of the ADC. Verify that the bandwidth of the driving amplifier is at least be four times the bandwidth of the RC filter. The REF5040 is used to drive the REF pin of the ADS8326. Proper selection of voltage reference output capacitor is very important for this design. Very low equivalent series resistance (ESR) creates gain-peaking, REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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which degrades SNR of the total system. If the ESR of the capacitor is not enough, then an additional resistor must be added in series with the output capacitor. A capacitance of 1 μF can connect to the NR pin to reduce band-gap noise of the REF50xx. Table 9-1 shows SNR measurements using different RC filters at the output of the OPA365, different values of output capacitor for the REF50xx and different values of capacitors at the TRIM/NR pin. Table 9-1. Data Acquisition Measurement Results for Different Conditions TEST CONDITION 1 TEST CONDITION 2 OPA365 RC filter 124Ω, 1nF 124Ω, 1nF REF5040 output capacitor 10μF 10μF + 47μF TRIM/NR pin capacitor 0μF 1μF SNR 86.7dB 92.8dB

9.2.1.3 Application Curve

Figure 9-2. FFT Plot-Noise Floor of Data Acquisition System

9.3 Power Supply Recommendations

The REF50xx family of voltage references features extremely low dropout voltage. With the exception of the REF5020, which has a minimum supply requirement of 2.7V, the REF50xx family of voltage references operates with a supply of 200mV more than the output voltage in an unloaded condition. For loaded conditions, Figure 6-6 provides a typical dropout voltage versus load plot. TI recommends a supply bypass capacitor ranging from 1 μF to 50μF for REF50xxI and REF50xxAI. TI recommends a supply bypass capacitor ranging from 1μF to 100μF for REF50xxEI.

9.4 Layout

9.4.1 Layout Guidelines

9.4.1.1 REF50xxI, REF50xxAI Layout Guidelines

• Place the power-supply bypass capacitor as closely as possible to the supply and ground pins. The recommended value of this bypass capacitor is from 1μF to 10μF. If necessary, add decoupling capacitance to compensate for noisy or high-impedance power supplies.
• Place a 1μF noise filtering capacitor between the NR pin and ground.
• Verify that the output decouples with a 1μF to 50μF capacitor. A resistor in series with the output capacitor is optional. For better noise performance, the recommended ESR on the output capacitor is from 1Ω to 1.5Ω. www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: REF50 REF50E

• Add a high-frequency, 1μF capacitor in parallel between the output and ground to filter noise and help with switching loads as data converters.

9.4.1.2 REF50xxEI Layout Guidelines

• Place the power-supply bypass capacitor as close as possible to the supply and ground pins. The recommended value of this bypass capacitor is from 0.1μF to 10μF. If necessary, add decoupling capacitance to compensate for noisy or high-impedance power supplies. Verify that the smallest capacitor is placed closest to the device.
• Place a 0.1μF to 1μF class 1 noise filtering capacitor between the NR pin and ground.
• Verify that the output decouples with a 1μF to 100μF low ESR (maximum 1Ω) capacitor.

9.4.2 Layout Example

C C R C C Figure 9-3. Layout Example for REF50xxI, REF50xxAI Figure 9-4. Layout Example for REF50xxEI

9.4.3 Power Dissipation

The REF50xx family is specified to deliver current loads of ±10mA over the specified input voltage range. The temperature of the device increases according to Equation 6: TJ = TA + PD × θJA (6) where

• TJ = junction temperature (°C)
• TA = ambient temperature (°C)
• PD = power dissipated (W)
• θJA = junction-to-ambient thermal resistance (°C/W) Establish that the REF50xx junction temperature does not exceed the absolute maximum rating of 150°C. REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, 0.05μV/°C (Maximum), Single-Supply CMOS Zero-Drift Series Operational Amplifier data sheet
• Texas Instruments, REF5020 PSpice Model
• Texas Instruments, REF5020 TINA-TI Reference Design
• Texas Instruments, REF5020 TINA-TI Spice Model
• Texas Instruments, INA270 PSpice Model
• Texas Instruments, INA270 TINA-TI Reference Design
• Texas Instruments, INA270 TINA-TI Spice Model

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision N (March 2025) to Revision O (October 2025) Page

• Updated title from: Electrical Characteristics REF50 to: Electrical Characteristics REF50xxA and REF50xxAI 7
• Changed from: Layout Guidelines to: REF50xxEI Layout Guidelines and REF50xxI, REF50xxAI Layout Changes from Revision M (December 2024) to Revision N (March 2025) Page www.ti.com REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: REF50 REF50E

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. REF50, REF50E SBOS410O – JUNE 2007 – REVISED OCTOBER 2025 www.ti.com

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www.ti.com 18-Jul-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) REF5010AID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5010 A REF5010AID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5010 A REF5010AIDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI | Nipdau Level-2-260C-1 YEAR -40 to 125 R50G REF5010AIDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50G REF5010AIDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI | Nipdau Level-2-260C-1 YEAR -40 to 125 R50G REF5010AIDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50G REF5010AIDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5010 A REF5010AIDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5010 A REF5010AIDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5010 A REF5010AIDRG4.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5010 A REF5010ID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5010 REF5010ID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5010 REF5010IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50G REF5010IDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50G REF5010IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50G REF5010IDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50G REF5020AID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5020 A Addendum-Page 1

www.ti.com 18-Jul-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) REF5020AID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5020 A REF5020AIDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI | Nipdau Level-2-260C-1 YEAR -40 to 125 R50A REF5020AIDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50A REF5020AIDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50A REF5020AIDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50A REF5020AIDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5020 A REF5020AIDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5020 A REF5020ID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5020 REF5020ID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5020 REF5020IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50A REF5020IDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50A REF5020IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50A REF5020IDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50A REF5020IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5020 REF5020IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5020 REF5025AID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5025 A REF5025AID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5025 A REF5025AIDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI | Nipdau Level-2-260C-1 YEAR -40 to 125 R50B REF5025AIDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50B REF5025AIDGKRG4 Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 R50B Addendum-Page 2

www.ti.com 18-Jul-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) REF5025AIDGKRG4.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 R50B REF5025AIDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI | Nipdau Level-2-260C-1 YEAR -40 to 125 R50B REF5025AIDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50B REF5025AIDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5025 A REF5025AIDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5025 A REF5025AIDR1G4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5025 A REF5025AIDR1G4.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5025 A REF5025EIDR Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 R5025E REF5025EIDR.A Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 R5025E REF5025ID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5025 REF5025ID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5025 REF5025IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50B REF5025IDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50B REF5025IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50B REF5025IDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50B REF5025IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5025 REF5025IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5025 REF5030AID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5030 A REF5030AID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5030 A Addendum-Page 3

www.ti.com 18-Jul-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) REF5030AIDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI | Nipdau Level-2-260C-1 YEAR -40 to 125 R50C REF5030AIDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50C REF5030AIDGKRG4 Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 R50C REF5030AIDGKRG4.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 R50C REF5030AIDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50C REF5030AIDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50C REF5030AIDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5030 A REF5030AIDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5030 A REF5030AIDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5030 A REF5030AIDRG4.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5030 A REF5030EIDR Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 R5030E REF5030ID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5030 REF5030ID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5030 REF5030IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50C REF5030IDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50C REF5030IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50C REF5030IDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50C REF5030IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5030 REF5030IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5030 REF5040AID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5040 A Addendum-Page 4

www.ti.com 18-Jul-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) REF5040AID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5040 A REF5040AIDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI | Nipdau Level-2-260C-1 YEAR -40 to 125 R50D REF5040AIDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50D REF5040AIDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI | Nipdau Level-2-260C-1 YEAR -40 to 125 R50D REF5040AIDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50D REF5040AIDGKTG4 Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50D REF5040AIDGKTG4.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50D REF5040AIDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5040 A REF5040AIDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5040 A REF5040AIDRG4 Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5040 A REF5040AIDRG4.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5040 A REF5040EIDR Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 R5040E REF5040ID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5040 REF5040ID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5040 REF5040IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50D REF5040IDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50D REF5040IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50D REF5040IDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50D REF5040IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5040 REF5040IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5040 Addendum-Page 5

www.ti.com 18-Jul-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) REF5045AID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5045 A REF5045AID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5045 A REF5045AIDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI | Nipdau Level-2-260C-1 YEAR -40 to 125 R50E REF5045AIDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50E REF5045AIDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI | Nipdau Level-2-260C-1 YEAR -40 to 125 R50E REF5045AIDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50E REF5045AIDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5045 A REF5045AIDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5045 A REF5045EIDR Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 R5045E REF5045ID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5045 REF5045ID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5045 REF5045IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50E REF5045IDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50E REF5045IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50E REF5045IDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50E REF5045IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5045 REF5045IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5045 REF5050AID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5050 A REF5050AID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5050 A Addendum-Page 6

www.ti.com 18-Jul-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) REF5050AIDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI | Nipdau Level-2-260C-1 YEAR -40 to 125 R50F REF5050AIDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50F REF5050AIDGKRG4 Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 R50F REF5050AIDGKRG4.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 R50F REF5050AIDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI | Nipdau Level-2-260C-1 YEAR -40 to 125 R50F REF5050AIDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50F REF5050AIDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5050 A REF5050AIDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 REF 5050 A REF5050EIDR Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 R5050E REF5050EIDR.A Active Production SOIC (D) | 8 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 R5050E REF5050ID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5050 REF5050ID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5050 REF5050IDGKR Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50F REF5050IDGKR.A Active Production VSSOP (DGK) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50F REF5050IDGKT Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50F REF5050IDGKT.A Active Production VSSOP (DGK) | 8 250 | SMALL T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 R50F REF5050IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5050 REF5050IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 125 REF 5050 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 7

www.ti.com 18-Jul-2026 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 8

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REF5010AIDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5010AIDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5010AIDR SOIC D 8 2500 353.0 353.0 32.0 REF5010AIDRG4 SOIC D 8 2500 353.0 353.0 32.0 REF5010IDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5010IDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5020AIDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5020AIDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5020AIDR SOIC D 8 2500 353.0 353.0 32.0 REF5020IDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5020IDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5020IDR SOIC D 8 2500 353.0 353.0 32.0 REF5025AIDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5025AIDGKRG4 VSSOP DGK 8 2500 353.0 353.0 32.0 REF5025AIDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5025AIDR SOIC D 8 2500 353.0 353.0 32.0 REF5025AIDR1G4 SOIC D 8 2500 353.0 353.0 32.0 REF5025EIDR SOIC D 8 3000 353.0 353.0 32.0 Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REF5025IDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5025IDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5025IDR SOIC D 8 2500 353.0 353.0 32.0 REF5030AIDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5030AIDGKRG4 VSSOP DGK 8 2500 353.0 353.0 32.0 REF5030AIDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5030AIDR SOIC D 8 2500 353.0 353.0 32.0 REF5030AIDRG4 SOIC D 8 2500 353.0 353.0 32.0 REF5030EIDR SOIC D 8 3000 353.0 353.0 32.0 REF5030IDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5030IDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5030IDR SOIC D 8 2500 353.0 353.0 32.0 REF5040AIDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5040AIDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5040AIDGKTG4 VSSOP DGK 8 250 213.0 191.0 35.0 REF5040AIDR SOIC D 8 2500 353.0 353.0 32.0 REF5040AIDRG4 SOIC D 8 2500 353.0 353.0 32.0 REF5040EIDR SOIC D 8 3000 353.0 353.0 32.0 REF5040IDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5040IDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5040IDR SOIC D 8 2500 353.0 353.0 32.0 REF5045AIDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5045AIDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5045AIDR SOIC D 8 2500 353.0 353.0 32.0 REF5045EIDR SOIC D 8 3000 353.0 353.0 32.0 REF5045IDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5045IDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5045IDR SOIC D 8 2500 353.0 353.0 32.0 REF5050AIDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5050AIDGKRG4 VSSOP DGK 8 2500 353.0 353.0 32.0 REF5050AIDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5050AIDR SOIC D 8 2500 353.0 353.0 32.0 REF5050EIDR SOIC D 8 3000 353.0 353.0 32.0 REF5050IDGKR VSSOP DGK 8 2500 353.0 353.0 32.0 REF5050IDGKT VSSOP DGK 8 250 213.0 191.0 35.0 REF5050IDR SOIC D 8 2500 353.0 353.0 32.0 Pack Materials-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) REF5010AID D SOIC 8 75 506.6 8 3940 4.32 REF5010AID.A D SOIC 8 75 506.6 8 3940 4.32 REF5010ID D SOIC 8 75 506.6 8 3940 4.32 REF5010ID.A D SOIC 8 75 506.6 8 3940 4.32 REF5020AID D SOIC 8 75 506.6 8 3940 4.32 REF5020AID.A D SOIC 8 75 506.6 8 3940 4.32 REF5020ID D SOIC 8 75 506.6 8 3940 4.32 REF5020ID.A D SOIC 8 75 506.6 8 3940 4.32 REF5025AID D SOIC 8 75 506.6 8 3940 4.32 REF5025AID.A D SOIC 8 75 506.6 8 3940 4.32 REF5025ID D SOIC 8 75 506.6 8 3940 4.32 REF5025ID.A D SOIC 8 75 506.6 8 3940 4.32 REF5030AID D SOIC 8 75 506.6 8 3940 4.32 REF5030AID.A D SOIC 8 75 506.6 8 3940 4.32 REF5030ID D SOIC 8 75 506.6 8 3940 4.32 REF5030ID.A D SOIC 8 75 506.6 8 3940 4.32 REF5040AID D SOIC 8 75 506.6 8 3940 4.32 REF5040AID.A D SOIC 8 75 506.6 8 3940 4.32 REF5040ID D SOIC 8 75 506.6 8 3940 4.32 REF5040ID.A D SOIC 8 75 506.6 8 3940 4.32 REF5045AID D SOIC 8 75 506.6 8 3940 4.32 REF5045AID.A D SOIC 8 75 506.6 8 3940 4.32 REF5045ID D SOIC 8 75 506.6 8 3940 4.32 REF5045ID.A D SOIC 8 75 506.6 8 3940 4.32 REF5050AID D SOIC 8 75 506.6 8 3940 4.32 REF5050AID.A D SOIC 8 75 506.6 8 3940 4.32 REF5050ID D SOIC 8 75 506.6 8 3940 4.32 REF5050ID.A D SOIC 8 75 506.6 8 3940 4.32 Pack Materials-Page 5

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.1 MAX

0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM

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