REF20-Q1

REF20xx-Q1 Low-Drift, Low-Power, Dual-Output, VREF and VREF / 2 Voltage References datasheet

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SBOSA80,*]
• PDF pages: 36

Technical content

REF20xx-Q1 Low-Drift, Low-Power, Dual-Output, VREF and VREF / 2 Voltage References

1 Features

• AEC-Q100 qualified with the following results: – Device temperature grade 1: –40°C to +125°C ambient operating temperature – Device HBM ESD classification level 2 – Device CDM ESD classification level C7B
• Functional Safety-Capable – Documentation available to aid functional safety system design
• Two Outputs, VREF and VREF / 2, for convenient use in single-supply systems
• Excellent temperature drift performance: – 8 ppm/°C (maximum) from –40°C to 125°C
• High initial accuracy: ±0.05% (maximum)
• VREF and VBIAS tracking overtemperature: – 7 ppm/°C (maximum) from –40°C to 125°C
• Microsize package: SOT23-5
• Low dropout voltage: 10 mV
• High output current: ±20 mA
• Low quiescent current: 360 μA
• Line regulation: 3 ppm/V
• Load regulation: 8 ppm/mA

2 Applications

• Telematics control
• Battery management systems
• Inverter and motor control
• Automotive gateway
• Power distribution box
• Power steering
• On board chargers

3 Description

Applications with only a positive supply voltage often require additional stable voltage in the middle of the analog-to-digital converter (ADC) input range to bias input bipolar signals. The REF20xx-Q1 provides a reference voltage (V REF) for the ADC and a second highly-accurate voltage (V BIAS) that can be used to bias the input bipolar signals. The REF20xx-Q1 offers excellent temperature drift (8 ppm/°C, maximum) and initial accuracy (0.05%) on both the V REF and V BIAS outputs while operating at a quiescent current less than 430 µA. In addition, the V REF and V BIAS outputs track each other with a precision of 7 ppm/°C (maximum) across the temperature range of –40°C to 125°C. All these features increase the precision of the signal chain and decrease board space, while reducing the cost of the system as compared to a discrete solution. Extremely low dropout voltage of only 10 mV allows operation from very low input voltages, which can be very useful in battery-operated systems. Both the V REF and V BIAS voltages have the same excellent specifications and can sink and source current equally well. Very good long-term stability and low noise levels make these devices ideally-suited for high-precision applications. Device Information PART NAME PACKAGE (1) BODY SIZE (NOM) REF20xx-Q1 SOT-23 (5) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. INA240-Q1 VIN REF20-Q1 VREF = 3.0 VVBIAS = 1.5 V EN ADC GND LOAD ISENSERSHUNT VIN- VIN+ REF1 VOUT Power Supply REF2 Application Example -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 ±75 ±50 ±25 0 25 50 75 100 125 150 Output Voltage Accuracy (%) Temperature (ƒC) C001 VREF VBIAS VREF and VBIAS vs Temperature REF20-Q1 SBOSA80 – DECEMBER 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

13.2 Receiving Notification of Documentation Updates..28

14 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES December 2021 * Initial Release REF20-Q1 SBOSA80 – DECEMBER 2021 www.ti.com

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5 Device Comparison Table

REF2025-Q1 2.5 V 1.25 V REF2030-Q1 3.0 V 1.5 V REF2033-Q1 3.3 V 1.65 V REF2041-Q1 4.096 V 2.048 V www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: REF20-Q1

6 Pin Configuration and Functions

Figure 6-1. DDC Package SOT23-5 (Top View) Table 6-1. Pin Functions PIN I/O DESCRIPTION NO. NAME

1 VBIAS Output Bias voltage output (VREF / 2)

2 GND — Ground

3 EN Input Enable (EN ≥ VIN – 0.7 V, device enabled)

4 VIN Input Input supply voltage

5 VREF Output Reference voltage output (VREF)

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Input voltage VIN –0.3 6 V EN –0.3 VIN + 0.3 Temperature Operating –55 150 °CJunction, Tj 150 Storage, Tstg –65 170 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±2500 V Charged-device model (CDM), per AEC Q100-011 ±1500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Supply input voltage range (IL = 0 mA, TA = 25°C) VREF + 0.02 (1) 5.5 V (1) See Figure 7-27 in Section 7.6 for minimum input voltage at different load currents and temperature

7.4 Thermal Information

THERMAL METRIC (1) REF20xx-Q1 UNITDDC (SOT23)

5 PINS

RθJA Junction-to-ambient thermal resistance 193.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 40.2 °C/W RθJB Junction-to-board thermal resistance 34.5 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 34.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: REF20-Q1

7.5 Electrical Characteristics

At TA = 25°C, IL = 0 mA, and VIN = 5 V, unless otherwise noted. Both VREF and VBIAS have the same specifications. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ACCURACY AND DRIFT Output voltage accuracy –0.05% 0.05% Output voltage temperature coefficient (1) –40°C ≤ TA ≤ 125°C ±3 ±8 ppm/°C VREF and VBIAS tracking over temperature (2) –40°C ≤ TA ≤ 125°C ±2 ±7 ppm/°C LINE AND LOAD REGULATION ΔVO(ΔVI) Line regulation VREF + 0.02 V ≤ VIN ≤ 5.5 V 3 35 ppm/V ΔVO(ΔIL) Load regulation Sourcing 0 mA ≤ IL ≤ 20 mA , VREF + 0.6 V ≤ VIN ≤ 5.5 V 8 20 ppm/mA Sinking 0 mA ≤ IL ≤ –20 mA, VREF + 0.02 V ≤ VIN ≤ 5.5 V 8 20 POWER SUPPLY ICC Supply current Active mode 360 430 µA –40°C ≤ TA ≤ 125°C 460 Shutdown mode 3.3 5 –40°C ≤ TA ≤ 125°C 9 Enable voltage Device in shutdown mode (EN = 0) 0 0.7 V Device in active mode (EN = 1) VIN – 0.7 VIN Dropout voltage 10 20 mV IL = 20 mA 600 ISC Short-circuit current 50 mA ton Turn-on time 0.1% settling, CL = 1 µF 500 µs NOISE Low-frequency noise (3) 0.1 Hz ≤ f ≤ 10 Hz 12 ppmPP Output voltage noise density f = 100 Hz 0.25 ppm/√ Hz CAPACITIVE LOAD Stable output capacitor range 0 10 µF HYSTERESIS AND LONG TERM STABILITY Long-term stability (4) 0 to 1000 hours 25 ppm Output voltage hysteresis (5) 25°C, –40°C, 125°C, 25°C Cycle 1 60 ppm Cycle 2 35 (1) Temperature drift is specified according to the box method. See the Section 9.3 section for more details. (2) The VREF and VBIAS tracking over temperature specification is explained in more detail in the Section 9.3 section. (3) The peak-to-peak noise measurement procedure is explained in more detail in the Section 8.4 section. (4) Long-term stability measurement procedure is explained in more in detail in the Section 8.2 section. (5) The thermal hysteresis measurement procedure is explained in more detail in the Section 8.3 section. REF20-Q1 SBOSA80 – DECEMBER 2021 www.ti.com

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7.6 Typical Characteristics

At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted. -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 Population (%) VREF Initial Accuracy (%) C010 Figure 7-1. Initial Accuracy Distribution (VREF) 0 1 2 3 4 5 6 7 8 Population (%) VREF Drift Distribution (ppm/ƒC) C015 –40°C ≤ TA ≤ 125°C Figure 7-2. Drift Distribution (VREF) -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 Population (%) VBIAS Initial Accuracy (%) C008 Figure 7-3. Initial Accuracy Distribution (VBIAS) 0 1 2 3 4 5 6 7 8 Population (%) VBIAS Drift Distribution (ppm/ƒC) C015 –40°C ≤ TA ≤ 125°C Figure 7-4. Drift Distribution (VBIAS) ±100 ±80 ±60 ±40 ±20 Population (%) VREF and VBIAS Matching (ppm) C004 Figure 7-5. VREF – 2 × VBIAS Distribution 0 1 2 3 4 5 6 7 Population (%) VREF and VBIAS Tracking Over Temperature (ppm/ƒC) C017 –40°C ≤ TA ≤ 125°C Figure 7-6. Distribution of VREF – 2 × VBIAS Drift Tracking Over Temperature www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: REF20-Q1

7.6 Typical Characteristics (continued)

At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted. Population (%) Solder Heat Shift Histogram - VREF (%) C041 Refer to the Section 8.1 section for more information. Figure 7-7. Solder Heat Shift Distribution (VREF) Population (%) Solder Heat Shift Histogram - VBIAS (%) C040 Refer to the Section 8.1 section for more information. Figure 7-8. Solder Heat Shift Distribution (VBIAS) -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 ±75 ±50 ±25 0 25 50 75 100 125 150 Output Voltage Accuracy (%) Temperature (ƒC) C001 VREF VBIAS Figure 7-9. Output Voltage Accuracy (VREF) vs Temperature ±1000 ±750 ±500 ±250 250 500 750 1000 ±75 ±50 ±25 0 25 50 75 100 125 150 VREF - 2 x VBIAS (ppm) Temperature (ƒC) C003 Figure 7-10. VREF – 2 × VBIAS Tracking vs Temperature 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 ±20 ±15 ±10 ±5 0 5 10 15 20 VREF (V) Load Current (mA) C038 125°C 25°C -40°C VREF output Figure 7-11. Output Voltage Change vs Load Current (VREF) 1.2493 1.2495 1.2497 1.2499 1.2501 1.2503 ±20 ±15 ±10 ±5 0 5 10 15 20 VBIAS (V) Load Current (mA) C039 125°C 25°C -40°C VBIAS output Figure 7-12. Output Voltage Change vs Load Current (VBIAS) REF20-Q1 SBOSA80 – DECEMBER 2021 www.ti.com

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At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted. ±75 ±50 ±25 0 25 50 75 100 125 150 VREF - Load Regulation Sourcing (ppm/mA) Temperature (ƒC) C025 VREF output IL = 20 mA Figure 7-13. Load Regulation Sourcing vs Temperature (VREF) ±75 ±50 ±25 0 25 50 75 100 125 150 VBIAS - Load Regulation Sourcing (ppm/mA) Temperature (ƒC) C020 VBIAS output IL = 20 mA Figure 7-14. Load Regulation Sourcing vs Temperature (VBIAS) ±75 ±50 ±25 0 25 50 75 100 125 150 VREF - Load Regulation Sinking (ppm/mA) Temperature (ƒC) C021 VREF output IL = –20 mA Figure 7-15. Load Regulation Sinking vs Temperature (VREF) ±75 ±50 ±25 0 25 50 75 100 125 150 VBIAS - Load Regulation Sinking (ppm/mA) Temperature (ƒC) C022 VBIAS output IL = –20 mA Figure 7-16. Load Regulation Sinking vs Temperature (VBIAS) 2.5 3.5 4.5 ±75 ±50 ±25 0 25 50 75 100 125 150 VREF Line Regulation (ppm/V) Temperature (ƒC) C019 VREF output Figure 7-17. Line Regulation vs Temperature (VREF) 2.5 3.5 4.5 ±75 ±50 ±25 0 25 50 75 100 125 150 VBIAS Line Regulation (ppm/V) Temperature (ƒC) C018 VBIAS output Figure 7-18. Line Regulation vs Temperature (VBIAS) www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: REF20-Q1

At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted. 100 1 10 100 1k 10k 100k PSRR (dB) Frequency (Hz) C026 VREF VBIAS CL = 0 µF Figure 7-19. Power-Supply Rejection Ratio vs Frequency 100 1 10 100 1k 10k 100k PSRR (dB) Frequency (Hz) C027 VREF VBIAS CL = 10 µF Figure 7-20. Power-Supply Rejection Ratio vs Frequency Time (500 µs/div) C006 500 mV/div 40 mV/div VIN - 0.25 V VIN + 0.25 V VIN + 0.25 V VREF CL = 1 µF Figure 7-21. Line Transient Response Time (500 µs/div) C006 500 mV/div 40 mV/div VIN - 0.25V VIN + 0.25V VIN + 0.25 V VREF CL = 10 µF Figure 7-22. Line Transient Response Time (500 µs/div) C032 +1 mA +1 mA - 1 mA 2 mA/div 20 mV/div VREF CL = 1 µF IL = ±1-mA step Figure 7-23. Load Transient Response 20 mV/div Time (500 µs/div) C037 +1 mA +1 mA - 1 mA 2 mA/div VREF CL = 10 µF IL = ±1-mA step Figure 7-24. Load Transient Response REF20-Q1 SBOSA80 – DECEMBER 2021 www.ti.com

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At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted. Time (500 µs/div) C031 VREF 40 mA/div -20 mA +20 mA +20 mA 40 mV/div CL = 1 µF IL = ±20-mA step Figure 7-25. Load Transient Response Time (500 µs/div) C036 40 mA/div +20 mA -20 mA +20 mA +20 mA +20 mA 40 mV/div VREF CL = 10 µF IL = ±20-mA step Figure 7-26. Load Transient Response 100 200 300 400 ±30 ±20 ±10 0 10 20 30 Dropout Voltage (mV) Load Current (mA) C005 25°C ±40°C 125°C Figure 7-27. Minimum Dropout Voltage vs Load Current

2 V/div

Time (100 µs/div) C033 VIN VREF CL = 1 µF Figure 7-28. Turn-On Settling Time Time (100 µs/div) C034 VIN VREF CL = 10 µF Figure 7-29. Turn-On Settling Time 200 250 300 350 400 450 500 ±75 ±50 ±25 0 25 50 75 100 125 150 Quiescent Current ( Temperature (ƒC) C006 Figure 7-30. Quiescent Current vs Temperature www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: REF20-Q1

At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted. 200 250 300 350 400 450 500 2 3 4 5 6 Quiescent Current ( Input Voltage (V) C007 Figure 7-31. Quiescent Current vs Input Voltage Voltage (5 V/div) Time (1 s/div) C028 VREF output Figure 7-32. 0.1-Hz to 10-Hz Noise (VREF) Voltage (5 V/div) Time (1 s/div) C029 VBIAS output Figure 7-33. 0.1-Hz to 10-Hz Noise (VBIAS) 0.01 0.1 1 10 100 1k 10k 2XWSXW1RLVH6SHFWUDO'HQVLW\\ SSP¥+] Frequency (Hz) C030 CL = 0 µF CL = 4.7 F CL = 10 µF Figure 7-34. Output Voltage Noise Spectrum 0.01 0.1 100 0.01 0.1 1 10 100 1k 10k 100k Output Impedance ( Frequency (Hz) C024 CL = 0 F CL = 1µF CL = 10 F VREF output Figure 7-35. Output Impedance vs Frequency (VREF) 0.01 0.1 100 0.01 0.1 1 10 100 1k 10k 100k Output Impedance ( Frequency (Hz) C023 CL = 0 F CL = 1µF CL = 10 F VBIAS output Figure 7-36. Output Impedance vs Frequency (VBIAS) REF20-Q1 SBOSA80 – DECEMBER 2021 www.ti.com

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At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted. 100 120 Population (%) Thermal Hysterisis - VREF (ppm) C013 Figure 7-37. Thermal Hysteresis Distribution (VREF) 100 120 Population (%) Thermal Hysteresis - VBIAS (ppm) C014 Figure 7-38. Thermal Hysteresis Distribution (VBIAS) Time (hr) Output Voltage Stability (ppm) 0 100 200 300 400 500 600 700 800 900 1000 -10 Figure 7-39. Long-Term Stability (First 1000 Hours) www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: REF20-Q1

8 Parameter Measurement Information

8.1 Solder Heat Shift

The materials used in the manufacture of the REF20xx-Q1 have differing coefficients of thermal expansion, resulting in stress on the device die when the part is heated. Mechanical and thermal stress on the device die can cause the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow soldering is a common cause of this error. To illustrate this effect, a total of 92 devices were soldered on four printed circuit boards [23 devices on each printed circuit board (PCB)] using lead-free solder paste and the paste manufacturer suggested reflow profile. The reflow profile is as shown in Figure 8-1. The printed circuit board is comprised of FR4 material. The board thickness is 1.57 mm and the area is 171.54 mm × 165.1 mm. The reference and bias output voltages are measured before and after the reflow process; the typical shift is displayed in Figure 8-2 and Figure 8-3. Although all tested units exhibit very low shifts (< 0.01%), higher shifts are also possible depending on the size, thickness, and material of the printed circuit board. An important note is that the histograms display the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is common on PCBs with surface-mount components on both sides, causes additional shifts in the output bias voltage. If the PCB is exposed to multiple reflows, the device must be soldered in the second pass to minimize its exposure to thermal stress. 100 150 200 250 300 0 50 100 150 200 250 300 350 400 Temperature (ƒC) Time (seconds) C01 Figure 8-1. Reflow Profile Population (%) Solder Heat Shift Histogram - VREF (%) C041 Figure 8-2. Solder Heat Shift Distribution, VREF (%) Population (%) Solder Heat Shift Histogram - VBIAS (%) C040 Figure 8-3. Solder Heat Shift Distribution, VBIAS (%) REF20-Q1 SBOSA80 – DECEMBER 2021 www.ti.com

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8.2 Long-Term Stability

The long term stability of the REF20xx-Q1 was collected on 32 parts that were soldered onto Printed Circuit Boards without any slots or special layout considerations. The boards were then placed into an oven with air temperature maintained at TA = 35°C. The Vref output of the 32 parts was measured regularly. Typical long term stability is as shown in Figure 8-4. Time (hr) Output Voltage Stability (ppm) 0 100 200 300 400 500 600 700 800 900 1000 -10 Figure 8-4. Long Term Stability – 1000 hours (VREF) www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: REF20-Q1

8.3 Thermal Hysteresis

Thermal hysteresis is measured with the REF20xx-Q1 soldered to a PCB, similar to a real-world application. Thermal hysteresis for the device is defined as the change in output voltage after operating the device at 25°C, cycling the device through the specified temperature range, and returning to 25°C. Hysteresis can be expressed by Equation 1: PRE POST 6 HYST NOM V V V 10 (ppm)V § · x ¨ ¸ ¨ ¸ © ¹ (1) where

• VHYST = thermal hysteresis (in units of ppm)
• VNOM = the specified output voltage
• VPRE = output voltage measured at 25°C pre-temperature cycling
• VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature range of –40°C to 125°C and returns to 25°C Typical thermal hysteresis distribution is as shown in Figure 8-5 and Figure 8-6. 100 120 Population (%) Thermal Hysterisis - VREF (ppm) C013 Figure 8-5. Thermal Hysteresis Distribution (VREF) 100 120 Population (%) Thermal Hysteresis - VBIAS (ppm) C014 Figure 8-6. Thermal Hysteresis Distribution (VBIAS) REF20-Q1 SBOSA80 – DECEMBER 2021 www.ti.com

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8.4 Noise Performance

Typical 0.1-Hz to 10-Hz voltage noise can be seen in Figure 8-7 and Figure 8-8 . Device noise increases with output voltage and operating temperature. Additional filtering can be used to improve output noise levels, although care must be taken to ensure the output impedance does not degrade ac performance. Peak-to-peak noise measurement setup is shown in Figure 8-9. Voltage (5 V/div) Time (1 s/div) C028 Figure 8-7. 0.1-Hz to 10-Hz Noise (VREF) Voltage (5 V/div) Time (1 s/div) C029 Figure 8-8. 0.1-Hz to 10-Hz Noise (VBIAS) 40 mF

10 F 1 k

0.1 Hz to 10 Hz Filter

0.1 F Figure 8-9. 0.1-Hz to 10-Hz Noise Measurement Setup www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: REF20-Q1

9 Detailed Description

9.1 Overview

The REF20xx-Q1 are a family of dual-output, V REF and V BIAS (VREF / 2) band-gap voltage references. The Section 9.1 section provides a block diagram of the basic band-gap topology and the two buffers used to derive the VREF and VBIAS outputs. Transistors Q1 and Q2 are biased such that the current density of Q 1 is greater than that of Q2. The difference of the two base emitter voltages (V BE1 – VBE2) has a positive temperature coefficient and is forced across resistor R5. The voltage is amplified and added to the base emitter voltage of Q 2, which has a negative temperature coefficient. The resulting band-gap output voltage is almost independent of temperature. Two independent buffers are used to generate V REF and VBIAS from the band-gap voltage. The resistors R 1, R2 and R3, R4 are sized such that VBIAS = VREF / 2. e-Trim™ is a method of package-level trim for the initial accuracy and temperature coefficient of V REF and VBIAS, implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent transistor mismatch, as well as errors induced during package molding. e-Trim is implemented in the REF20xx-Q1 to minimize the temperature drift and maximize the initial accuracy of both the VREF and VBIAS outputs.

9.2 Functional Block Diagram

• - + + R7R6

9.3 Feature Description

9.3.1 VREF and VBIAS Tracking

Most single-supply systems require an additional stable voltage in the middle of the analog-to-digital converter (ADC) input range to bias input bipolar signals. The V REF and V BIAS outputs of the REF20xx-Q1 are generated from the same band-gap voltage as shown in the Section 9.2. Hence, both outputs track each other over the full temperature range of –40°C to 125°C with an accuracy of 7 ppm/°C (maximum). The tracking error is calculated using the box method, as described by Equation 2: DIFF(MAX) DIFF (MIN) 6 REF V V Tracking Error 10 (ppm)V Temperature Range (2) where ‡DIFF REF BIASV V 2 V REF20-Q1 SBOSA80 – DECEMBER 2021 www.ti.com

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The tracking accuracy is as shown in Figure 9-1. -0.05 -0.04 -0.03 -0.02 -0.01 0.01 0.02 0.03 0.04 0.05 ±75 ±50 ±25 0 25 50 75 100 125 150 Output Voltage Accuracy (%) Temperature (ƒC) C001 VREF VBIAS Figure 9-1. VREF and VBIAS Tracking vs Temperature

9.3.2 Low Temperature Drift

The REF20xx-Q1 is designed for minimal drift error, which is defined as the change in output voltage over temperature. The drift is calculated using the box method, as described by Equation 3: REF(MAX) REF(MIN) 6 REF V V Drift 10 (ppm)V Temperature Range (3)

9.3.3 Load Current

The REF20xx-Q1 family is specified to deliver a current load of ±20 mA per output. Both the V REF and V BIAS outputs of the device are protected from short circuits by limiting the output short-circuit current to 50 mA. The device temperature increases according to Equation 4: ‡J A D -$T T P R (4) where

• TJ = junction temperature (°C)
• TA = ambient temperature (°C)
• PD = power dissipated (W)
• RθJA = junction-to-ambient thermal resistance (°C/W) The REF20xx-Q1 maximum junction temperature must not exceed the absolute maximum rating of 150°C.

9.4 Device Functional Modes

When the EN pin of the REF20xx-Q1 is pulled high, the device is in active mode. The device must be in active mode for normal operation. The REF20xx-Q1 can be placed in a low-power mode by pulling the ENABLE pin low. When in shutdown mode, the output of the device becomes high impedance and the quiescent current of the device reduces to 5 µA in shutdown mode. See the Section 7.5 for logic high and logic low voltage levels. www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: REF20-Q1

10 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

10.1 Application Information

The low-drift, bidirectional, single-supply, low-side, current-sensing solution, described in this section, can Positive current is represented by output voltages from 1.5 V to 2.75 V, whereas negative current is represented by output voltages from 250 mV to 1.5 V. The difference amplifier is the INA240-Q1 current-shunt monitor, whose supply and reference voltages are supplied by the low-drift REF2030-Q1.

10.2 Typical Application

10.2.1 Low-Side, Current-Sensing Application

±ILOAD VBUS +IN+ IN- REF1 OUT Reference VS VCC VREF VBIAS VIN EN GND GND VOUT REF20-Q1 INA240-Q1 ADC VREF REF2 Figure 10-1. Low-Side, Current-Sensing Application REF20-Q1 SBOSA80 – DECEMBER 2021 www.ti.com

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10.2.1.1 Design Requirements

The design requirements are as follows: 1. Supply voltage: 5.0 V 2. Load current: ±2.5 A 3. Output: 250 mV to 2.75 V 4. Maximum shunt voltage: ±25 mV

10.2.1.2 Detailed Design Procedure

Low-side current sensing is desirable because the common-mode voltage is near ground. Therefore, the current- sensing solution is independent of the bus voltage, V BUS. When sensing bidirectional currents, use a differential amplifier with a reference pin. This procedure allows for the differentiation between positive and negative currents by biasing the output stage such that it can respond to negative input voltages. There are a variety of methods for supplying power (V+) and the reference voltage (V REF, or V BIAS) to the differential amplifier. For a low-drift solution, use a monolithic reference that supplies both power and the reference voltage. Figure 10-2 shows the general circuit topology for a low-drift, low-side, bidirectional, current-sensing solution. This topology is particularly useful when interfacing with an ADC; see Figure 10-1 . Not only do V REF and V BIAS track over temperature, but their matching is much better than alternate topologies. RSHUNT ±ILOAD VBUS IN+ IN- OUT Reference VCC VREF VBIAS VIN EN GND GND VOUT REF20-Q1 INA240-Q1 ± VSHUNT REF1 VS REF2 Figure 10-2. Low-Drift, Low-Side, Bidirectional, Current-Sensing Circuit Topology The transfer function for the circuit given in Figure 10-2 is as shown in Equation 5: OUT SHUNT BIAS LOAD SHUNT BIAS V G V V G I R V r r (5) www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: REF20-Q1

10.2.1.2.1 Shunt Resistor

As illustrated in Figure 10-2 , the value of V SHUNT is the ground potential for the system load. If the value of VSHUNT is too large, issues may arise when interfacing with systems whose ground potential is actually 0 V. Also, a value of V SHUNT that is too negative may violate the input common-mode voltage of the differential amplifier in addition to potential interfacing issues. Therefore, limiting the voltage across the shunt resistor is important. Equation 6 can be used to calculate the maximum value of RSHUNT. (max)LOAD (max)SHUNT (max)SHUNT I V R (6) Given that the maximum shunt voltage is ±25 mV and the load current range is ±2.5 A, the maximum shunt resistance is calculated as shown in Equation 7. : m10A 5 . 2 mV25 I V R (m ax)LOA D (m ax)SH UN T (m ax)SH UN T (7) To minimize errors over temperature, select a low-drift shunt resistor. To minimize offset error, select a shunt resistor with the lowest tolerance. For this design, the Y14870R01000B9W resistor is used.

10.2.1.2.2 Differential Amplifier

The differential amplifier used for this design must have the following features: 1. Single-supply (3 V) 2. Reference voltage input 3. Low initial input offset voltage (VOS) 4. Low-drift 5. Fixed gain 6. Low-side sensing (input common-mode range below ground) For this design, a current-shunt monitor (INA240-Q1) is used. The INA240-Q1 family topology is shown in Figure 10-3. The INA240-Q1 specifications can be found in the INA240-Q1 product data sheet. OUT GND REF1 VS REF2 IN+ IN- Figure 10-3. INA240-Q1 Current-Shunt Monitor Topology The INA240-Q1 is an excellent choice for this application because all the required features are included. In general, instrumentation amplifiers (INAs) do not have the input common-mode swing to ground that is essential for this application. In addition, INAs require external resistors to set their gain, which is not desirable for low-drift applications. Difference amplifiers typically have larger input bias currents, which reduce solution accuracy at small load currents. Difference amplifiers typically have a gain of 1 V/V. When the gain is adjustable, these amplifiers use external resistors that are not conducive to low-drift applications. REF20-Q1 SBOSA80 – DECEMBER 2021 www.ti.com

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10.2.1.2.3 Voltage Reference

The voltage reference for this application must have the following features: 1. Dual output (3.0 V and 1.5 V) 2. Low drift 3. Low tracking errors between the two outputs For this design, the REF2030-Q1 is used. The REF20xx-Q1 topology is as shown in the Section 9.2 section. The REF2030-Q1 is an excellent choice for this application because of its dual output. The temperature drift of 8 ppm/°C and initial accuracy of 0.05% make the errors resulting from the voltage reference minimal in this application. In addition, there is minimal mismatch between the two outputs and both outputs track very well across temperature, as shown in Figure 10-4 and Figure 10-5. ±100 ±80 ±60 ±40 ±20 Population (%) VREF and VBIAS Matching (ppm) C004 Figure 10-4. VREF – 2 × VBIAS Distribution (At TA = 25°C) 0 1 2 3 4 5 6 Population (%) VREF and VBIAS Tracking Over Temperature (ppm/ƒC) C016 Figure 10-5. Distribution of VREF – 2 × VBIAS Drift Tracking Over Temperature

10.2.1.2.4 Error Calculations

Two types of errors will be discussed: initial accuracy and drift. Accuracy errors include:

• Shunt resistor tolerance: αshunt_tol = 0.1% (maximum)
• INA initial input offset voltage: VOS_INA = 5 μV (typical)
• INA PSRR: VOS_INA_PSRR = 1 μV/V (typical)
• INA CMRR: VOS_INA_CMRR = 132 dB (typical)
• INA gain error: αINA_GE = 0.05% (typical)
• Reference output accuracy: αREF_output = 0.05% (maximum) It should be noted that these error sources can be greatly reduced at 25ºC by performing a two point system calibration. Drift errors, on the other hand, can only be reduced by performing the calibration over temperature. The drift errors include:
• Shunt resistor drift: δshunt_drift = 15 ppm/ºC (maximum)
• INA offset voltage drift: δINA_drift_Vos = 50 nV/ºC (typical)
• INA gain error drift: δINA_drift_GE = 0.5 ppm/ºC (typical)
• Reference output drift: δREF_drift_output = 3 ppm/ºC (typical) Equation 8 can be used to convert specifications given in parts per million (ppm) to a percentage (%), and vice versa. Equation 9 can be used to convert specifications given in decibels (dB) to a linear representation. www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: REF20-Q1

For some error calculations a full-scale range (FSR) is required. The FSR for this design is determined by the voltage across the shunt resistor, which is ±25 mV (or 50 mV). For drift errors, the largest change in temperature ( ΔT) is 100ºC, which is the difference between the maximum specified temperature (125ºC) and room temperature (25ºC). This temperature change is used when calculating drift errors for the shunt resistor and INA240-Q1. Because the REF20-Q1 uses the box method to determine drift, the temperature range used for calculations is the entire operating range, or 150ºC. Finally, errors due to CMRR and PSRR specifications require an adjustment depending on the difference between the system’s requirements and how the devices were characterized. For example, the INA240-Q1 was characterized using a common-mode voltage of 12 V. The common-mode voltage in this design is ~0V. This discrepancy causes an input-referred offset voltage. Below, Table 10-1 summarizes the initial accuracy calculations. Table 10-1. Initial Accuracy Error Summary ERROR SOURCE DEVICE: RSHUNT (PPM) DEVICE: IN240-Q1 (PPM) DEVICE: REF2030-Q1 (PPM) TOTAL (PPM, RSS) OFFSET 100 FSR 500 FSR 510 FSR CMRR 60 FSR 60 FSR PSRR 40 FSR 40 FSR GAIN ERROR 1000 500 1118 TOTAL (PPM, RSS) 1000 1087.5 FSR 500 FSR 1231 FSR (0.123%) Below, Table 10-2 summarizes the total temperature drift calculations. Table 10-2. Temperature Drift Error Summary ERROR SOURCE DEVICE: RSHUNT (PPM) DEVICE: IN240-Q1 (PPM) DEVICE: REF2030-Q1 (PPM) TOTAL (PPM, RSS) OFFSET DRIFT 100 FSR 495 505 FSR GAIN ERROR DRIFT 1500 50 1501 TOTAL (PPM, RSS) 1500 111.8 FSR 495 1583.52 FSR (0.194%) REF20-Q1 SBOSA80 – DECEMBER 2021 www.ti.com

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10.2.1.2.5 Application Curves

Performing a two-point calibration at 25°C removes the errors associated with offset voltage, gain error, and so forth. Figure 10-6 to Figure 10-8 show the measured error at different conditions. For a more detailed description on measurement procedure, calibration, and calculations, please refer to TIDU357. 0.5 1.5 2.5 -3 -2 -1 0 1 2 3 Output Voltage (Vout) Load current (mA) C00 Figure 10-6. Measured Transfer Function ±800 ±600 ±400 ±200 200 400 600 800 ±3 ±2 ±1 0 1 2 3 Uncalibrated error (ppm) Load current (mA) C00 -40°C 0°C 25°C 85°C 125°C Figure 10-7. Uncalibrated Error vs Load Current ±800 ±600 ±400 ±200 200 400 600 800 ±3 ±2 ±1 0 1 2 3 Calibrated error (ppm) Load current (mA) C00 -40°C 0°C 25°C 85°C 125°C Figure 10-8. Calibrated Error vs Load Current www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: REF20-Q1

11 Power-Supply Recommendations

The REF20xx-Q1 family of references feature an extremely low-dropout voltage. These references can be operated with a supply of only 20 mV above the output voltage. For loaded reference conditions, a typical dropout voltage versus load is shown in Figure 11-1. A supply bypass capacitor ranging between 0.1 µF to 10 µF is recommended. 100 200 300 400 ±30 ±20 ±10 0 10 20 30 Dropout Voltage (mV) Load Current (mA) C005 25°C ±40°C 125°C Figure 11-1. Dropout Voltage vs Load Current REF20-Q1 SBOSA80 – DECEMBER 2021 www.ti.com

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12 Layout

12.1 Layout Guidelines

Figure 12-1 shows an example of a PCB layout for a data acquisition system using the REF2030-Q1. Some key considerations are:

• Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF, and VBIAS of the REF2030-Q1.
• Decouple other active devices in the system per the device specifications.
• Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
• Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
• Minimize trace length between the reference and bias connections to the INA and ADC to reduce noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary.

12.2 Layout Example

C GND OUT C C Figure 12-1. Layout Example www.ti.com REF20-Q1 SBOSA80 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: REF20-Q1

13 Device and Documentation Support

13.1 Documentation Support

13.1.1 Related Documentation

For related documentation see the following:

• INA240-Q1 Automotive, Wide Common-Mode Range, High- and Low-Side, Bidirectional, Zero-Drift, Current- Sense Amplifier With Enhanced PWM Rejection (SBOS808)
• Low-Drift Bidirectional Single-Supply Low-Side Current Sensing Reference Design (TIDU357)

13.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

13.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

13.4 Trademarks

e-Trim™ is a trademark of Texas Instruments, Inc. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. REF20-Q1 SBOSA80 – DECEMBER 2021 www.ti.com

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www.ti.com 9-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) REF2025QDDCRQ1 Active Production SOT-23- THIN (DDC) | 5 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 GACQ REF2025QDDCRQ1.B Active Production SOT-23- THIN (DDC) | 5 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 GACQ REF2030QDDCRQ1 Active Production SOT-23- THIN (DDC) | 5 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 GADQ REF2030QDDCRQ1.B Active Production SOT-23- THIN (DDC) | 5 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 GADQ REF2033QDDCRQ1 Active Production SOT-23- THIN (DDC) | 5 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 GAEQ REF2033QDDCRQ1.B Active Production SOT-23- THIN (DDC) | 5 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 GAEQ REF2041QDDCRQ1 Active Production SOT-23- THIN (DDC) | 5 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 GAFQ REF2041QDDCRQ1.B Active Production SOT-23- THIN (DDC) | 5 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 GAFQ (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 1

www.ti.com 9-Nov-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant REF2025QDDCRQ1 SOT-23- THIN REF2030QDDCRQ1 SOT-23- THIN REF2033QDDCRQ1 SOT-23- THIN REF2041QDDCRQ1 SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REF2025QDDCRQ1 SOT-23-THIN DDC 5 3000 213.0 191.0 35.0 REF2030QDDCRQ1 SOT-23-THIN DDC 5 3000 213.0 191.0 35.0 REF2033QDDCRQ1 SOT-23-THIN DDC 5 3000 213.0 191.0 35.0 REF2041QDDCRQ1 SOT-23-THIN DDC 5 3000 213.0 191.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 0.20

0.12 TYP

0.25 GAGE PLANE 3.05 2.55 1.1 0.7 0.1

0.0 TYP

5X 0.5 0.3

0.2 C A B

0.6

0.3 TYP

1.9 0 -8 TYP 0.95 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (0.2) (0.15) SOT-23 - 1.1 max heightDDC0005A SMALL OUTLINE TRANSISTOR 4220752/C 08/2024 SEATING PLANE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC MO-193. 4. Support pin may differ or may not be present. 0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.7) 4X (0.95) (R0.05) TYP 4220752/C 08/2024 SOT-23 - 1.1 max heightDDC0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPLOSED METAL SHOWN SCALE:15X SYMM 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDERMASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.7) 4X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.1 max heightDDC0005A SMALL OUTLINE TRANSISTOR 4220752/C 08/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM SYMM 3 4

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