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R6501

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R6501 ETC

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6500 Microcomputer System

Rockwell One-Chip Microprocessor SUMMARY FEATURES The Rockwell R6501 is a complete, high performance B-bit * Enhanced 6502 CPU NMOS-3 microcomputer on a single chip and is compatible —Four new bit manipulation instructions with all members of the R6500 family ‘+ Set Memory Bit (SMB) ‘The R6501 consists of an enhanced 6502 CPU, an internal Fete ee a oasy. clock oscillator, 192 bytes of Random Access Memory (RAM), earch on a . (ee! oy ‘and versatile interface circuitry. The interface circuitry includes © Branch on Bit Reset (6A) two-l8bit programmable. timericounters. 32 bidirectional —Decimal and binary arithmetic modes inputioutput lines (inckuding four edge-sensitive lines and input 18 acidreesing modes latching on one 8-bit port), a full-duplex serial /O channel, ten Thue indexing interrupts, and bus expandability. + 192-byte static RAM The innovative architecture and the demonstrated high per- * 32 bidirectional, TTL-compatible I/O lines (four ports) formance of the R6502 CPU, as well as instruction simplicity, —One B-bit port may be tri-stated under software contro! results in system cost-effectiveness and a wide range of com- —One 8-bit port may have latched inputs under software putational power. These features make the R50! a leading ‘control candidate for microcomputer application. —Internal pull-up resistors on parts PA, PB, and PC Rockwell supports development of the R6501 with the Low Cost ‘* Two 16-bit programmable counterfiniers, with latches Emulator (LCE) Development System and the R6500/" Family —Pulse width measurement ‘of Personality Modules. Complete in-circuit emulation with the —Asymmetrical pulse generation R500/" Family of Personality Modules allows total system test —Pulse generation ‘and evaluation, —Interval timer This product description assumes that the reader is familiar —Event counter ; with the R6502 CPU hardware and programming capabilities. —Retriggerable interval timer ‘A detailed description of the R6502 CPU hardware is included «Serial port in the R650 Microcomputer System Hardware Manual (Docu- ~Full-duplex asynchronous operation mode ment Order No. 201). A description ofthe instruction capabili- “Selectable 6. to B-bit characters ties of the R6502 CPU is contained in the R6500 Microcom- Wake-up feature puter System Programming Manual (Document Order No. 202) “synchronous shift register mode —Standard programmable bit rates programmable up to ORDERING INFORMATION 25K bitssec @ 1 MHz | Part Number: + Ten interrupts e501 —Four edge-sensitve lines; two positive, two negative | ] —Reset and non-maskable interrupt / Temperature Range (Ty to Ty): —Iwo counter undertiows | No Letter = 0°C to 70°C —Serial data received and serial data transmitted Ee are oe + Bus expandable to 64K bytes of external memory | (industrial) + Flexible clock circuitry | — Package —2 MHz (RBSO1A) or 1 MHz (R65O1) internal operation | J = 68-in Plastic Leaded —Crystal or clock input | Chip Carrier (PLCC) + 118 minimum instruction execution time at 2 MHz } Q = 64-Pin Plastic QUIP * Single +5V power supply | FRtogle = 1 MHz Operation + 12 mW stand-by power for 32 bytes of the 192-byte RAM A = 2MHz Operation + Available in 64-pin plastic QUIP and 68-pin PLCC packages Document No. 29651N48 Product Description Order No. 2145 +3 Rev. 4, June 1987 at

R6501 One-Chip Microprocessor Table 2-1. 6501 Pin Descriptions Vee 1 2 22 POWER, Main power supply. +5V. Vea \\ «3 46 RAN RETENTION POWER. Separate power pin for RAM. In tho event that Voc power is off, this power retains RAM data. +5V. Vss_ 44 48 GROUND. Signal and power ground (OV). XTLt i 42 45 (CRYSTAL IN. Crystal or clock input for internal clock oscillator. Allows input of X1 clock ‘signal if XTLO is connected to Vss, or of X4 (RE501) or X2 (RE501A) clock if XTLO is foates XTLO ° at 44 CRYSTAL OUT. Crystal output from intemal clock oscillator. RES. 1 6 7 RESET. The Reset input is used to initialize the device. This signal must not transition {rom tow to high for atleast eight cycles alter Vee reaches operating range and the internal oscillator has stabilized $2 ° 45 49 PHASE 2 CLOCK, Clock signal output at internal frequency. 3 wi 1 23 25 NON-MASKABLE INTERRUPT. A negative going edge on the Non-Maskable Inter- fupt signal requests that a non-maskable interrupt be generated with the CPU. PAO-PAT vo 39-32 42-35, PORT A. General purpose VO Port A. PCO-PC7 vo ‘54-61 ‘58-65 PORT C. General purpose I/O Port C. PDO-PD7 vo 62-64, 1-5 66, 67,16 PORT D. General purpose I/O Port D. Four 8-dit ports used for either input/output. Each line of Ports A, B and C consists of ‘an active vansistor to Vss and a passive pultup to Vec. Port D functions as elther an bit input or an 8-bit output port. I has active pullup and pulldown transistors. poarz.as | 0 | 2087 219,8 | ADDRESS LINES. Fourteen address lines used to address a complete 65K external address space. Note: A13 and A14 are sourced through PC6 and PC7 when in the Full ‘adress Mode. 80-087 vo | soa6 57-50 | DATALINES. Eight biairectiona data bus ines used to transmit datato and from exter- nal memory. sync ° 2 2 SYNC. SYNC isa positive going signal for the tll clock cycle whenever the CPU isper- forming an OP CODE fetch RW ° “0 43 [READIWRITE. Controls the direction of data transfer between the CPU and the exter- 3-105,

R6501 One-Chip Microprocessor FROSOP SECTION 3 SYSTEM ARCHITECTURE This section provides a functional description of the R6501. location is stored (or “pushed’) onto the stack. Each time Functionally the R6501 consists of a CPU, RAM, four 8-bit data are to be pushed onto the stack, the Stack Pointer is parallel V/O ports, a serial VO port, dual counteriatch circuits, placed on the Address Bus, data are written into the memory ‘a mode control register, and an interrupt flag/enable dual location addressed by the Stack Pointer, and the Stack register circuit, a block diagram of the system is shown in Pointer is decremented by 1. Each time data are read (or Figure 3+ pulled’) from the stack, the Stack Pointer is incremented by 1. The Stack Pointer is then placed on the Address Bus and — data are read from the memory location addressed by the NOTE Pointer. Throughout this document, unless specified otherwise, The stack is located on zer0 page, i... memory locations all memory or register adross locations are speci’ OOFF-0040. After reset, which leaves the Stack Pointer indeterminate, normal usage calls for its initialization at OOFF. 3.1 CPU LOGIC 3.1.4 Arithmetic And Logic Unit (ALU) ‘The R650! internal CPU is a standard 6502 configuration with ‘All anthmatic and logic operations take piace in the ALU, an 8-bit Accumulator register, two 8-bit Index Registers (X and including incrementing and decrementing internal registers Y); an 6-bit Stack Pointer register, an ALU, a 16-bit Program (except the Program Counter). The ALU cannot store data Counter, and standard instruction registerkiecode and internal for more than one cycle. If data are placed on the inputs to timing control logic. the ALU at the beginning of a cycle, the result is always gated into one of the storage registers or to external memory during

3.1.1 Accumulator tho next cycle

The accumulator is a general purpose 8-bit register that stores the results of most arithmetic and logic operations. In Each bit of the ALU has two inputs. These inputs can be tied addition, the accumulator usually contains one of the two {0 various internal buses or to a logic zero; the ALU then data words used in these operations. ‘generates the function (AND, OR, SUM, and so on) using the data on the two inputs.

3.1.2 Index Registers

‘There are two 8-bit index registers, X and Y. Each index reg- 3.1.5 Program Counter ‘ster can be used as a base to modify the address data pro- The 16-bit Program Counter provides the addresses that are gram counter and thus obtain a new address—the sum of Used to step the processor through sequential instructions the program counter contents and the index register contents. in a program. Each time the processor fetches an instruction from program memory, the lower (least significant) byte of When executing an instruction which specifies indirect the Program Counter (PCL) is placed on the low-order bits addressing, the CPU fetches the op code and the address of the Address Bus and the higher (most significant) byte of and modifies the address from memory by adding the index the Program Counter (PCH) is placed on the high-order 8 register to it prior to loading or storing the value of memory. bits of the Address Bus. The Counter is incremented each time an instruction or data is fetched from program memory. Indexing greatly simplifies many types of programs, espe- cially those using data tables. 3.1.6 Instruction Register and Instruction Decode

3.1.3 Stack Pointer Instructions are fetched from ROM or RAM and gated onto

The Stack Pointer is an 6-bit register. It is automatically renee Router meres, nee a wat nda, incremented and decremented under control of the micro- interrupt signals to generate control signals for the various processor to perform stack manipulation in response to either registers. User instructions, an internal IRQ interrupt, of the external interrupt line NMI, The Stack Pointer must be initialized by the usr progam 3.1.7 Timing Control The Timing Control Logic keeps track of the specific instruc- The stack allows simple implementation of multiple level tion cycle being executed. Ths logic is set to TO each time interrupts, subroutine nesting and simplification of many types fan instruction fetch is executed and is advanced at the of data manipulation. The JSR, BRK, RT! and RTS instruc beginning of each Phase One clock pulse for as many cycles tions use the stack and Stack Pointer. a are required to complete the instruction. Each data transfer which takes place between the registers is caused by The stack can be envisioned as a deck of cards which may decoding the contents of both the instruction register and be accessed only from the top. The address of a memory timing controi unit. 3-106

“Uhr WAAL ii), = Ol pce ‘FA ie, 6|ClCO —_ fe i CSM ===se fo oe

6501 One-Chip Microprocessor

3.1.8 Interrupt Logic For the RAM to retain data upon loss of Voc, Via must be sup-

. _— plied within operating range and RES must be driven low at Interrupt logic controls the sequencing of three interrupts; RES, least eight 02 clock pulses before Vcc falls out of operating NMiand IRG. Ris generated by any one of eight conditions: range, RES must then be held low while Voc is out of operat- ‘2Counter Overtiows, 2 Positive Edge Detects, 2 Negative | Edge ing range and until at least eight $2 clock cycles after Voc is Detects, and 2 Serial Port Conditions. again within operating range and the internal 2 oscillator is stabilized. Va must remain within Vcc operating range during 3.2 NEW INSTRUCTIONS normal operation. When Voc is out of operating range, Van ms e must remain within the Vaq retention range in order to retain In addition to the standard R6502 instruction set, four new bit 4 manipulation instructions have been added to the R501. The data. Figure 3.2 shows typical waveforms added instructions and their format are explained in the follow- —— ing paragraphs. Refer to Appendix A for the Op Code RAM OPERATING MODE RAM RETENTION MODE mnemonic addressing matrix for these added instructions. The i} | | four added instructions do not impact the CPU processor status wae SF ee ee eel register. oJ = a 3.2.1 Set Memory Bit SMB m, Addr. ° 2. jory ) - i Le This instruction sets to “1” one of the 8-bit data field specified lo jo | bm by the zero page address (memory or VO port). The first byte by of the instruction specifies the SMB operation and one of eight 4) INITIAL APPLICATION OF Vcc AND You bits to be set. The second byte of the instruction designates Fe eu NoeY Power address (0-255) of the byte to be operated upon. “4 >892 CLOCK PULSES AFTER OSCILLATOR STABILIZATION. 3 >ag2 cLocK PuLses. 3.2.2 Reset Memory Bit (RMB m, Addr.) This instruction is the same operation and format as SMB Figure 3-2. Data Retention Timing instruction except a reset to “0” of the bit results. 3.2.3 Branch On Bit Set Relative (BBS m, Addr, 3.5 CLOCK OSCILLATOR DEST) ‘The R6501 has been configured for a crystal oscillator, a count- ‘This instruction tests one of eight bits designated by a 3-bit down network, and for Master Mode Operation immediate field within the first byte of the instruction. The ‘reference frequency can be generated with the on-chip oscil second byte is used to designate the address of the byte to be lator using either an external crystal or an external oscillator. tested within the zero page address range (memory or V/O The oscillator reference frequency passes through an internal ports). The third byte of the instruction is used to specify the countdown network to obtain the internal operating frequency. &-bit relative address to which the instruction branches if the ‘The on-chip oscillator is designed for a parallel resonant crys- bittestedis a "1". {f the bit tested is not set, the next sequential tal connected between XTLI and XTLO pins. The equivalent instruction is executed. oscillator circuit is shown in Figure 3-3a. A parallel resonant crystal is specified by its load capacitance 324 re pagal Reset Relative (BBR m, ‘and series resonant resistance. For proper oscillator operation, + DEST) the load capacitance (C,), series resistance (R,) and the crys- This instruction is the same operation and format as the BBS tal resonant frequency (F) must meet the following two relations: instruction except that a branch takes place if the bit tested is (C+ 2-2 of C= 20 -270F aro 2x10 Ry = Remax = Far 33 READ-ONLY: MEMORY (ROM) where: F is in MHz; C and C, are in pF; R is in ohms. The R501 has no ROM and its Reset vector is at FFFC. To select a parallel resonant crystal for the oscillator first select the load capacitance from a crystal manufacturer's catalog. 3.4 RANDOM ACCESS MEMORY (RAM) Next, calculate Asma based on F and Cy. The selected crys- ‘The RAM consists of 192 bytes of read/write memory with an tal must have a Ress than the Plane assigned page zero address of 0040 through OOFF. The R6501 For example, if CL = 22 pF for a 4 MHz parallel resonant crys- provides a separate power pin (Var) which may be used for tal, then ‘standby power for 32 bytes located at 0040-0065F- In the event = _ = F ‘of the loss of Vcc power, the lowest 32 bytes of RAM data will © = (2x22) — 27 = 17 pF (use standard value of 18 PF) be retained if standby power is supplied to the Vaa pin. If the ‘The series resistance of the crystal must be less than RAM data retention is not required then Vaq must be con- - 210° - nected to Vec. During operation Va must be at the Vc level. Remar = Tx app 7 8 ohms 3108

a R6501 One-Chip Microprocessor OE Internal timing can also be controlled by driving the XTLI pin. simultaneous interrupts cause the TRO interrupt request to with an external frequency source. Figure 3-3b shows typical remain active until all interrupting conditions have been connections. If XTLO is left floating, the external source is serviced and cleared. divided by the internal countdown network. However, if XTLO is tied to Ves, the internal countdown network is bypassed \\ i information th causing the chip to operate at the frequency of the external Fhe tlre Fig epito: on n ae source. ‘of the Interrupt Flag Register may be examined at any time by reading at address: 0011. Edge detect IFR bits may be ces% mu Gleared by executing a MB instruction at address location 27F 0010. The MB X, (0010) instruction reads FF, modifies bit resot X to a0’, and writes the modified value at address location NOE-B¥4 0011. In this way IFR bits set to a "1" after the read cycle of 2-4 Me [_])XTAL reatia ‘a Read-Modity-Write instruction (such as RMB) are protected —DIVIDE-B¥2, from being cleared. A logic "1" is ignored when writing to edge detect IFR bits. Sctsw xTLo apr = Each IFR bit has a corresponding bit in the Interrupt Enable ‘A. CRYSTAL INPUT Register which can be set to a "1" by writing a “1” in the respective bit position at location 0012. Individual IER bits may be cleared by writing a °0" in the respective bit position, 24 ME xT tw cove, cr by RES. If set to a "1", an IRQ will be generated when the Res01A—DIVIDE-B¥2 corresponding IFR bit becomes true. The Interrupt Flag Reg- ned xm ister and Interrupt Enable Register bit assignments are shown in Figure 3-5 and the functions of each bit are explained in Table 3-1. 1:2 Miz om XTL ty < 2MHE 6501 —DIVIDE-B¥1 RGS01A—DIVIDE-B¥1 | XTLO } Vss = | mcr sccm OO) | GET] == nek Figure 3-3. Clock Oscillator Input Options | Sou Mose See vimee $— * rea Canraton | [ | Sieaese us Mode Select, 11 te wt ews, \\ 0 — dinar nee | 01 Anyrmetie Pulse Ganerton | Sri

3.6 MODE CONTROL REGISTER (MCR) costinen Rewramnntie iver

The Mode Control Register contains control bits for the mul- roto 1h'sale tifunction VO ports and mode select bits for Counter A and (= TH State High impedance Mode) Counter B. Its setting, along with the setting of the Serial Sat clr Communications Control Register (SCCR), determines the atone basic configuration of the R501 in any application. Initial- oT thawiene izing this register is one of the first actions of any software program. The Mode contro! Register bit assignment is shown Figure 3-4. Mode Control Register in Figure 3-4, ‘The use of Counter A Mode Select is shown in Section 6.1.

3.7 INTERRUPT FLAG REGISTER (IFR)

AND INTERRUPT ENABLE ‘The use of Counter B Mode Select is shown in Section 6.2. REGISTER (IER) The use of Port B Latch Enable is shown in Section 44 An IRG interrupt request can be initiated by any or all of eight possible sources. These sources are all capable of being The use of Port D in Tri-State Enable is shown in Section 4.6. ‘enabled or disabled by the use of the appropriate interrupt enabled bits in the Interrupt Enable Register (IER). Multiple The use of Bus Mode Select is shown in Section 45 and 46. 3109

R6501 One-Chip Microprocessor ee ‘The Carry Bit may be set or cleared under program control Bonne by use of the Set Carry (SEC) or Ciear Carry (CLC) instruc- eR tion, respectively. Other operations which affect the Carry Bit TTT TTT tf are ADC, ASL, CMP, CPX, CPY, LSR, PLP, ROL, ROR, ATI, Cr TEs TdT TT Jaen woe ; rR PAO Positive age Detect, PAI Positive ee Edge Detect waeste CELE ETI PAS Negative Cage Owtect, ensayo Count & Ceartow Fg = const outa 8 3: Siryeuw “Undertow Flag. SO) Receiver 1s twonen Fog 2 Anam Ren xan snrennurr essere «@ 1: Ro ret sid i rou ent | Figure 3-5. Interrupt Enable and Flag Registers ccamas move 101)

3.8 PROCESSOR STATUS REGISTER 0: Seanmose”

The &-bit Processor Status Register, shown in Figure 3-6, orean consano contains seven status flags. Some of these flags are controlled nova Command by the user program; others may be controlled both by the ovenrcow 01) user's program and the CPU. The R6502 instruction set con- o tains a number of conditional branch instructions which are 05 Gramay Geer designed to allow testing of these flags. Each of the eight $$ eoarvem processor status flags is described in the following sections. a 1 eon Ve Setar mas

3.8.1 Carry Bit (C)

The Carry Bit (C) can be considered as the ninth bit of an arithmetic operation. It is set to logic 1 if a camy from the eighth bit has occurred or cleared to logic 0 if no carry Figure 3-6. Processor Status Register occurred as the result of arithmetic operations. Table 3-1. Interrupt Flag Register Bit Codes FRO: PAO Positive Edge Detect Flag—Set to a “1” when a posive going edge is detected on PAO ‘Cleared by RMB © (0010) instruction or by RES. IFR 1: PAI Positive Edge Detect Flag—Set to a 1 when a postive going edge is detected on PAI. Cleared by MB 1 (0010) instruction or by RES. IFR 2: PA2 Negative Edge Detect Flag—Set to a 1 when a negative going edge is detected on PA2. | ‘Cleared by RMB 2 (0010) instruction or by RES. FR 8: | PAS Negative Edge Detect Flag—Set to 1 when a negative going edge is detected on PAS. Cleared by FMB 3 (0010) instruction or by RES. FR 4: Counter A Undertlow Flag—Set to a 1 when Counter A underflow occurs. Cleared by reading | the Lower Counter A at location 0018, by writing to address location 001A. or by RES. IFRS: Counter Undertow Flag Soto a1 when Counter B undrow occu, Clare by reading the Lower Counter B at location 001C. by writing to address location 001E, or by RE! FRE: Receiver Interrupt Flag—Set to a 1 when any of the Serial Communication Status Register bits ough 3 is st 8 1.Cieared when the Racaiver Sits ie (SCBR 0-5) are caared or by FR 7: ‘Transmitter Interrupt Flag—Set to a 1 when SCSR 6is set to a 1 while SCSR Sis a 0 or SCS 7s set to a 1. Cleared when the Transmitter Status bits (SCSR 6 & 7) are cleared or by RES. j 3-110

R6501 One-Chip Microprocessor a 3.8.2 Zero Bit (2) 3.8.5 Break Bit (B) The Zero Bit (Z) is set to logic 1 by the CPU during any data The Break Bit (B) is used to determine the condition which movement or calculation which sets all 8 bits of the result to caused the IRG service routine to be entered. If the IRQ service Zero. This bit is cleared to logic 0 when the resultant 8 bits routine was entered because the CPU executed a BRK com- of a data movement or calculation operation are not all zero. mand, the Break Bit will be set to logic 1. If the IRQ routine was ‘The F6500 instruction set contains no instruction to specifi- entered as the result of an IRO signal being generated, the B bit cally set or clear the Zero Bit. The Zero Bit is, however, will be cleared to logic 0. There are no instructions which can affected by the following instructions; ADC, AND, ASL, BIT, set or clear this bit. ‘CMP, CPX, CPY, DEC, DEX, DEY, EOR, INC, INX, INY, LDA, LDX, LDY, LSR, ORA, PLA, PLP, ROL, ROR, RTI, 3.8.6 Overflow Bit (V) SBC, TAX, TAY, TXA, TSX, and TVA. ‘The Overflow Bit (V) is used to indicate that the result of a signed, binary addition, or subtraction, operation is a value

3.8.3 Interrupt Disable Bit (}) that cannot be contained in seven bits (~128 < n = 127)

The Interrupt Disable Bit (|) is used to control the servicing This indicator only has meaning when signed arithmetic (sign of an interrupt request (RQ). If the | Bit is reset to logic 0, ‘and seven magnitude bits) is performed. When the ADC or the [FIG signal will be serviced. Ifthe bit is set 10 logic 1, the SBC instruction is performed, the Overflow Bit is set to logic IRQ signal will be ignored. The CPU will set the Interrupt 1 if the polarity of the sign bit (bit 7) is changed because the Disable Bit to logic 1 if a RESET (RES), IRQ, or Non-Mask- result exceeds +127 or -128; otherwise the bit is cleared able Interrupt (NMi) signal is detected. to logic 0. The V bit may also be cleared by the programmer using a Clear Overflow (CLV) instruction. The | bit is cleared by the Clear interrupt Mask Instruction (CLI) and is set by the Set Interrupt Mask Instruction (SEI). ‘The Overflow Bit may also be used with the BIT instruction. This bit is set by the BRK Instruction. The Return from inter- ‘The BIT instruction—which may be used to sample interface rupt (RTI) and Pull Processor Status (PLP) instructions will devices—allows the overflow flag to reflect the condition of also affect the | bit. bit 6 in the sampled field. During a BIT instruction the Over- flow Bit is set equal to the content of the bit 6 on the data 3.8.4 Decimal Mode Bit (D) tested with BIT instruction. When used in this mode, the The Decimal Mode Bit (0) is used to control the arithmetic overflow has nothing to do with signed arthmeti, but is just mode of the CPU. When this bit is set to logic 1, the adder ‘another sense bit forthe microprocessor. instructions affecting operates as a decimal adder. When this bit cleared to logic 0, the V flag are ADC, BIT, CLV, PLP, RT! and SBC. the adder operates as a staight binary adder. The adder mode is controlled only by the programmer. The Set Decimal 3.8.7 Negative Bit (N) ‘Mode (SED) instruction will set the D bit; the Clear Decimal The Negative Bit (N) is used to indicate that the sign bit Mode (CLD) instruction clears it. The PLP and RTI instruc- (it 7) in the resulting value of a data movement or data arith- tions also affect the Decimal Mode Bit. metic operation is set to logic 1. If the sign bit is set to logic 1, the resulting value of the data movement or arithmetic ‘operation is negative; if the sign bit is cleared, the result of CAUTION the data movement or arithmetic operation is positive. There The Decimal Mode Bit will either set or clear in an erp intrucone Set sot oF cls tne ee noe Ine ictable manner upon power application. This bit fegative Bit represents only the status of a result. The unered instructions that effect the state of the Negative Bit are: ADC, ‘must be initialized to the desired state by the user pro- AND, ASL, BIT, CMP, CPX, CPY, DEC, DEX, DEY, EOR, gram oF erroneous results may occur. ING, INX, INY, LDA, LDX, LDY, LSR, ORA, PLA, PLP, ROL, ROR, RTI, SBC, TAX, TAY, TSX, TXA, and TYA. ant

Resi One Chiip Microprocessor SECTION 4 PARALLEL INPUT/OUTPUT PORTS & BUS MODES The devices have 32 I/O lines grouped into four 8-bit ports Port D may only be all inputs or all outputs. All inputs is (PA, PB, PC, and PD). Ports A through C may be used either selected by setting bit 5 of the Mode Control Register (MCRS) {or input or output individually or in groups of any combination. toa'0" Port D may be used as alll inputs or all outputs. The status of the input lines can be interrogated at any time ‘Multifunction VO's such as Port A and Port C are protected by reading the VO port addresses. Note that this will return ‘from normal port I/O instructions when they are programmed the actual status of the input lines, not the data written into to perform a multiplexed function. the /O port registers. Internal pull-up resistors (FET's with an impedance range of Flead/Modty/Write instructions can be used to modify the / ese Kann) ae provided on all por pine except operation of PA, PB, PC, & PD. During the Read cycle of a | PotD or port Pi Rlead/Modify/Write instruction the Port VO register is read. | For all other read instructions the port input lines are read. Read/Modity/Write instructions are: ASL, DEC, INC, LSR, ‘The direction of the 32 VO lines is controlled by four 8-bit port RMB, ROL, ROR, and SMB. registers located in page zero. This arrangement provides quick programming access using simple two-byte zeropage address. instructions. There are no direction registers associated with 4.2 OUTPUTS the /O ports, thus simplifying VO handling. The VO addresses Outputs for Ports A thru D are controlled by writing the are shown in Table 4-1. Appendix E.4 shows the I/O Port Timing. desired VO line output states into the corresponding I/O port register bit positions. A logic 1 will force a high (>2.4V) output while a logic 0 will force a low (<0.4V) output. Table 4-1. I/O Port Addresses Port D all outputs is selected by setting MCRS to a “1”. ; j 3000 4.3 Port A (PA) B 0001 Port A can be programmed via the Mode Control Register c e002 (MCR) and the Serial Communications Control Register ° 0003 (SCCR) as a standard parallel 8-bit, bit independent, /O port or as serial channel VO lines, counter VO lines, or an input data strobe for the Port B input latch option. Table 4-2 tab- ulates the control and usage of Port A.

4.1 INPUTS In addition to their normal VO functions, PAO and PA1 can

Inputs for Ports A, B, and C are enabled by loading logic 1 detect positive going edges and PA2 and PA3 can detect into all VO port register bit positions that are to correspond negative going edges. A proper transition on these pins will to VO input lines. A low (<0.8V) input signal will cause a logic set a corresponding status bit in the IFR and generate an 0 to be read when a read instruction is issued to the port interrupt request if the respective Interrupt Enable Bit is set. register. A high (>2.0V) input will cause a logic 1 to be read. The maximum rate at which an edge can be detected is one- ‘An RES signal forces all /O port registers to logic 1 thus half the 82 clock rate. Edge detection timing is shown in Ap- initially treating all /O lines as inputs. pendix E.3. 3112

Oe ____ R6501 One-Chip Microprocessor Table 4-2. Port A Control and Usage cr a PORT B INPUT (1) LATCH STROBE ‘SIGNAL wae PA2 a IMCRO = 0 IMCRO = ‘SCCR7 = 0 IMCR1 = 0 IMCRt = 0 SCCRE = 0 ISCCR7 = 0 SCCR7 = 0 MCRI = 1 |RCVR S/R MODE = 0 |RCVR SIR MODE = 0 (4) (5) 4) Sena Sout NAME TYPE NAME TYPE a [aur ‘SCCRS = 1 @ wae iad [ ve sana xox [out nemesis [rer MCR3 = 0 MCR3 = 0 MCR3 = 1 MCR2 = 0 MCR2 = 1 MCR2 = X seu | wae] a a [es [ene [omer | one | neuron | [Tr ronan ar ‘SERIAL VO (2) POSITIVE EDGE DETECT XMTR OUTPUT (3) NEGATIVE EDGE DETECT (4) ROVR S/R MODE = 1 WHEN Scone sooRs. sche ee | |" a fsa rar flo so | sae Tee | aren a A ieee + SCCRT-SCCRESCORS ‘SERIAL VO +SCCRT-SCCRESCCR4 a em [eae [vee [tae [et nero 3-113,

R6501 One-Chip Microprocessor eee

4.4 PORT B (PB) selected to operate in the Abbreviated Mode PDO-PD7 serves

jl as data register bits D0-D7. When Port D is selected to oper- Port B can be programmed as an &-bit, bitindependent I/O port ate in the Multiplexed ‘Mode data bits DO through D7 are time {thas a latched input capability which may be enabled or dis- muttiplexed with address bits Ad through Ati, respectively. abled via the Mode Control Register (MCR). Table 4-3 tabulates Refer to the Memory Maps (Appendix C) for Abbreviated and the control and usage of Port B. An Input Data Strobe signal Muttiplexed memory assignments. See Appendices E.3 must be provided thru PAO when Port B is programmed to be through 5 for Port D timing used with latched input option. Input data latch timing for Port B is shown in Appendix E.5

4.7 BUS MODES

Table 4-3. Port B Control & Usage Aspecial attribute of Port C and Port D is their capability tobe == strand ae Cowan tots tes |e paanen Men = 0 In the Full Address Mode, the separate address and data bus | Stanat_ are used in conjunction with PC6 and PC7, which automatically 78" | wane | toe _| provide A13 and A14. The remaining ports perform the normal io VO funetion. a | peo | Peo | vO | PBO | INPUT 30 Per PBI vo Pet INPUT In the VO Bus Mode all ports serve as /O. The address and data 3 bes eae 10 Pes Neur bus are still functional but without A13 and A14. Since the inter- nal RAM and registers are in the OOXX location, A1S can be Z| pe eee HS cee | Neue used for chip select and A0-A12 used for selecting 8K of exter- 25 | pes | pee | wo | PBS | INPUT nal memory. oe eee Inthe Abbreviated Bus Mode, the address and data lines can 1) Resistive Pul-Up, Active Buffer PultDown inthe fisted Bas Mode, biosererata eenenees and Port D are automatically transformed into an abbreviated address bus and control signals (Port C) and a bidirectional data bus (Port D). 64 Peripheral addresses can be selected.

45 PORT C (PC) In general usage, these 64 addresses would be distributed to

Port C can be programmed as an VO port, as part of the full several external /O devices such as R6522 and R6520, etc., address bus, and, in conjunction with Port D, as an abbreviated each of which may contain more than one unique address. bus, or as a multiplexed bus. When operating in the Full Address Mode PC6 and PC7 serve as A13 and A14 with In the Multiplexed Bus Mode, the operation is similar to the PCO-PCS operating as normal 1/0 pins. When used in the Abbreviated Mode except that a full 16K of external addresses abbreviated or multiplexed bus modes, PCO-PC7 function as are provided. Port C provides the lower addresses and control AO-AS, A12, RW, A13, and EMS, respectively, as shown in signals. Port D multiplexes functions. During the first halt of the Table 4-4. EMS (External Memory Select) is asserted (low) cycle it contains the remaining necessary 8 address bits for whenever the internal processor accesses memory area 16K; during the second half of the cycle it contains a bidirec- between 0100and 3FFF. (See Memory Map, Appendix B). The tional data bus. The address bits appearing on Port D must be leading edge of EMS may be usedto strobe the eight address latched into an external holding register. The leading edge of lines multiplexed on Port D in the Multiplexed Bus Mode. See EMS which indicates that the bus function is active, may be ‘Appendices E.3 through ES for Port C timing, used for this purpose.

4.6 PORT D (PD) MORS must be a logic 1 inthe Abbreviated and Multiplexed

Port D can be programmed as an VO Port, an 8-bittr-state data bus, or as a muttiplexed bus. Mode selection for Port Dis made Figures 4-1a through 4-1d show the possible configurations of by the Mode Control Register (MCR). The Port D output drivers the four bus modes. Figure 4-2 shows a memory map of the can be selected as tri-state drivers by setting bit 5 of the MCR part as a function of the Bus Mode and further shows which 101 (one). Table 4-5 shows the necessary settings for the MCR adddresses are active or inactive on each of the three possi- to achieve the various modes for Port D. When Port D is ble buses. aig

R6501 One-Chip Microprocessor il a es Nien See Table 4-4. Port C Control & Usage Full Address ‘Abbreviated ‘Multiplexed Mode Mode Mode ‘MCR7 = 0 MCR6 = 0 Ln PCO PCO WO (1) PCO ed AO OUTPUT AO OUTPUT PCr Pci wo) PCI re} AL OUTPUT AL OUTPUT | PC2 pce WO) pce ie} AZ OUTPUT Ae OUTPUT | pes PC vo) PC3 vo a3 OUTPUT 43 OUTPUT | Pes Pos vO) PCs vo Aa ouTPUT Atz ourPuT PCs Pcs wow PCs vo RW oureut AW ouput PCE AIS ‘OUTPUT (2) PCS vO AIS OUTPUT ANZ. OUTPUT PCr ate OUTPUT (2) Per 10 Ems output ews output (i) Resistive Pull-Up, Active Buller Pul-Dawn (2) Active Butter Pull-Up and Pul-Down Table 4-5. Port D Control & Usage EI ‘Abbreviated Mode Multiplexed Mode MCR? = 0 wcRT = 0 WOR? = 1 WORT = 1 MCR6 = X MCR = X MCRE = 0 MCRE = 1 MCRS = 0 MCRS = 1 MCRS = 1 MCRS = 1 POO POO INPUT PDO OUTPUT DATAQ vo wm OUTPUT DATAO vo Por por input | Por | output | ata | vO as | oureuT —OATAL Wo PO2 PO2 INPUT PO2 OUTPUT DATA2 re} AB OUTPUT DATA2 vo POS POS INPUT POs OUTPUT DATAS | uO aT OUTPUT —DATAS vo PDs pos input | pos | ouTpuT | DAM | 10 as | output cama | 0 POS: POS: INPUT POS: OUTPUT DATAS: ie} As OUTPUT DATAS: vo POS pos put | pos | output | vats | vo | ato | ouTPUT cams | v0 (1) Tri-State Buffer is in High Impedance Mode (2) Tri-State Butter is in Active Mode {@) Ti-State Butters in Active Mode only during the phase 2 portion of a Write Cycle 3115

R6501 One-Chip Microprocessor ia => a a “ am “ Ka ve ESOT Kom) rome e501 Keane» rome | = =) ‘A. FULL ADORESS MODE B. NORMAL BUS MODE ~ =r te te) rome : KD me “ C= Om [aman y| (SE! meso Bp | aa, ay — SEahe | = — — a ——) | | C. ABBREVIATED BUS MODE D. MULTIPLEXED BUS MODE — | Figure 4-1. 6501 Bus Mode Configurations

R6501 One-Chip Microprocessor ABBREVIATED MULTIPLEXED NORMAL FULL ADDRESS | MODE MODE MODE WoDE FFF . Ty FFFF me] Boe | Bey | AS mt ate nere' OSS P< | 7 N Tere ' \\ - oer \\X] \\\\ FFF

3000 AN EMS VALID

20008 (WHEN ABBROR | FFF INN MUX MODE 1000, SELECTED) x00 oy 100 OOFF j OFF ‘RAM AND | INTERNAL REGISTERS 0010 oo10 | oF N N 000F N N 0003, Pp 0003 | Vo PORTS | a2 3 222 222 222 “te fii 2:2 823 #33 26 $88 G88 § 66 Be 252 252 28 2 2&5 \\] active | BUT REDUNDANT MAY BE ACTIVE ga (OPTION DEPENDENT) E] INACTIVE Figure 4-2. R6501 Memory Map

R6501 One-Chip Microprocessor ih ee seats SECTION 5 SERIAL INPUT/OUTPUT CHANNEL The device provides a full duplex Serial /O channel with pro- samen we wren ry grammable bit rates and operating modes. The serial 1/0 a functions are controlled by the Serial Communication Control — Register (SCCR). The SCCR bit assignment is shown in (aloe) Figure 5-1. The serial bit rate is determined by Counter A for all modes except the Receiver Shift Register (RCVR S/R) | mode for which an extemal shift clock must be provided. The re | maximum data rate using the internal clock is 62.5K bits per ‘second (at $2 = 1 MHZ). The transmitter (MTR) and receiver (RCVA) can be independently programmed to operate in ssmentonon woe wm MY different modes and can be independently enabled or Pd disabled. PT+TTsTe Tet Te less a 01s | | socr | 0~0dd Parity | | | Even Parity | 0 Party Ofsabie serrmeren woo vars | 1 Party Enable Se — ) | | 9 o~s.tercnar | 0 1~7Bita/Char ermcoren cook oe 1 0~6 BiterChar r [ $ sceemene Toni |

0 OXMTR & RCVR ASYN Mode 1

xk sm; nevn Asya Figure 5-2. SIO Data Modes ¢ Reve era In the S/R mode, eight data bits are always shifted out. Bits! 0 XMTR Disable character and parity control bits are ignored. The serial data

1 XMTR Enable is shifted out via the SO output (PA6) and the shift clock is

available at the CA (PAA) pin. When the transmitter under- Figure 5-1. Serial Communication Control Register runs in the S/R mode the SO output and shift clock are held in a high state. Except for the Receiver Shift Register Mode (RCVR S/R), all The XMTR Interrupt Flag bit (IFR7) is controlled by Serial XMTR and RGVA bit rates will occur at one sixteenth of the Communication Status Register bits SCSR5, SCSR6 and Counter A interval timer rate. Counter A is forced into an SCSR7. interval timer mode whenever the serial I/O is enabled in a __ mode requiring an intemal clock. IFR7 = SCSR6 (SCSRS + SCSR7) Whenever Counter A is required as a timing source it must be loaded with the hexadecimal code that selects the data 5.2 RECEIVER OPERATION (RCVR) rate for the serial /O Port. Refer to Counter A (paragraph 6.1) The receiver and its selected control and status functions are for a table of hexadecimal values to represent the desired enabled when SCCR-6 is set to a "1." In the ASYN mode, data rate. data format must have a start bit, the appropriate number of dala bits, a parity bit (f enabled), and one stop bit. Refer to paragraph 5.1 for a diagram of bit allocations. The receiver

5.1 TRANSMITTER OPERATION (XTMR) bit period is divided into 8 sub-intervals for internal synchro-

The XTMR operation and the transmitter related controV nization. The receiver bit stream is synchronized by the start status functions are enabled by bit 7 of the Serial Commu- bit anda strobe signal is generated at the approximate center nications Control Register (SCCR). The transmitter, when in ‘of each incoming bit. Refer to Figure 5-3 for ASYN Receive the Asynchronous (ASYN) mode, automatically adds a start Data Timing. The character assembly process does not start bit, one or two stop bits, and, when enabled, a parity bit to if the start bit signal is less than one-half the bit ime after a the transmitted data. A word of transmitted data (in asyn- low level is detected on the Receive Data Input. Framing chronous parity mode) can have 5, 6, 7, oF 8 bits of data. ‘error, over-run, and parity error conditions or a RCVR Data The nine data modes are shown in Figure 5-2. When parity is Register Full will set the appropriate status bits. Any of the disabled, the 5, 6, 7 oF 8 bits of data are terminated with two above conditions will cause an interrupt Request if the stop bits. Receiver Interrupt Enable bit is set to logic 1. 3118

R6501 One-Chip Microprocessor SSE received data has a parity error. This bit is cleared or oe et by reading the Receiver Data Register or by RES. heal our ee ae ‘SCSR 3: Framing Error—Set to a logic 1 when the received data contains a zero bit after the last data or parity Seyret bit in the stop bit slot. Cleared by reading the Goa UF LE PLE Receiver Data Register or by RES (ASYN Mode only). SCSA 4: Wake-Up—Set to a logic 1 by writing a “1” in bit z a 4 of address: 0016. The Wake-Up bit is cleared by Sete eo ove sine ES or when the receiver detects a string of ten consecutive 1’s. When the Wake-Up bit is set Figure 5-3. ASYN Receive Data Timing SCSRO through SCSR3 are wee Inthe S/R mode, an external shift clock must be provided at SCSR 5: End of Transmission—Set to a logic 1 by writing CA (PAA) pin along with 8 bits of serial data (LSB first) at the "1" bit position 5 of ae te tte Et SI input (PA7). The maximum data rate using an external Of Transmission bit Is cleared by RES or upon shift clock is one-eighth the internal clock rate. Refer to writing a new data word into the Transmitter Data Figure 5-4 for SIR Mode Timing. Register. When the End-of-Transmission bit is true the Transmitter Ragister Empty bit is disabled untit ee ee es ae ee a Transmiter Under-Run occurs, enemas One ‘SCSR 6: Transmitter Data Register Empty—Set to a logic Fn Me oe a ee Oe pp 1 when the contents of the Transmitter Data Reg- cock ister are transterred to the Transmitter Shift Reg- oe as er ere en ene, tn inuahons tra Oot oa Transmit Data Register. This bit is initialized to a a logic 1 by RES. ‘SCSR 7: Transmitter Under-Run—Set to a logic 1 when the last data bit is transmitted if the transmitter is in a + Seria input Data Shad a SJR Mode or when the last stop bit is transmitted "Serial Output Data Makes Transition if the XMTR is in the ASYN Mode while the Trans- rmitter Data Register Empty Bit is set. Cleared by Figure 5-4. S/R Mode Timing Pikshee rai into the Transmitter Shift A RCVR interrupt (IFR6) is generated whenever any of SeShOS a tuo a Oc ce ed

5.3 SERIAL COMMUNICATION STATUS ncvn oats

REGISTER (SCSR) Reg Fall The Serial Communication Status Register (SCSA) holds FEM Over on information on various cornmunication error conditions, status Paster Srver of the transmitter and recetver data registers, a transmitter Frame Error end-of-transmission condition, and a receiver idle line con- | dition (Wake-Up Feature). The SCSR bit assignment is shown wuete | in Figure 5-5. Bit assignments and functions of the SCSR are End of Tranamision { as follows: XT bets Rog Empty SCSRO: Receiver Data Register Full—Set to a logic 1 when 2a Under Run ‘a character is transferred from the Receiver Shift Register to the Receiver Data Register. This bit is Figure 5-5. SCSR Bit Allocations cleared by reading the Recewver Data Register, or 7 by RES and is disabled if SCCR 6 = 0. The SCSR 5.4 WAKE-UP FEATURE O bit will not be set to a logic 1 if the received data In a multi-istributed microprocessor or microcomputer appli- contains an error condition; instead, a corre- ations, a destination address is usually included at the begin- sponding error bit will be set to a logic 1 ning of the message. The Wake-Up Feature allows non-selected CPU's to ignore the remainder of the message until the begin- SCSR 1: Over-Run Error—Set to a logic 1 when a new char- ning of the next message by setting the Wake-Up bit. As long acter is transferred from the Receiver Shift Reg- as the Wake-Up flag is true, the Receiver Data Register Full Flag ister with the last character stil in the Receiver remains false. The Wake-Up bit is automatically cleared when Data Register. This bit is cleared by reading the the receiver detects a string of eleven consecutive 1's which indi- Receiver Data Register or by RES. cates an idle transmit line. When the next byte is received, the Receiver Data Register Full Flag signals the CPU to wake-up ‘SCSR 2: Parity Error—Set to logic 1 when the RCVR is in and read the received data. the ASYN Mode, Parity Enable bit is set, and the 3119

R6501 One-Chip Microprocessor ep SECTION 6 COUNTER/TIMERS The device contains two 16-bit counters (Counter A and Upper Latch A before the contents of the 16-bit latch are Counter 8) and three 16-bit latches associated with the transferred to Counter A. Counter A is set to the latch value counters. Counter A has one 16-bit latch and Counter B has: whenever Counter A underflows. When Counter A decre- two 16-bit latches, Each counter can be independently pro- ‘ments from 0000 the next counter vaiue will be the latch grammed to operate in one of four modes: value—not FFFF—and the Counter A Undertlow Flag (IFR: 4) will be set to "1". This bit may be cleared by reading the Counter A Counter B Lower Counter A at location 0018, by writing to address lo- Pulse width ‘¢ Retriggerable Interval Counter Cation 001A, or by FES. measurement ¢ Asymmetrical Pulse Counter A operates in any of four modes. These modes are 1» Pulse Generation Generation selected by the Counter A Mode Control bits in the Control © Interval Timer «¢ Interval Timer Register Event Counter «Event Counter ( gerummccemammcemecenes (SUR [| by the Mode Control Register. All counting begins at the initialization value and decrements. When modes are selected ° Interval Timer ' requiring a counter inputoutput line, PAS is automatically 1 |__-Pulse Generation selected for Counter A and PAS is automatically selected for ° | Event Counter Counter B (see Table 4.2). 1 Puise Width Measurement The Interval Timer, Pulse Generation, and Pulse Width Mea- 6.1 COUNTER A surement Modes are ¢2 clock counter modes. The Event Counter A consists of a 16-bit counter and a 16-bit latch Counter Mode counts the occurrences of an external event organized as follows: Lower Counter A (LCA), Upper Counter ‘on the CNTR line. ‘A (UCA), Lower Latch A (LLA), and Upper Latch A (ULA). The counter contains the count of either #2 clock pulses or The Counter is set to the interval Timer Mode (00) when a external events, depending on the counter mode selected. RES signal is generated. The contents of Counter A may be read any time by exe- ccuting a read at location 0019 for the Upper Counter A and 6.1.1 Interval Timer ‘at location 001A or location 0018 for the Lower Counter A. In the Interval Timer mode the Counter is initialized to the A read at location 0018 also clears the Counter A Underfiow Latch value by either of two conditions: Flag (IFR4). 1. When the Counter is decremented from 0000, the next The 16-bit latch contains the counter initialization value and Counter value is the Latch value (not FFF). can be loaded at any time by executing a write to the Upper Latch A at location 0019 and the Lower Latch A at location 2. When a write operation is performed to the Load Upper 0018. In either case, the contents of the accumulator are Latch and Transfer Latch to Counter address 001A, copied into the applicable latch register. the Counter is loaded with the Latch value. Note that the contents of the Accumulator are loaded into the Counter A can be started at any time by writing to address: Upper Latch before the Latch value is transferred to 001A. The contents of the accumulator will be copied into the the Counter. The Counter value is decremented by one count at the 02 emMmnmnAnn. clock rate. The 16-bit Counter can hold trom 1 to 65535 1 counts. The Counter Timer capacity is therefore 11s to 65.535 Conren noerion ms at the 1 MHz 92 clock rate or 0.5 ys to 32.767 ms al the cow 2 MHz 2 clock rate. Time intervais greater than the max: i imum Counter value can be easily measured by counting a IRQ interrupt requests in the counter IRQ interrupt routine. ’ | Sauron When Counter A decrements from 0000, the Counter A connects Underfiow (IFR4) is sat to logic 1. if the Counter A Interrupt Enable Bit (IER4) is also set, an IRQ interrupt request will be “ generated. The Counter A Underfiow bit in the Interrupt Flag — Register can be examined in the IRQ interrupt routine to Figure 6-1. Interval Timer Timing Diagram determine tat the 1G was goneraied by the Counter A 3-120

R6501 One-Chip Microprocessor ae While the timer is operating in the Interval Timer Mode, PA4 The Counter A underflow fag will be set only when the count operates as a PA VO bit. in the timer reaches zero. Upon reaching zero the timer will be loaded with the latch value and continue counting down ‘A timing diagram of the Interval Timer Mode is shown in as long as the CA pin is held low. Alter the counter is stopped Figure 6-1. by a high level on CA, the count will hold as long as CA remains high. Any further low levels on CA will again cause 6.1.2 Pulse Generation Mode the counter to count down from its present value. The state In the Pulse Generation mode, the CA line operates as a of the CA line can be determined by testing the state of PAS. Counter Output. The line toggles from tow to high or from high to low whenever a Counter A Undertiow occurs or a ‘A timing diagram for the Pulse Width Measurement Mode is write is performed to address 001A. shown in Figure 6.3. The normal output waveform is a symmetrical square-wave. The CA output is initialized high when entering the mode and transitions low when writing to 001A. a Tron ‘Asymmetric waveforms can be generated it the value of the aw ts latch is changed after each counter underflow. | cowry ws | oe ‘A one-shot waveform can be generated by changing trom “ Pulse Generation to Interval Timer mode after only one ‘occurrence of the output toggle condition. 6-3. Pulse Width Measurement

6.1.3 Event Counter Mode

In this mode the CA is used as an Event Input line, and the Counter will decrement with each rising edge detected on 6.1.5 Serial /O Data Rate Generation this line, The maximum rate at which this edge can be Counter A also provides clock timing for the Serial VO which detected is one-half the 2 clock rate. establishes the data rate for the Serial /O port. When the Serial VO is enabled, Counter A is forced to operate at the The Counter can count up to 65,535 occurrences before internal clock rate. Counter A is not required for the RCVR underflowing. As in the other modes, the Counter A Under- ‘S/R mode. The Counter I/O (PA4) may also be required to flow bit (IER4) is set to logic 1 if the underflow occurs. ‘support the Serial VO (see Table 4-2). Figure 6.2 is a timing diagram of the Event Counter Mode. Table 6-1 identifies the values to be loaded in Counter A for selecting standard data rates with a $2 clock rate of 1 MHz and 2 MHz. Although Table 6-1 identifies only the more eT LOLS Lye rir common data rates, any data rate from 1 to 62.5K bps can romp be selected by using the formula: oon. Ta [ en __ fan fe tee N= age N= decimal value to be loaded into Counter A using its hexadecimal equivalent. Figure 6-2. Event Counter Mode fe = the clock frequency (1 MHz or 2 MHz) bps = the desired data rate.

6.1.4 Pulse Width Measurement Mode NOTE

‘This mode allows the accurate measurement of a low pulse In Table 6-1 you will notice that the standard data rate duration on the CA fine. The Counter decrements by one and the actual data rate may be slightly different. count at the (2 clock rate as long as the CA line is held in Transmitter and receiver errors of 1.5% or less are ‘he low state. The Counter is stopped when CA is in the high acceptable, A revised clock rate is included in Table state. 6-1 for those baud rates which fall outside this limit. 3-121

—_— R6501 One-Chip Microprocessor ih ah Anbshd shebecl ‘Table 6-1. Counter A Values for Baud Rate Selection 6.2.1 Retriggerable Interval Timer Mode CLOCK RATE! When operating in the Retriggerable Interval Timer mode, (NEEDED ‘Counter Bis initialized to the latch value by writing to address TO GET 001E, by a Counter B underflow, or whenever a positive edge s Dec! sranoano ‘occurs on the CB pin (PAS). The Counter B interrupt flag will BAUD RATE be set if the counter underfiows before a positive edge occurs | tutis 2 wht] “1 mite 2 it [1 te 2 ‘on the CB line. Figure 6-4 illustrates the operation. 50 O4E1 09C3 50.00 50.00] 1.0000 2.0000} 75 | 0340 0682] 75.03 74.99/1.0000 2.0000] Latch 110 0237 = (O46F 110.04 110.04/1.0000 2.0000} Von | 150 O1A0 0340 | 149.88 150.06/1.0000 2.0000; 300 OCF O1A0| 30048 299.76) 1.0000 2.0000) Count Value 600, 0067 O0CF} 600.96 600.961.0000 2.0000) 0000 1200 | 0033 0067 | 1201.92 1201.92|1.0000 2.0000 ete ae eee | 3600 0010 0021 | 3676.47 3676.47)0.9792 1.9584) / | 4800 | 000¢ 0019 4807.69 4807.69]1.0000 2.0000] Scions ep Raat by Sofware 7200 0008 0010 | 6944.44 7362.94/1.0368 1.9584} 9600 | 0006 000C | 8928.57 9615.38] 1.0752 2.0000] eae | 6.2 COUNTER B Figure 6-4. Counter B Retriggerable Interval Timer Mode ‘Counter B consists of a 16-bit counter and two 16-bit latches organized as follows: Lower Counter B (LOB), Upper Counter 6.2.2 Asymmetrical Pulse Generation Mode B (UCB), Lower Latch B (LLB), Upper Latch B (ULB), Lower Counter B has a special Asymmetrical Pulse Generation Latch C (LLC), and Upper Latch C (ULC). Latch C is used Mode wheraby a pulse train with programmable pulse width ‘only in the asymmetrical pulse generation mode. The counter and period can be generated without the processor interven- contains the count of either 62 clock pulses or external tion once the latch values are initialized. ‘events depending on the counter mode selected. The con- tents of Counter B may be read any time by executing a Read In this mode, the 16-bit Latch B is initialized with a value ‘at location 001D for the Upper Counter B and at location ‘which corresponds to the duration between pulses (referred ‘001E oF 001C for the Lower Counter B. A Rlead at location to as D in the following descriptions). The 16-bit Latch C is 001C also clears the Counter B Underflow Flag. initialized with a value corresponding to the desired pulse ‘width (referred to as P in the following descriptions). The Latch 8 contains the counter initialization value and can be initialization sequence for Latch B and C and the starting of loaded at any time by executing a Write to the Upper Latch a counting sequence are as follows: B at location 0010 and the Lower Latch B at location 001C. Ineach case, the contents of the accumulator are copied into 1. The lower 8 bits of P are loaded into LLB by writing to the applicable latch register. address 001C; the upper 8 bits of P are loaded into ULB and the full 16 bits are transferred to Latch C by Counter B can be initialized at any time by writing to address: writing to address location 001D. At this point both OO1E. The contents of the accumulator is copied into the Latch B and Latch C contain the value of P. Upper Latch B before the value in the 16-bit Latch Bis trans- ferred to Counter B. Counter B will also be set to the laich 2. The lower 8 bits of D are loaded into LLB by writing to, value and the Counter B Underflow Flag bit (IFRS) will be set address 001C; the upper 8 bits of D are loaded into to a "1" whenever Counter B underflows by decrementing ULB by writing to address location 001E. Writing to from 0000. address location 001E also causes the contents of the 16-bit Latch B to be downloaded into the Counter B IFR 5 may be cleared by reading the Lower Counter 8 at ‘and the CB output to go low as shown in Figure 6-5. location 001C, by writing to address location OO1E, or by RES. 3. When Counter B undertiow occurs the contents of the Latch C are loaded into the Counter B and the CB out- ‘Counter B operates in the same manner as Counter A in the put toggles to a high level, staying high until another Interval Timer and Event Counter modes. The Pulse Width underflow occurs. Latch 8 is then down-loaded and the Measurement Mode is replaced by the Retriggerabie Interval CB output toggles to a low level repeating the whole Timer mode and the Pulse Generation mode is replaced by process. the Asymmetrical Pulse Generation Mode. Mode Contro! Register bits MCR2 and MCR3 select the four Counter B modes in a similar manner and coding as MCRO and MCR1 select the modes of Counter A. 3-122

reaches operating range and the internal oscillator has sta- ured as shown in Table 7-1. Figure 741. P Turn-On Timing nt nM and omnes ore registers will initialize in a random,

7.2 POWER-ON RESET

Clear or Set Decimal Mode
Set up Mode Controls as required

R6501 One-Chip Microprocessor we This appendix contains a summary of the Enhanced R6502 instruction set. For detailed information, consult the R6502 Microcomputer System Programming Manual, (Order No. 202). The four instructions notated with a * are added instructions to enhance the standard 6502 instruction set. A.1 INSTRUCTION SET IN ALPHABETIC SEQUENCE [Mnemonic [Description [| Mnemonic _| Description ‘ADC ‘Add Memory to Accumulator with Carry LDA ‘Load Accumulator with Memory ‘AND “AND” Memory with Accumulator LOX Load Index X with Memory ASL Shift Left One Bit (Memory or Accumulator) LOY Load Index Y with Memory LSR Shift One Bit Right (Memory or Accumulator) “BBR Branch on Bit Reset Relative “BBS Branch on Bit Set Relative NOP No Operation Bcc Branch on Carry Clear Bcs Branch on Carry Set son BEQ Branch on Result Zero ORA ‘OR” Memory with Accumulator BIT Test Bits in Memory with Accumulator BMI Branch on Result Minus PHA Push Accumulator on Stack BNE Branch on Result not Zero PHP Push Processor Status on Stack BPL Branch on Result Plus PLA Pull Accumulator from Stack BRK Force Break PLP Pull Processor Status from Stack BYC Branch on Overflow Clear BvS Branch on Overflow Set “AME Reset Memory Bit ROL Rotate One Bit Left (Memory or Accumulator) cLe Clear Carry Flag ROR Rotate One Bit Right (Memory or Accumulator) CLD Clear Decimal Mode ATI Retum from Interrupt cu Clear Interrupt Disable Bit ATS Return from Subroutine civ Clear Overflow Flag cmp ‘Compare Memory and Accumulator Px Compare Memory and Index X sec ‘Subtract Memory from Accumulator with Borrow SEC Set Carry Flay cPY Compare M 1d Index Y ty Flag pare memory ang index SED | Set Decimal Mode DEC Decrement Memory by One Sel Set Interrupt Disable Status DEX Decrement Index X by One pate en to M DEY Dec it Index Y by One sumulator in Memory rement Index Y By sTx Store Index X in Memory EOR ““Exclusive-Or” Memory with Accumulator sty Store Index ¥ in Memory Inc Increment Memory by One TAX Transfer Accumulator to Index X NX Increment Index X by One TAY ‘Transfer Accumulator to Index Y INY Increment Index Y by One TSX ‘Transfer Stack Pointer to Index X TXA Transfer Index X to Accumulator MP Jump to New Location TXS Transfer Index X to Stack Register JSR Jump to New Location Saving Return Address TYA Transfer Index Y to Accumulator 3-124

R6501 One-Chip Microprocessor

3 Oe ULES SRSA LAR IRR UST

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1 Se, 1, 3

= [alee bes 8 2223 a i il D ccceasee sas 83 2 seo f Fe Pome 11 i] bais 11) bopbeeeetee Pred | PPPeeE Sheroa,/ 1 POSER RESET REN ate a = F ATT ij 9 $3 $ 2 seaee < |_TeeE aonenesersseassesctesneneonpansofvtcaanefescease Hn: i 3-125

R6501 One-Chip Microprocessor . APPENDIX B KEY REGISTER SUMMARY — en Por a CET TPet Tt] . — es CT ee canay cr room cowren re sem a xo rrocunon errs + SSE ITERAUPT OSABLE (1G) CPU Registers Hie fontnat mn occun. woe nee comune oO omen oO sent sernoa® et eee | Sot. Tae serlcn loe | | JSS *CLETEEEL LT Je ro | STE at TTTTiT {Tf === ePEEEE DET] | octets resroame | | (ein gh mpadence ae) LL earpoete 1 naan |_| coven peas nly L sesnepae fest) ne Mode Control Register coun Shore court evn Soon Pag seen Po me Interrupt Enable and Flag Registers sol T eT [+ [> [2] Te] | Tost ty e~bD>LEELET IT] <~ b) oo) Lge | er" i | a deme roman | 1} Seamer | Ponty Er jo4 Schattes: Lema me t—tmurna neem agyn ose oiirn asm noon wou oncvn uae $nevn ono am ove nan =p) “Via ene 1 Unde in Serial Communications Control Register 3127 ‘Serial Communications Status Register

a R6501 One-Chip Microprocessor ROO APPENDIX C ADDRESS ASSIGNMENTS/MEMORY MAPS/PIN FUNCTIONS C.1 1/0 AND INTERNAL REGISTER ADDRESSES = ee (HEX) READ [tise | Seen Upper Counter B Upper Latch B, Latch C—Latch B Lower Counter B, CLR Flag Lower Latch B. 8 == —

19 Upper Counter A Upper Latch A

18 ‘Lower Counter A, CLR Flag Lower Latch A 16 Serial Comm. Status Register Serial Comm, Status Reg. Bits 4 & 5 only 18 Sevial Comm. Control Regster Serial Comm. Control Register

14 Mode Control Register Mode Contro} Register

[ilies p= Interrupt Flag Flegster = Read FF Clear int Flag (Bis 0-3 only, Wit 0's only) oF 0c | | oc

08 RESERVED

09 These addresses are reserved and are used by the CPU duting Read and Write

08 operation over the external Data Bus (D0-D7). i eee

02 Port C Port

0000 Port A Port A

R6501 One-Chip Microprocessor C.2 FULL ADDRESS MODE MEMORY MAP—R6501 a rere [__nes vector | roa | _mmvecron—] ow / TEAL ‘ = f o10 / 00F [neem Ss steer] Lee JZ C.3 MULTIPLE FUNCTION PIN ASSIGNMENTS—PORT C AND PORT D oor [aime Tm MODE FUNCTION Per Por Pc2 PC2 Pcs Pca Pca ce Pc? POT POT Do ASIDI Poe poe be A602 Pos Pos D3 ATS Pos PDS 05 SIDS Pos Pos Ds 10108 PO7 PO? o7 AMDT 3429

R6501 One-Chip Microprocessor RO MAXIMUM RATINGS* [Parameter | Symbol | Value [Unit] *NOTE: Stresses above those listed may cause permanent [Sppowoage | ecBvmg| -0ate +7 |e] camageto nee, This asressatog ony and funion Supply Vi Veo& Van | -0.3t0 +70 | Vac co 5 Nn ‘operation of the device at these or any other conditions above Lapua Vohiege. = 0310 +70 | Vee those indicated in the other sections of this document is not Operating Temperature Range, Ts TL toTy °c implied. Exposure to absolute maximum rating conditions for ‘Commercial Ot0 +70 ‘extended periods may affect device reliability. Industrial =40 to +85 | DC CHARACTERISTICS (Voc = 50V £5%, Van = Voci Vsg = OV; Ta = T. to Ty, unless otherwise specified) RAM Standby Votage (Retention Mode) [Vm | 80 | [ve fv { RAM Standby Current Retention Mode) | lm | — [| # [| — [ ma | Tasasc | input High Voltage Vue Vv All Except XTU +20 xTu +40 [twputtow vores] MT oe | = | oe fv P input Leakage Current ny Vn = 01050V RES, NMI Taput Low Current Vi = 04v PA, PB, PC, PD Bupa High Vonage Gent LO) | Von | 24 [| veg | V| te = -10008_| Opal Low Vorape a a ee WO Port Pull-Up Resistance R PA0-PA7, PBO-P87, PCO-PC7 Dupul Loko Guron (Tree Sale OH | oe f= |= | ae [af Input Capacitance Tq = 25°C XTL, XTLO Vw = OV Al Others 15 10 MHz ‘Output Capacitance (Three-State Off) Ta = 25°C Vu = OV t= 1.0 MHz Power Dissipation (Quiputs High) a Notes: 1. Typical values measured al T, = 25°C and Voc = 5.0V. 2. Nogative sign indicates outward current flow, positive indicates inward flow. 3-130,

R6501 One-Chip Microprocessor APPENDIX E TIMING REQUIREMENTS AND CHARACTERISTICS E.1 GENERAL NOTES E.2 CLOCK TIMING 1. Veo = SV +5%, OC = TA < 70°C [wiz [amine _| 2. A valid Vec ~ RES sequence is required before proper [win | max | min | Max | Operation i achieved. [Fax cee [1000 [108 [500 | v0 3. All timing reference levels are 0.8V and 2.0V, unless Towns XTLI Input Clock 500 250 Pulse Width 22 =10 otherwise specified. xItO vss 4. Alltime units are nanoseconds, unless otherwise specified. hee a Width at Minimum 225 +20 5. All capacitive loading is 130pf maximum, except as noted Tove below: Tr Te | Output Clock Rise, | * |

8 S0pF maximum oe tire

PA, PI - Suman igemame [eee [= [=|] PC (ABB and Mux Mode) — 130pF maximum PC6, PC7 (Full Address Mode) — 130pF maximum ET Tove | xmu 18v 18 (CTL = Vs.) Towns \\$——— Tree se + 1. % | 3131

a R6501 One-Chip Microprocessor i SN E.3 ABBREVIATED MODE TIMING—PC AND PD (MCR 5 ~ 1, MCR 6 = 0,MCR7~ 1) | ‘SYMBOL PARAMETER } Mie 2 we tam | max | ma | ioe {PC5) RIW Setup Time — | 25 | — | 140 Tress |(PCO-PCA, PCB) Address Setup Time | — | 225 | — | 140 [ts (PD) Data Setup Time j so) — | 35 | _ [Teena |(PD) Data Read Hold Time w} — | 10) — |} Teo |(PD) Data Write Hold Time wo | — |) — Tosco (PD) Data Output Delay - 175 - 150 Toone (PCO-PC4, PC6) Address Hold Time ko - 30 | - [Tren (PCS) RW Hold Time | w - | 3) = [Teow | (C7) EMS Hold Time | | — | 10 | - [Teeve |(PC7) EMS Stabiization Time j 30} — |} 390 | — E.3.1 Abbreviated Mode Timing Diagram READ WRITE RW Y V UY, | MI] Ws I ‘PCRS Ms L— Tesw PC0-PCA,| | a ///, | 1; a = ld ee {+ —Teene Tpenw 3-132,

R6501 One-Chip Microprocessor £.4 MULTIPLEXED MODE TIMING—PC AND PD (MCR 5 = 1,MCR 6 ~ 1,MCR7 = 1) es [wan [wax [ wan | wax | [ies POS AW Soup tne] ‘| ame [ | 0 | Tres | Peo-Pca. Pom aasess Soup Tine | — | eas | — | 10 [rae [Porat Sono tne | = | es | — | 0] Tau [P0)awsoustow | = | L — | Tour (0) Ona Rew toertne | 0 | — [| = Trea (PO) Data Wie Ho Tere [af — [o> —| Trees [PD) Data Ouput oly ——=S«dYC ‘+ as | — | 80 Trou |POO-PCA, POS) Address Hold Time | 90 | — | 30 | — Trem (PD) Ad6ress Hold Time | 10 | 10 | to | 80 Trem (PCS) IW Hold Time [af — | so) — Mew Pon EWS Mestre | | = |) [Tae [PON Assess eENSDayTme | 0] | | [raw POM ERS SemiewenTne | wo | — | | [Tass [EWS soup Tine - | = | ss | = [20 NOTE 1 Vaties assume PCO-PC4, PCE and PC7 have he same copactive load E.4.1 Multiplex Mode Timing Diagram ‘READ WRITE e N ia Ta Rw - U7, wo V/) Ds ——_- teers | } = 7 (cn, -— Tew OY Th ohn te, vo ra ) | XD? CX XU 3 ey i TRBAS |__| TecvD TRBHR TRBHW 3-133

R6501 One-Chip Microprocessor Tote E.5 0, EDGE DETECT, COUNTERS, AND SERIAL I/O TIMING | sympot| . "PARAMETER twin ze | Srweot! [MN MAX | MIN | MAX i Ta we PrarwaDxa va T H Troe | PA,P8,PO TTL — so — | 500 ioe | Pa‘ Pe. pc owos | — © 1000 1000 ‘rom | po = ls = | 50 Penpheral Data SetupTme ! Tem PALPBLPC [20 = | 20] - Tew | PO. iso — | sol — SE aESnnEEE Penpheral Data Hed Tene 2 Tae | PAP.PC 75 wi nz PA0-PAD Eage Outeci ise Wah Toe Tee] | Teounrs A and 8 i [Tene PAS, PAS Input Pulse Wisth tle = Tac} — Tio__|_ PAPAS Outut Deay Sm! 0 i Pon 8 Lan Mage | Toue | PAOStobe Pose With Toe — [Tye — TTT | Be Date Satup Tine we oT fis. Tj ! Tr__|_ PB Data Hold Time ee ee ee i TSeraivo a | Te PABXMTA TIL — . so! s00 | [Team PABXMTR CMOS = 1000) = | 1000} LIST pas neve Sm Cox won Bac = |éToe Tene _PAGMT Cock—SR Mage (CMOS) _— 1000 | — 1000 NOTE 1 Manor Load Gapicince S00F Pasove Pap Ferre E.5.1 1/0, Edge Detect, Counter, and Serial I/O Timing 2 1.5V so ‘TPDSU PAO-PAT 20-PB7 poo - PCo-PC7 oo poo-poy | | RHR. — EDGE DETECTS KO (PA0-PAS) _ —— a ‘TEPW CNTR. PAA, PAS. 1.5 1.8V uv. rer ew CNTR rep 2.4V) (PAS, PAS) — oa Troow PD0-PO7 - =| ‘ToMOoS PAO-PAT TOW ay vost] PCO-PC7 PBO-P87 av +——_ pe — (LATCH MODE) 1.8V 1.5V pao-STROBE 3-134

a R6501 One-Chip Microprocessor lc Sea E.6 MICROPROCESSOR TIMING (D0-D7, A0-A12, A15, SYNC, R/W) Tom [Rw Seup tine | —| 2s | = | wo Taos [ AO-A12, A15 Setup | * | 75 __| time . | Tosu D0-D7 Data Setup Time _— [Te 0-07 Read Hold Time 10 | — [Tew [00-07 Write Hold Time [= | | — eee CC | Delay (Ta [smic Sau | — [aes | — Te | A0-A12,A15 Hold me | 20] — | 20 Trow [RW Hold Time ao} — | 20 Tree Extemal Memory Access | — | Tac — | Tae Time Tace = Tove Te Tacs Toss - | Tome SYNC Hold Time _ _30 | — so | E.6.1 Microprocessor Timing Diagram a write - -— —) = THRW | A li aw | trws =) may AD-AI2, ~ - - a ~ 7 ca | XK __| ‘TOSU—~| DATA O- TSYH | + TSYH sync Itsy (3-135

a R6501 One-Chip Microprocessor “GAPINPLASTIC QUAD IN-LINE PACKAGE (QUIP) Lo oe [e_[ ioe T i23_T cere [6600 | a [0 [048 T“os6 [ore | 0072} (e-[erase—| ose alalalalalafafalllllllllllalatel, <a Eat ret sep one poree] meee {sar} one_Dozie a a hi i i i i a | “ko on | Sg - 8 Lp 4———— ff - (a oe rH 3-136

R6501 One-Chip Microprocessor 68-PIN PLASTIC CHIP CARRIER (PCC) ' INDEX D—__» SEATING CORNER [+1 — PLANE Nrveevest:cbreeesel | t f if a: * | 4 PIN’ old INDICATOR B ong 02g nn 43 TOP VIEW SIDE VIEW & = i ° eae is a ca ele ne be os tr ‘SECTION A-A ‘TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE) = CHAM.J x 45° [waa wa] pooooonneooceoOR oo ee. pS a 2O ‘Os [xs sre [ara [ase [58] = FE [ae aar1_[ 260 [061 [oo] = 3 [ce] “carte [oer | S + [coer sar aes Tes | = S a az Sy [Cea—paoe_ m6 796 [005 | BO Qs [orf arse | B43 2S [os [zz | zaae_|o75 {os | voswanoapooganont a fo wike bot a A | CHAM. 17 PINS EJECTOR PIN MARKS en Wi 45* PER SIDE 4 PLCS BOTTOM OF Eater eer 3PLCS EQUALLY PACKAGE ONLY [x] son re | oo rr} ‘SPACES (TYPICAL) (moze rve [oro BOTTOM VIEW 3197

Selected Specification

List of Unclassifed Man... R6501 overview.

Overview

R6501 is listed in the Microcontroller category. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

ONE CHIP MICROPROCESSOR

Description

ONE CHIP MICROPROCESSOR

Source title R6501 Datasheet(PDF) - List of Unclassifed Manufacturers

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