R1LP0408C HITACHI

Document overview

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  • PDF pages: 14

Technical content

Features

  • Single 5 V supply: 5 V ± 10%
  • Access time: 55/70 ns (max)
  • Power dissipation:  Active: 10 mW/MHz (typ)  Standby: 4 µW (typ)
  • Completely static memory.  No clock or timing strobe required
  • Equal access and cycle times
  • Common data input and output.  Three state output
  • Directly TTL compatible.  All inputs and outputs
  • Battery backup operation.
  • Operating temperature: −40 to +85°C

Rev.1.00, Aug.01.2003, page 2 of 13

Ordering Information

Type No. Access time Package R1LP0408CSP-5SI 55 ns 525-mil 32-pin plastic SOP (32P2M-A) R1LP0408CSP-7LI 70 ns R1LP0408CSB-5SI 55 ns 400-mil 32-pin plastic TSOP II (32P3Y-H) R1LP0408CSB-7LI 70 ns R1LP0408CSC-5SI 55 ns 400-mil 32-pin plastic TSOP II reverse (32P3Y-J) R1LP0408CSC-7LI 70 ns

Rev.1.00, Aug.01.2003, page 3 of 13 Pin Arrangement A18 A16 A14 A12 I/O0 I/O1 I/O2 V SS V A15 A17 WE# A13 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 CC (Top view) 32-pin SOP 32-pin TSOP A18 A16 A14 A12 I/O0 I/O1 I/O2 V SS V A15 A17 WE# A13 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 CC (Top view) 32-pin TSOP (reverse) Pin Description Pin name Function A0 to A18 Address input I/O0 to I/O7 Data input/output CS# (CS) Chip select OE# (OE) Output enable WE# (WE) Write enable VCC Power supply VSS Ground

Rev.1.00, Aug.01.2003, page 4 of 13 Block Diagram I/O0 I/O7 CS# WE# OE# A3 A2A1A0 A6A5 V V CC SS Row Decoder Memory Matrix 2,048 2,048 Column I/O Column DecoderInput Data Control Timing Pulse Generator Read/Write Control A4 A7 A11 A15 A18 A10 A13 A17 A16 A14 A12 LSB MSB LSB MSB

Rev.1.00, Aug.01.2003, page 5 of 13 Operation Table WE# CS# OE# Mode V CC current I/O0 to I/O7 Ref. cycle × H × Not selected I SB, ISB1 High-Z  H L H Output disable I CC High-Z  H L L Read I CC Dout Read cycle L L H Write I CC Din Write cycle (1) L L L Write I CC Din Write cycle (2) Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value Unit Power supply voltage relative to VSS V CC −0.5 to +7.0 V Terminal voltage on any pin relative to VSS V T −0.5* to VCC + 0.3* V Power dissipation P T 0.7 W Operating temperature Topr −40 to +85 °C Storage temperature range Tstg −65 to +150 °C Storage temperature range under bias Tbias −40 to +85 °C Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +7.0 V. DC Operating Conditions (Ta = −40 to +85°C) Parameter Symbol Min Typ Max Unit Supply voltage V CC 4.5 5.0 5.5 V V SS 0 0 0 V Input high voltage V IH 2.2  V CC + 0.3 V Input low voltage V IL −0.3*  0.8 V Note: 1. V IL min: −3.0 V for pulse half-width ≤ 30 ns.

Rev.1.00, Aug.01.2003, page 6 of 13 DC Characteristics Parameter Symbol Min Typ * Max Unit Test conditions Input leakage current |I LI|   1 µA Vin = V SS to VCC Output leakage current |I LO|   1 µA CS# = V IH or OE# = VIH or WE# = VIL or VI/O = VSS to VCC Operating current I CC  1.5 3 mA CS# = V IL, Others = VIH/ VIL, II/O = 0 mA Average operating current I CC1  8 25 mA Min. cycle, duty = 100%, CS# = VIL, Others = VIH/VIL II/O = 0 mA I CC2  2 5 mA Cycle time = 1 µs, duty = 100%, I I/O = 0 mA, CS# ≤ 0.2 V, VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V Standby current I SB  0.1 0.5 mA CS# = V IH Standby current to +85 °C I SB1   20* µA Vin ≥ 0 V, CS# ≥ VCC − 0.2 V   10* µA to +40 °C I SB1  1.0* 10* µA  1.0* µA −20°C to +25°C I SB1  0.8* 10* µA  0.8* µA Output low voltage V OL   0.4 V I OL = 2.1 mA Output high voltage V OH 2.4   V I OH = −1.0 mA V OH2 2.6   V I OH = −0.1 mA Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed. 2. L version. ( −7LI) 3. SL version. ( −5SI) Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance Cin   8 pF Vin = 0 V 1 Input/output capacitance C I/O   10 pF V I/O = 0 V 1 Note: 1. This parameter is sampled and not 100% tested.

Rev.1.00, Aug.01.2003, page 7 of 13 AC Characteristics (Ta = −40 to +85°C, VCC = 5 V ± 10%, unless otherwise noted.) Test Conditions

  • Input pulse levels: V IL = 0.4 V, VIH = 2.4 V
  • Input rise and fall time: 5 ns
  • Input and output timing reference levels: 1.5 V
  • Output load: 1 TTL Gate + CL (50 pF) (R1LP0408C-5I)

1 TTL Gate + C L (100 pF) (R1LP0408C-7I)

(Including scope and jig) Read Cycle R1LP0408C-I -5 -7 Parameter Symbol Min Max Min Max Unit Notes Read cycle time t RC 55  70  ns Address access time t AA  55  70 ns Chip select access time t CO  55  70 ns Output enable to output valid t OE  25  35 ns Chip select to output in low-Z t LZ 10  10  ns 2 Output enable to output in low-Z tOLZ 5  5  ns 2 Chip deselect to output in high-Z tHZ 0 20 0 25 ns 1, 2 Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2 Output hold from address change tOH 10  10  ns

Rev.1.00, Aug.01.2003, page 8 of 13 Write Cycle R1LP0408C-I -5 -7 Parameter Symbol Min Max Min Max Unit Notes Write cycle time t WC 55  70  ns Chip selection to end of write t CW 50  60  ns 4 Address setup time t AS 0  0  ns 5 Address valid to end of write t AW 50  60  ns Write pulse width t WP 40  50  ns 3, 12 Write recovery time t WR 0  0  ns 6 Write to output in high-Z t WHZ 0 20 0 25 ns 1, 2, 7 Data to write time overlap t DW 25  30  ns Data hold from write time t DH 0  0  ns Output active from end of write tOW 5  5  ns 2 Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2, 7 Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. A write occurs during the overlap (t WP ) of a low CS# and a low WE#. A write begins at the later transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going high or WE# going high. t WP is measured from the beginning of write to the end of write. 4. t CW is measured from CS# going low to the end of write. 5. t AS is measured from the address valid to the beginning of write. 6. t WR is measured from the earlier of WE# or CS# going high to the end of write cycle. 7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE# transition, the output remain in a high impedance state. 9. Dout is the same phase of the write data of this write cycle. 10. Dout is the read data of next address. 11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 12. In the write cycle with OE# low fixed, t WP must satisfy the following equation to avoid a problem of data bus contention. tWP ≥ tDW min + tWHZ max

Rev.1.00, Aug.01.2003, page 9 of 13 Timing Waveform Read Timing Waveform (WE# = VIH) tAA tCO tRC tLZ tOE tOLZ tHZ tOHZ Valid data Valid address High impedance Address CS# OE# Dout tOH

Rev.1.00, Aug.01.2003, page 10 of 13 Write Timing Waveform (1) (OE# Clock) tWC tCW tWPtAS tOHZ tDW tDH tAW tWR Address OE# CS# WE# Dout Din Valid data Valid address High impedance

Rev.1.00, Aug.01.2003, page 11 of 13 Write Timing Waveform (2) (OE# Low Fixed) Address CS# WE# Dout Din tWC tCW tWR tAW tWP tAS tWHZ tOW tOH tDW tDH *11 *9 *10 Valid data Valid address High impedance

Rev.1.00, Aug.01.2003, page 12 of 13 Low V CC Data Retention Characteristics (Ta = −40 to +85°C) Parameter Symbol Min Typ* Max Unit Test conditions* VCC for data retention V DR 2   V CS# ≥ VCC − 0.2 V, Vin ≥ 0 V Data retention current to +85°C I CCDR *   20 µA V CC = 3.0 V, Vin ≥ 0 V CS# ≥ VCC − 0.2 V I CCDR *   10 to +40 °C I CCDR *  1.0 10 µA I CCDR *  1.0 3 −20°C to +25°C I CCDR *  0.8 10 µA I CCDR *  0.8 3 Chip deselect to data retention time tCDR 0   ns See retention waveform Operation recovery time t R t RC *   ns Notes: 1. This characteristic is guaranteed only for L version. 2. This characteristic is guaranteed only for SL version. 3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode, Vin levels (address, WE#, OE#, I/O) can be in the high impedance state. 4. Typical values are at V CC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. 5. t RC = read cycle time. Low V CC Data Retention Timing Waveform (CS# Controlled) VCC 4.5 V 2.4 V 0 V CS# tCDR tR CS# ≥ VCC – 0.2 V VDR Data retention mode

Rev.1.00, Aug.01.2003, page 13 of 13 Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan. Colophon 0.0

Rev.1.00, Aug.01.2003, page 14 of 13 Revision Record Rev. Date Contents of Modification Drawn by Approved by 1.00 Aug. 01, 2003 Initial issue