Power Management

PTIOL221RGER

Texas Instruments

TIOL221 Dual Channel IO-Link Device PHY with Integrated LDO and SPI Interface SEPTEMBER 2024

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TIOL221 TI

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Technical content

TIOL221 Dual Channel IO-Link Device PHY with Integrated LDO and SPI Interface

1 Features

7V to 36V supply voltage
IO-link configurable CQ output with auxiliary digital output (DO) and digital input (DI) channels
Configurable via pin-control or SPI interface
PNP, NPN or IO-Link configurable CQ output – IEC 61131-9 COM1, COM2 and COM3 Data Rate Support
Output drivers with low power dissipation and high configurability – Low RDSON 2.5Ω (typical) – Active driver current limiting capability – Configurable driver overcurrent limit: 50mA to 350mA – Active reverse polarity protection of up to 65V on LP, CQ, DO and DI – Safe and fast demagnetization of inductive loads
Integrated protection features for robust systems – Fault indicator for overcurrent, overtemperature and UVLO faults – Extended ambient temperature operation: –40°C to 125°C – ±8kV IEC 61000-4-2 ESD contact discharge – ±4kV IEC 61000-4-4 electrical fast transient – ±1.2kV, 500Ω IEC 61000-4-5 surge
Large capacitive and inductive load driving capability
Integrated LDO provides up to 20mA current
Optional external regulator input (5V) to reduce internal power dissipation in the LDO
Small space-saving package options – 4mm x 4mm VQFN package – 2.7mm x 2.7mm DSBGA package

2 Applications

Field Transmitters and actuators
Factory automation
Process automation
IO-link PHY in remote IO

3 Description

The TIOL221 transceiver integrates dual low-power output drivers with active reverse polarity protection. When the device is connected to an IO-Link controller through a three-wire interface, the controller can initiate communication, and exchange data with the remote node while the TIOL221 acts as a complete physical layer for the communication. The device also integrates an auxiliary DI channel. The device is capable of withstanding up to 1.2kV (500Ω) of IEC 61000-4-5 surge and feature integrated reverse polarity protection. In addition to the SPI interface for configurability and expanded diagnostic capability, a simple pin-programmable interface allows easy interfacing with the controller circuits. The output current limit can be configured using either an external resistor or per-configured limits via SPI interface. TIOL221 can be configured to generate wake-up pulse, and be used in IO-link controller applications. Fault reporting and internal protection functions are provided for undervoltage, overcurrent and overtemperature conditions.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) TIOL221 VQFN (24) 4mm x 4mm DSBGA (25) 2.7mm x 2.7mm (1) For more information, see Section 12. (2) The package size (length × width) is a nominal value and includes pins, where applicable. TIOL221 ILIM_ADJ1 EN1 TX1 VOUT CQ LM WU RX1 ILIM_ADJ2 EN2 TX2 DO RX2 DI SCK SDI/NPN INT/NFLT1 LP SPI/PIN CS /PP Buck Regulator GND CQ DO V5IN SDO/NFLT2 Microcontroller VCC 3.3 V VSEL GND GND GND RESET R VOUT R VOUT Typical Application Diagram ADVANCE INFORMATION TIOL221 SLLSFS6 – SEPTEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

10.1 Receiving Notification of Documentation Updates..44

12 Mechanical, Packaging, and Orderable

SLLSFS6 – SEPTEMBER 2024 www.ti.com

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4 Pin Configuration and Functions

24SDI/NPN 7 ILIM_ADJ2 1CS/PP 18 WU 23SPI/PIN 8 CQ 2RX1 17 TX2 22SCK 9 LP 3EN1 16 VSEL 21SDO/NFLT2 10 LM 4TX1 15 RX2 20INT/NFLT1 11 DO 5V5IN 14 RESET 19EN2 12 DI 6ILIM_ADJ1 13 VOUT Not to scale Thermal Pad Figure 4-1. RGE (VQFN), 24-Pin (Top View) 1 2 3 4 5 A B C D E Not to scale CQ LP LM DO DI RESET ILIM_ADJ1 ILIM_ADJ2 VOUT V5IN TX1 EN1 NC VSEL RX2 RX1 SPI/PIN SDO/NFLT2 WU TX2 CS/PP SDI/NPN SCK INT/NFLT1 EN2 Figure 4-2. YAH (DSBGA), 25-Pin (Top View, Bumps Down) Table 4-1. Pin Functions PIN NAME PIN NUMBER I/O TYPE DESCRIPTION VQFN DSBGA CQ 8 A1 I/O High Voltage IO-link signal data pin. CS/PP 1 E1 I Digital Chip select input pin in the SPI-mode. DI 12 A5 I High Voltage DI receiver Input. DI receiver output can be monitored at the RX2 pin. DO 11 A4 O High Voltage DO driver output. DO is the inverse logic level of the input at the TX2 pin. EN1 3 C2 I Low voltage Digital CQ driver enable input signal from the local controller. Logic low sets the CQ output at Hi-Z. Weak internal pull-down. EN2 19 E5 I Low voltage Digital DO driver enable input signal from the local controller. Logic low sets the DO output at Hi-Z. Weak internal pull-down. ILIM_ADJ1 6 B2 I Low voltage Analog Input for the current limit adjustment for the CQ driver. Connect resistor RSET1 between ILIM_ADJ1 and LM. ILIM_ADJ2 7 B3 I Low voltage Analog Input for the current limit adjustment for the DO driver. Connect resistor RSET2 between ILIM_ADJ2 and LM. INT/NFLT1 20 E4 O Low voltage Digital Interrupt output, push-pull (SPI-mode) or fault indicator for CQ channel, open- drain (pin-mode) LM 10 A3 G Ground Ground. LP 9 A2 PI High Voltage Power supply input (24V typical) to the device. Connect 1µF capacitor to LM (ground) as close to the device as possible. NC -- C3 NC No Connect Not connected internally. RX1 2 D1 O Low voltage Digital C/Q Receiver Logic Output. RX2 is the inverse logic level of the signal on the CQ input. RX2 15 C5 O Low voltage Digital DI Receiver Logic Output. RX2 is the inverse logic level of the signal on the DI input. SCK 22 E3 I Low voltage Digital SPI clock input SDI/NPN 24 E2 I Low voltage Digital SPI serial data input (SPI-mode) Or NPN mode selector (pin-mode) SDO/NFLT2 21 D3 O Low voltage Digital SPI serial data output, push-pull (SPI-mode) or fault inductor for DO channel, open-drain (pin-mode) www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TIOL221 ADVANCE INFORMATION

Table 4-1. Pin Functions (continued) PIN NAME PIN NUMBER I/O TYPE DESCRIPTION VQFN DSBGA SPI/PIN 23 D2 I Low voltage Digital SPI or pin-mode selection input. Drive this pin low for pin-mode operation. Drive this pin high for SPI-mode control. TX1 4 C1 I Low voltage Digital CQ driver input data from local microcontroller. Weak internal pull-up. TX2 17 D5 I Low voltage Digital DO driver input data from local microcontroller. Weak internal pull-up. VOUT 13 B4 PO Low voltage LDO regulator output. Output level determined by VSEL pin VSEL 16 C4 I Low voltage

Connect to GND for 3.3V LDO output with LP as the LDO input supply
Connect to VOUT for 5V LDO output with LP as the LDO input supply
Leave the pin floating for 3.3V LDO output with V5IN as the LDO input supply RESET 14 B1 O Low voltage Reset output pin, open-drain, active low. The pin behaves as a RESET pin to indicate UV or VOUT. V5IN 5 B5 PI Low voltage (Optional) Connect this pin 5V supply input from external regulator to reduce the power dissipation from the internal regulator. Leave the pin floating if unused. WU 18 D4 O Low voltage Digital Wake-up indicator to the local microcontroller. Open-drain output, connect this pin via pull-up resistor to VCC_OUT. Thermal Pad Thermal Pad N/A G Ground Connect the exposed thermal pad to ground (LM) for optimal thermal and electrical performance TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT LP, CQ, DO, DI Steady state voltage for LP, CQ, DO and DI –65 65 V Transient pulse width < 100 µs for LP and CQ –70 70 V |V(LP) – V(CQ)|, |V(LP) – V(DO)|, |V(LP) – V(DI)|, | V(CQ) – V(DO)|, |V(CQ) – V(DI)|, |V(DO) – V(DI)| Voltage drop between bus pins 65 V VOUT Regulator output voltage –0.3 6 V TX1, TX2, EN1, EN2, VSEL, RX1, RX2, CS/PP, SDI/NPN, SDO/NFLT2, SCK, INT/ NFLT1, WU, ILIM_ADJ1, ILIM_ADJ2, SPI/PIN Logic pin voltage –0.3 min(VOUT+0.3 , 6) V Output current RX1, RX2, WU, INT/NFLT1, SDO/NFLT2, –5 5 mA Storage temperature, Tstg -55 170 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. All voltages are with reference to the L- pin, unless otherwise specified.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins ±4000 V V(ESD) Electrostatic discharge Charged Device Model (CDM), per ANSI/ESDA/JEDEC JS-002 (2) All pins ±750 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 ESD Ratings - IEC Specifications

V(ESD) Electrostatic discharge IEC 61000-4-2 ESD (Contact Discharge), LP, CQ, DO, DI and LM (1) (2) ±8,000 VElectrostatic discharge IEC 61000-4-5, 1.2 µs/50 µs Surge with 500 Ω in series, LP, CQ, DO, DI and LM (1) ±1,200 Electrostatic discharge IEC 61000-4-4 EFT (Fast transient or burst), LP, CQ, DO, DI and LM (1) ±4,000 (1) Minimum 100-nF capacitor is required between LP and LM. Minimum 1-µF capacitor is required between VOUT and LM. (2) Device requires a minimum 1nF capacitor between the CQ/DO driver output and LM to pass ±8000 V. Passing level is ±4000 V without the minimum 1nF capacitor

5.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V(LP) 24V Input Supply Voltage 7 24 36 V V(V5IN) 5V Input Supply Voltage 5V Input Supply Voltage 4.5 5 5.5 V V(I) Logic level input voltage at TX1, TX2, EN1, EN2,CS/PP, SDI/NPN, SCK, SPI/PIN 3.3 V configuration 3 3.3 3.6 5 V configuration 4.5 5 5.5 V 1/tBIT Data rate (Communication mode) 250 kbps I(VOUT) LDO output current 20 mA TA Operating ambient temperature –40 125 °C TJ Junction temperature -40 150 °C www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TIOL221 ADVANCE INFORMATION

5.5 Thermal Information

THERMAL METRIC(1) TIOL221 UNIT RGE (24 Pins) YAH (25 Pins) RθJA Junction-to-ambient thermal resistance 32.2 58.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 27.2 0.2 °C/W RθJB Junction-to-board thermal resistance 11.4 14.5 °C/W ψJT Junction-to-top characterization parameter 0.3 0.1 °C/W ψJB Junction-to-board characterization parameter 11.4 14.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.7 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.6 Electrical Characteristics

Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical values are at LP = 24 V, VVOUT = 3.3 V and TA = 25 ℃ unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (LP) I(LP-SHDN) Supply quiescent current in shutdown mode CQ TX and RX, DO and DI are disabled. No load on VOUT. SPI mode only 1.2 2.1 mA I(LP-RX-ONLY) Supply current when only inputs are enabled CQ and DO are disabled. CQ RX and DI are enabled. No load on VOUT. RSETx >= 10kΩ (current limit < 500mA) , EN1=EN2=L CQ and DO are disabled. CQ RX and DI are enabled. No load on VOUT 1.4 2.5 mA I(LP-CQ-DO) Quiescent supply current when both CQ and DO are enabled. V5IN supplied externally RSETx >= 10kΩ. TX1=TX2=H, No load on CQ or DO, Push-pull or NPN mode only 3.1 4 mA I(LP-CQ-DO) RSETx >= 10kΩ. TX1=TX2=L, No load on CQ or DO 4.7 5.5 mA V(LP-UVLO) LP under voltage lockout LP falling; NFAULT = Hi-Z LP falling; NFAULT = Hi-Z 6 6.3 V V(LP-UVLO) LP under voltage lockout LP rising; NFAULT = LOW LP rising; NFAULT = LOW 6.5 6.8 V V(LP- UVLO,HYS) LP under voltage hysteresis Rising to falling threshold Rising to falling threshold 200 mV V(LPW) LP undervoltage warning LP falling 14 16 18 V V(LPW-HYS) LP undervoltage warning hysteresis 530 mV V5IN V5IN(UVLO, F) Falling UVLO level for V5IN V5IN Falling 3.4 3.5 3.6 V V5IN(UVLO, R) Rising UVLO level for V5IN V5IN Rising 3.7 3.8 4.0 V I5_IN Input supply current at 5VIN CQ and DO disabled, No load on VOUT 0.15 1 mA LINEAR REGULATOR (VOUT) V(VOUT) Voltage regulator output VOUT set to 5 V 4.75 5 5.25 V VOUT set to 3.3 V 3.13 3.3 3.46 V LINEREGVO UT Line regulation (dV(VOUT)/dV(LP)) I(VCC_OUT) = 1 mA V(LP) = 7 V to 36 V (VOUT = 5 V) V(LP) = 7 V to 36 V OR V5IN = 4.5 to 5.5 V (VOUT = 3.3 V) 1.7 mV/V LOADREGV OUT Load regulation (dV(VOUT)/V(OUT)) V(LP) = 24 V for VOUT=5V V(LP) = 24 V or V5IN= 5V for VOUT=3.3 V I(VCC_OUT) = 100 µA to 20 mA 1 % UVVOUT5F Falling UV threshold on VOUT (5V setting) VSEL connected to VOUT, VOUT falling 3.4 3.6 3.8 V UVVOUT5R Rising UV threshold on VOUT (5V setting) VSEL connected to VOUT, VOUT rising 3.6 3.8 4.0 V TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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5.6 Electrical Characteristics (continued)

Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical values are at LP = 24 V, VVOUT = 3.3 V and TA = 25 ℃ unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UVVOUT3F Falling UV threshold on VOUT (3.3V setting) VSEL connected to GND or Floating(V5IN supplied), VOUT falling 2.5 2.7 2.9 V UVVOUT3R Rising UV threshold on VOUT (3.3V setting) VSEL connected to GND or Floating(V5IN supplied), VOUT rising 2.6 2.8 3.0 V PSSR Power Supply Rejection Ratio 100 kHz, I(VCC_OUT) = 20 mA 40 dB DRIVER OUTPUT (CQ, DO) RDSON-HS High-side driver on-resistance ILOAD = 200 mA, Current Limit = 300 mA 2.5 4.5 Ω RDSON-LS Low-side driver on-resistance ILOAD = 200 mA, Current Limit = 300 mA 2.5 4.5 Ω IO(LIM) Driver output current limit SPI/PIN = LOW V(DRIVER)= (VLP - 3) V or 3V, RSETx = 110 kΩ 35 55 70 mA RSETx = 10 kΩ 300 350 400 mA RSETx = 0 to 5 kΩ 500 mA RSETx = OPEN 260 330 400 mA IO(LIM) Driver output current limit SPI/PIN = HIGH, V(DRIVER)= (VLP - 3) V or 3V, 3h[7:6]= 0h 35 60 75 mA 3h[7:6]= 1h 50 75 95 mA 3h[7:6]= 2h 100 140 175 mA 3h[7:6]= 3h 150 190 260 mA 3h[7:6]= 4h 200 230 330 mA 3h[7:6] = 5h 250 290 410 mA 3h[7:6] = 6h 300 350 485 mA 3h[7:6]= 7h 500 700 mA IOZ(CQ) CQ leakage EN1 = LOW, 0 ≤ V(CQ) ≤ (V(LP) - 0.1 V) –2 2 µA ILLM(CQ) CQ load discharge current EN1 = LOW, RSET1 = 0 to 5 kΩ (1), V(CQ) >= 5 V 5 8.5 15 mA ILLM(DO) DO load discharge current EN2 = LOW, RSET2 = 0 to 5 kΩ; V(DO) >= 5 V 5 8.5 15 mA IPU-DO DO driver weak pull-up current SPI/PIN=HIGH, EN2=LOW, TX2=HIGH, RSET2: 10 kΩ to 110 kΩ AND Weak pull- up enabled (SPI mode only) 0 ≤ V(DO) ≤ (V(LP) - 2 V) 40 50 80 µA IPD-DO DO driver weak pull-down current (SPI/PIN=HIGH, EN2=LOW, TX2=LOW, RSET2: 10 kΩ to 110 kΩ AND Weak pull-up enabled (SPI mode only) 2 ≤ V(DO) ≤ V(LP) 40 50 80 µA IPU-CQ CQ driver weak pull-up current Driver disabled, Weak pull-up enabled (SPI mode) 0 ≤ V(CQ) ≤ (V(LP) - 2 V) 40 50 80 µA IPD-CQ CQ driver weak pull-down current Driver disabled, Weak pull-down enabled (SPI mode) 2 ≤ V(CQ) ≤ V(LP) 40 50 80 µA RECEIVER INPUT (CQ, DI) V(THH) Input threshold “H” V(LP) > 18 V, EN= LOW 10.5 13 V V(THL) Input threshold “L" 8 11.5 V V(HYS) Receiver Hysteresis (V(THH) - V(THL)) 0.75 V V(THH) Input threshold “H” V(LP) < 18 V, EN= LOW See Note (2) See Note (3) V V(THL) Input threshold “L" V(LP) < 18 V, EN= LOW See Note (4) See Note (5) V V(HYS) Receiver Hysteresis (V(THH) - V(THL)) 0.75 V CIN-CQ CQ input capacitance CQ driver disabled, weak pull-up/ pull-down disabled, f =100kHz 150 pF CIN-DI DI input capacitance f =100kHz 100 pF www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TIOL221 ADVANCE INFORMATION

Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical values are at LP = 24 V, VVOUT = 3.3 V and TA = 25 ℃ unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPU-DI DI weak pull-up current SPI Mode, Weak pull-up enabled on DI pin 0 ≤ V(DI) ≤ (V(LP) - 2 V) 40 50 80 µA IPD-DI DI weak pull-down current SPI Mode, Weak pull-down enabled on DI pin 2 ≤ V(DI) ≤ V(LP) 40 50 80 µA LOGIC-LEVEL INPUTS (CS/PP, SCK, SDI/NPN, SPI/PIN, EN1, EN2, TX1, TX2, VSEL) VIL Input logic low voltage 0.3*VOUT V VIH Input logic high voltage 0.7*VOUT V RPD Pull-down resistance at EN1, EN2, SDI/NPN, SCK 100 kΩ RPU Pull-up resistance at TX1, TX2, , CS/PP, SPI/PIN 100 kΩ RPU Pull-up resistance at VSEL 1000 kΩ LOGIC-LEVEL OUTPUTS (WU, SDO/NFLT2, INT/NFLT1, RX1, RX2, RESET) VOH Output logic high voltage RX1, RX2, SDO, INT IO = 4 mA IO = 4 mA VOUT-0.5 V VOL Output logic low voltage IO = 4 mA 0.4 V IOZ Output high impedance leakage at NFLT1, NFLT2, WU, RESET Output in Hi-Z, VO = 0 V or VCC_IN/OUT –1 1 µA PROTECTION CIRCUITS T(WRN) Thermal warning Die temperature TJ 125 °C T(SDN) Thermal shutdown 150 160 °C T(HYS) Thermal hysteresis for shutdown 14 °C T(WRN) Thermal hysteresis for warning Die temperature TJ Die temperature TJ 14 °C IREV CQ Leakage current in reverse polarity EN=LOW, TX=x; LP= 24 V VCQ = (V(LP) -36V) OR V(CQ) = (V(LP) +36V) 60 µA EN=LOW, TX=x; LP= 24 V VCQ = (V(LP) -65V) OR V(CQ) = 65V 110 µA EN = HIGH, TX = LOW; V(CQ to LP) = 3 V, RSET >= 10 kΩ 650 µA EN = HIGH, TX = HIGH; V(CQ to LM) = -3 V 10 µA (1) Current fault indication and current fault auto recovery will be de-activated. (2) VTHH (min) = 5 V + (11/18) [V(LP) - 8 V] (3) VTHH (max) = 6.5 V + (13/18) [V(LP) - 8 V] (4) VTHL (min) = 4 V + (8/18) [V(LP) -8 V] (5) VTHL (max) = 6 V + (11/18) [V(LP) -8 V] TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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5.7 Switching Characteristics

Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical values are at LP = 24 V, VVOUT = 3.3 V and TA = 25 ℃ unless otherwise specified. PARAMETER TEST CONDITIONS TEST CONDITI ONS TEST CONDITIONS MIN TYP MAX UNIT CQ, DO DRIVER tPLH Driver propagation delay, low-to-high transition See Test Circuit for Driver Output Measurements and Driver Output Switching Waveforms RL = 2 kΩ CL = 5 nF Push-pull and PNP configuration RSET = 10 kΩ 600 1200 ns tPHL Driver propagation delay, high-to-low transition See Test Circuit for Driver Output Measurements and Driver Output Switching Waveforms RL = 2 kΩ CL = 5 nF Push-pull and NPN configuration RSET = 10 kΩ 600 1200 ns tP(skew) Driver propagation delay skew. |tPLH - tPHL | See Test Circuit for Driver Output Measurements See Driver Output Switching Waveforms RL = 2 kΩ CL = 5 nF Push-pull configuration RSET = 10 kΩ 100 ns tPZH Driver enable delay high See Test Circuit for Driver Output Measurements and Driver Enable/Disable Timing Diagrams RL = 2 kΩ CL = 5 nF Push-pull and PNP configuration only RSET = 10 kΩ 4 µs tPZL Driver enable delay low See Test Circuit for Driver Output Measurements and Driver Enable/Disable Timing Diagrams RL = 2 kΩ CL = 5 nF Push-pull and NPN configuration only RSET = 10 kΩ 4 µs tPHZ Driver disable delay high See Test Circuit for Driver Output Measurements and Driver Enable/Disable Timing Diagrams RL = 2 kΩ CL = 5 nF Push-pull and PNP configuration only RSET = 10 kΩ 4 µs tPLZ Driver disable delay low See Test Circuit for Driver Output Measurements and Driver Enable/Disable Timing Diagrams RL = 2 kΩ CL = 5 nF Push-pull and NPN configuration only RSET = 10 kΩ 4 µs tr Driver output rise time See Test Circuit for Driver Output Measurements and Driver Output Switching Waveforms RL = 2 kΩ CL = 5 nF Push-pull and PNP configuration RSET = 10 kΩ 200 530 900 ns tf Driver output fall time See Test Circuit for Driver Output Measurements and Driver Output Switching Waveforms RL = 2 kΩ CL = 5 nF Push-pull and NPN configuration RSET = 10 kΩ 200 480 900 ns www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TIOL221 ADVANCE INFORMATION

5.7 Switching Characteristics (continued)

Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical values are at LP = 24 V, VVOUT = 3.3 V and TA = 25 ℃ unless otherwise specified. PARAMETER TEST CONDITIONS TEST CONDITI ONS TEST CONDITIONS MIN TYP MAX UNIT |tr – tf| Difference in rise and fall time See Test Circuit for Driver Output Measurements and Driver Output Switching Waveforms RL = 2 kΩ CL = 5 nF Push-pull configuration only RSET = 10 kΩ 50 ns tWU1 Wake-up recognition begin See Wake-up recognition timing diagram 45 60 75 µs tWU2 Wake-up recognition end 85 100 145 µs tpWAKE Wake-up output delay 150 µs tWUL Wake output pulse duration on wake detection 175 225 285 µs tSC Current fault blanking time See Wake-up recognition timing diagram (SPI/PIN = low and 10 kΩ <= RSETx <= 110 kΩ) OR SPI/PIN=high and CQ_BL_TIME[1:0]=00b (CQ) OR DO_BL_TIME[1:0]=00b (DO) 0.175 0.2 ms SPI/PIN=high and CQ_BL_TIME[1:0]=01b (CQ) OR DO_BL_TIME[1:0]=01b (DO) 0.5 ms SPI/PIN=high and CQ_BL_TIME[1:0]=10b (CQ) OR DO_BL_TIME[1:0]=10b (DO) 5 ms (SPI/PIN = low and ILIM_ADJ floating) OR SPI/PIN=high and CQ_BL_TIME[1:0]=11b (CQ) OR DO_BL_TIME[1:0]=11b (DO) 0.5 2 4 µs tAR Auto retry time after current fault Auto retry time after current fault SPI/PIN = L OR SPI/PIN=H and CQ_RETRY_TIME=00b 50 ms SPI/PIN=H and CQ_RETRY_TIME=01b 100 ms SPI/PIN=H and CQ_RETRY_TIME=10b 200 ms SPI/PIN=H and CQ_RETRY_TIME=11b 500 ms t(UVLO) CQ and DO re-enable delay after UVLO (1) CQ and DO re-enable delay after UVLO (1) SPI/PIN = L OR SPI/PIN=H and T_UVLO=1b0 0.1 0.25 1 ms t(UVLO) CQ and DO re-enable delay after UVLO (1) CQ and DO re-enable delay after UVLO (1) SPI/PIN = L OR SPI/PIN=H and T_UVLO=1b1 10 30 50 ms CQ, DI RECEIVER tPLH_CQ, tPHL_CQ CQ Receiver propagation delay See Receiver Test Circuit Diagram and Receiver Timing Diagram CL=15 pF SPI/PIN=L OR SPI/PIN=H and CQ_RX_FILTER=1b0 0.2 0.36 µs SPI/PIN=H and CQ_RX_FILTER=1b1 1.15 1.6 µs tPLH_DI, tPHL_DI DI Receiver propagation delay SPI/PIN=L OR SPI/PIN=H and DI_RX_FILTER=1b0 1 1.5 µs SPI/PIN=H and DI_RX_FILTER=1b1 1.8 2.7 µs SPI Timing (CS, SCK, SDI, SDO/CUR_OK2) tINT_TOG INT pin High/low time (when toggling) COUT= 10 pF 100 µs TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical values are at LP = 24 V, VVOUT = 3.3 V and TA = 25 ℃ unless otherwise specified. PARAMETER TEST CONDITIONS TEST CONDITI ONS TEST CONDITIONS MIN TYP MAX UNIT fSCK_BURS T Maximum SPI clock frequency Burst mode

10 MHz

tSCKH SCK pulse-width high 50 ns tSCKL SCK pulse-width low 50 ns fSCK Maximum SPI clock frequency Non-burst mode

12.5 MHz

tSCKH SCK pulse-width high 40 ns tSCKL SCK pulse-width low 40 ns tCSS CS falling edge to SCK rise time 20 ns tCSH SCK rise to CS rise hold time 40 ns tDH SDI hold time 10 ns tDS SDI setup time 25 ns tDO SDO data propagation delay COUT= 10 pF 20 ns tDORF SDO rise and fall time COUT= 10 pF 20 ns tCSPW Minimum CS pulse width (idle time between SPI transactons) 10 ns (1) CQ/DO output remains Hi-Z for this time www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TIOL221 ADVANCE INFORMATION

6 Parameter Measurement Information

CQ, DO TX1, TX2 EN1, EN2 RL CL CQ, DO TX1, TX2 EN1, EN2 CL RL LM PNP , Push-Pull Mode NPN Mode LP LM Figure 6-1. Test Circuit for Driver Switching tr tf VOH VOL 80% 20% 80% 20% TX CQ 50% 50% tPHL tPLH VOL VOH VOL CQ VOH CQ Figure 6-2. Waveforms for Driver Output Switching Measurements EN1, EN2 CQ, DO 50% 50% tPZL tPLZ 10% EN1, EN2 CQ, DO 50% 50% tPZH tPHZ 90% V(LP) TX1, TX2 V(LP) VOUT TX1, TX2

0 V0 V

NPN Mode PNP and Push-Pull Mode Figure 6-3. Waveforms for Driver Enable or Disable Time Measurements RX1, RX2 CQ, DI CL Figure 6-4. Test Circuit for Receiver Switching TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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Figure 6-8. SPI Read/Write Timing Characteristics CQ, DO TX1, TX2 EN1, EN2 R PNP , Push-Pull Mode CQ, DO TX1, TX2 EN1, EN2 NPN Mode LP L R L Figure 6-9. Driving the Inductive Load CQ, DO TX1, TX2 EN1, EN2 R C L CQ, DO TX1, TX2 EN1, EN2 CL R LM PNP , Push-Pull Mode NPN Mode LP CL Figure 6-10. Driving the Capacitive Load TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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Figure 6-11. Interrupt Pin Toggling Behavior (SPI Mode; INT_TOG = 1b) www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TIOL221 ADVANCE INFORMATION

7 Detailed Description

7.1 Overview

Figure 7-1 shows the functional block diagram of TIOL221. The device has an IO-link compatible channel (CQ), a digital output driver (DO) and a digital input (DI) interface. The drivers at CQ and DO can be used in either push-pull, high-side driver (PNP), or low-side driver (NPN) configuration using the CS/PP and SDI/NPN pins in the pin-mode or via the serial peripheral interface (SPI). The internal receiver on the CQ line converts the 24V signal to standard logic levels on the receiver data output pin, RX1. Similarly, internal receiver on the DI line converts the 24V signal to standard logic levels on the receiver data output pin, RX2. A simple parallel interface is used to receive/transmit data and status information between the device and the local controller. The device can be configured by using the pins via pin mode (when SPI/ PIN is tied low) or using the SPI interface (when SPI/ PIN is tied high). By using the SPI interface, the micro controller can read additional diagnostics and status information as well as configure the device. The device has integrated IEC 61000-4-4/5 EFT and surge protection. In addition, tolerance to ±70V transients enables flexibility to choose from a wider range of TVS diodes if an application requires higher levels of protection. These integrated robustness features simplify the system level design by reducing external protection circuitry. TIOL221 transceiver implements protection features for overcurrent, overvoltage and over-temperature conditions. The devices also provide a current-limit setting of the driver output current using an external resistor. The devices derive the low-voltage supply from the IO-Link LP voltage (24V nominal) via an internal linear regulator to provide power to the local controller and sensor circuitry. TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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7.2 Functional Block Diagrams

& CONTROL CONTRO L LOGIC ILIM_ADJ1 CUR_OK1 EN1 TX1 VOUT PWR_OK LP CQ LM TMP_OK1 WU RX1 TIOL221 DIAGNOSTICS & CONTROL CONTRO L LOGIC CUR_OK2 EN2 TX2 DO RX2 LM LPP VOUT DI CONFIG SCK SDI/NPN INT/NFLT1 Rev. Polarity Protection LPP Rev. Polarity Protection ESD & Surge Protection ESD & Surge Protection Integrated Protection ESD & Surge Protection ESD & Surge Protection VOLTAGE REGULATOR LP SPI/PIN LM VSEL V5IN TMP_OK2 CS/PP SDO/NFLT2 NFLT1 NFLT2 RESET NFLT2 ILIM_ADJ2 Figure 7-1. Block Diagram

7.3 Feature Description

7.3.1 Wake-Up Detection

The CQ channel of TIOL221 may be operated in IO-Link mode or Standard Input / Output (SIO) mode. If the CQ channel is in SIO mode, and the IO-link controller node wants to initiate communication with the device node, the controller drives the CQ line to the opposite of the present state. The device either sinks or sources the current ( ≥ 500mA) for the wake-up duration (typically 80 μs) depending on the CQ logic level as per the IO-Link specification. The TIOL221 detects a wake-up condition and communicates to the local microcontroller www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TIOL221 ADVANCE INFORMATION

by asserting the WU pin low for the duration of t WUL. The IO-Link communication specification requires the device node to switch to receive mode within 500μs after receiving the wake-up signal. Table 7-1. Wake-Up Function (tWU1 < t < tWU2) EN1 TX1 CQ CURRENT WAKE COMMENT L / Open X X Asserts low for tWUL Device asserts low for tWUL if RX output changes high- to-low or low-to-high for tWU1 < t < tWU2 H H / Open | I(CQ) | ≥ IO(LIM) mA Asserts low for tWUL Device receives high-level wake-up request over the IO-Link bus H L | I(CQ) | ≥ IO(LIM) mA Asserts low for tWUL Device receives low-level wake-up request over the IO- Link bus For overcurrent conditions shorter or longer than a valid wake-up pulse, the WAKE pin remains in a high- impedance (inactive) state. This is illustrated in Figure 6-6. In the SPI-mode, in addition to the WU asserted low, WU_INT bit is set. Wake-up signaling can be disabled in the SPI-mode by setting the WU_DIS bit to 1b in the DEVICE_CONFIG register. Wake-up detection cannot be disabled in the pin-mode. The DO channel of TIOL221 does not recognize wake-up pulses. The DO pin does provide overcurrent limiting and detection.

7.3.2 Current Limit Configuration

The output current of CQ and DO pins can be configured independently in the pin-mode as well as SPI-mode.

7.3.2.1 Current Limit Configuration in Pin-Mode

In the pin-mode, the current limit of CQ and DO can be configured with an external resistor on the ILIM_ADJ1 and ILIM_ADJ2 pins respectively. The highest current limit setting with an external resistor of 10k Ω provides a minimum of 300mA over the operating temperature and voltage range. Refer to Table 7-2 for the pin-mode configuration of the CQ and DO drivers. Output disable due to current fault and current fault auto recovery features can be disabled by floating ILIM_ADJ1/2 pins. However, the current fault indication is still active in this configuration. This feature is useful when driving large capacitance. When ILIM_ADJ1/2 pins are shorted to ground, the CQ and the DO drivers can configured to be in the IO-link controller mode. In this mode, the drivers can source or sink minimum of 500mA to generate a wake-up request. In addition, drivers enable a small current sink of 5mA (minimum) at the driver output pins. The current fault indication, output disable, and auto recovery features are disabled in this mode. Table 7-2. Current Limit Configuration in Pin-mode ILIM_ADJ1/2 Pin Condition CQ/DO Current Limit (Min.) NFLT1/2 Indication Due to Current Fault Current Fault Blanking Time (tSC) Output Disable and Auto Recovery RSET resistor to L- (10kΩ to 110kΩ) Variable (35mA to 300mA) Yes 200µs (typ) Yes Connected to L- (RSET 0 to 5kΩ) 500mA No N/A No OPEN 260mA Yes None (immediate fault indication) No

7.3.2.2 Current Limit Configuration in SPI mode

In the SPI mode, CQ and DO driver current limit can be configured via SPI. CQ driver can be configured via CQ_CURLIM Register. CQ_CURLIM[7:5] register can be used to configure the current limits. Similarly, DO_CURLIM[7:5] register can be used to configure the current limits for the DO driver. TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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7.3.3 CQ Current Fault Detection, Indication and Auto Recovery

If the output current at CQ exceeds the internally-set current limit I O(LIM) for a duration longer than the current blanking time, tSC, the device detects the condition as an overcurrent fault. In pin-mode, the INT/NFLT1 pin is driven logic low to indicate a fault condition. The output can be set to either turn off (auto-recovery mode) or continue to supply the current until the device enters thermal shutdown. The behavior depends on how the ILIM_ADJ1 pin is connected. See Table 7-2. In the auto-recovery mode, the driver periodically retries to check if the output is still in the over current condition. In this mode, the output is switched on for t SC in t SCEN intervals. Current fault auto retry mode can be disabled by setting ILIM_ADJ1 = OPEN or GND. Current fault blanking time is zero when ILIM_ADJ1=OPEN. See current limit indicator function (t > tSC) for details. In SPI-mode, CQ_CURLIM register settings can be used to configure the CQ driver behavior. CQ_CUR_LIM bits set the current limit whereas the CQ_BL_TIME and CQ_RETRY_TIME set the current fault blanking time and auto-recovery time respectively. CQ_AUTO_RETRY_EN controls the auto-recovery behavior. When the driver is disabled, the current limit indicator is inactive.

7.3.4 DO Current Fault Detection, Indication and Auto Recovery

If the output current at DO exceeds the internally-set current limit I O(LIM) for a duration longer than the current blanking time, tSC, the device detects the condition as an overcurrent fault. In pin-mode, the SDO/NFLT2 pin is driven logic low to indicate a fault condition. The output can be set to either turn off (auto-recovery mode) or continue to supply the current until the device enters thermal shutdown. The behavior depends on how the ILIM_ADJ2 pin is connected. See Table 7-2 In the auto-recovery mode, the driver periodically retries to check if the output is still in the over current condition. In this mode, the output is switched on for t SC in t SCEN intervals. Current fault auto retry mode can be disabled by setting ILIM_ADJ2 = OPEN or GND. Current fault blanking time is zero when ILIM_ADJ2=OPEN. In SPI-mode, DO_CURLIM register settings can be used to configure the DO driver behavior. DO_CUR_LIM bits set the current limit whereas the DO_BL_TIME and DO_RETRY_TIME set the current fault blanking time and auto-recovery time respectively. DO_RETRY_EN controls the auto-recovery behavior. When the driver is disabled, the current limit indicator is inactive. www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TIOL221 ADVANCE INFORMATION

7.3.5 CQ and DI Receivers

RX1 is the output of the CQ receiver. The receiver output is the inverse logic of the CQ input and the receiver function is summarized in Table 7-3. In pin-mode, the CQ receiver is always on. In SPI mode, in addition to the RX1 output, the CQ_RX_LEVEL bit in the STATUS register reflects the logic level of CQ bus input level. In SPI mode, the receiver can be disabled by setting the RX_DIS bit in the CQ_CONFIG register. When the receiver is disabled, RX1 output is in high-impedance and CQ_RX_LEVEL bit in the status register is invalid. Table 7-3. CQ Receiver Function SPI/PIN CQ VOLTAGE RX1 CQ_RX_LEVEL bit COMMENT L or (H && RX_DIS =0) V(CQ) < V(THL) H L Normal receive mode, input low V(THL) < V(CQ) < V(THH) ? ? Indeterminate output, can be either high or low V(THH) < V(CQ) L H Normal receive mode, input high Open ? ? Indeterminate output, can be either high or low H && RX_DIS =1) X Z Z Output is in high-Z RX2 is the output of the DI receiver. The receiver output is the inverse logic of the DI input and the receiver function is summarized in Table 7-3. In pin-mode, the DI receiver is always on. In SPI mode, in addition to the RX2 output, the DI_LEVEL bit in the STATUS register reflects the logic level of DI input. In SPI mode, the receiver can be disabled by setting the DI_DIS bit in the DI_CONFIG register. When the receiver is disabled, RX2 output is in high-impedance and DI_LEVEL bit in the status register is invalid. Table 7-4. DI Receiver Function DI VOLTAGE RX2 DI_LEVEL bit COMMENT V(DI) < V(THL) H L Normal receive mode, input low V(THL) < V(DI) < V(THH) ? ? Indeterminate output, can be either high or low V(THH) < V(DI) L H Normal receive mode, input high Open ? ? Indeterminate output, can be either high or low

7.3.6 Fault Reporting

In the pin mode, NFLT1 pin is driven low if the CQ driver enters overcurrent condition, or if the CQ driver temperature sensor has exceeded T(WRN). NFLT1 returns to high-impedance as soon as both the fault conditions clear. Similarly, NFLT2 pin is driven low if the DO driver enters overcurrent condition, or if the DO driver temperature sensor has exceeded T(WRN). NFLT1 returns to high-impedance as soon as both the fault conditions clear. If the LP supply or the VOUT supply fall below their UVLO thresholds, RESET pin goes low. RESET pin goes high after both LP and VOUT rise above their UVLO thresholds. TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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7.3.6.1 Thermal Warning, Thermal Shutdown

The TIOL221 has three separate thermal sensors: one for each of the driver and another one for the LDO. If the die temperature around the CQ driver exceeds T (WRN), the NFLT1 flag is held low indicating a potential over temperature problem. When the T J exceeds T (SDN), the CQ driver is disabled. The LDO and DO driver remain operational as long as the respective thermal sensors do not exceed T (SDN). As soon as the temperature drops below the temperature threshold (and after T (HYS)), the internal circuit re-enables the driver, subject to the state of the EN1 and TX1 pins. If the die temperature around the DO driver exceeds T (WRN), the NFLT2 flag is held low indicating a potential over temperature problem. When the T J exceeds T (SDN), the DO driver is disabled. The LDO and CQ driver remain operational as long as the respective thermal sensors do not exceed T (SDN). As soon as the temperature drops below the temperature threshold (and after T (HYS)), the internal circuit re-enables the driver, subject to the state of the EN2 and TX2 pins. The thermal sensor near the LDO detects the temperature exceeding the T (SDN). The LDO and both the drivers are turned off and RESET is held low. As soon as the temperature drops below the temperature threshold (and after T(HYS)), the internal circuit re-enables the LDO and the drivers and RESET is released after the VOUT is above the UVLO threshold.

7.3.7 The Integrated Voltage Regulator (LDO)

The TIOL221 has an integrated linear voltage regulator (LDO) which can supply power to external components. The LDO is capable of delivering up to 20mA. LDO output level is configurable via VSEL pin. When VSEL is connected to GND, VOUT is configured to provide a 3.3V output with LP as the input supply. When VSEL is left floating, VOUT provides a 3.3V output, with V5IN as the supply input to reduce the power dissipation in the device. When VSEL is connected to VOUT, VOUT is set to 5V. The VSEL pin status is detected at power-up and VOUT output level is determined and latched until the next power-up cycle. Table 7-5. LDO Output Configuration via VSEL pin VSEL pin connection VOUT Connected to LM 3.3V (supplied from LP) Floating 3.3V (supplied from V5IN) Connected to VOUT 5V When configured for 5V output, the voltage regulator works with input voltage, LP, in the range of 7V to 36V with respect to LM. When configured for 3.3V output, the regulator can work with either V5IN supply (when VSEL is floating) or LP supply (when VSEL is connected to VOUT). Selecting V5IN as the supply input for the 3.3V output on VOUT helps reduce the on-chip power dissipation. When VSEL is set to be floating, if the V5IN supply is not present or below the V5IN_UVLO threshold, the VOUT regulator is shut-off and RESET output is active. The LDO is designed to be stable with standard ceramic capacitors with values of 1 μF or larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR must be less than 1Ω. With tolerance and dc bias effects, the minimum capacitance to make sure stability is 1μF. The voltage regulator has an internal 35mA current limit to protect against initial start up inrush current due to large decoupling capacitors and accidental short circuit conditions.

7.3.8 Reverse Polarity Protection

Reverse polarity protection circuitry protects the devices against accidental reverse polarity connections to the LP, CQ, DO, DI and LM pins. Any combinations of the pins can be connected to DC voltages up to 65V (max). The maximum voltage between any of the pins may not exceed 65V DC at any time. TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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7.3.9 Integrated Surge Protection and Transient Waveform Tolerance

The LP, CQ, DO and DI pins of the device are capable of withstanding up to 1.2kV of 1.2/50 – 8/20 μs IEC 61000-4-5 surge with a source impedance of 500 Ω. The surge testing should be performed with a minimum 100nF supply decoupling capacitor between LP and LM, and 1µF between VOUT and LM. External TVS diodes may be required for higher transient protection levels. The system designer must make sure the maximum clamping voltage of the external diodes is < 65V at the desired current level. The device is capable of withstanding up to ±70V transient pulses < 100µs. Decoupling Network R EUT CQ > 100 nF Combination wave Generator Protection Equipment Auxiliary Equipment 1.2/50 – 8/20µs CWG R = 500Ω Figure 7-4. Surge Test Setup

7.3.10 Undervoltage Lock-Out (UVLO)

The device enters UVLO if either the LP voltage or the VOUT supply fall below their respective UVLO thresholds. As soon as the supplies falls below UVLO thresholds, RESET is pulled low, and the drivers (CQ and DO) are disabled (Hi-Z). Receiver performance is not specified in this mode. When the supplies rise above their rising thresholds, RESET pin goes high. The driver outputs are turned on after t(UVLO) delay. www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TIOL221 ADVANCE INFORMATION

7.3.11 Interrupt Function

The interrupt is used to signal some of the critical events to the microcontroller via the INT pin in the SPI mode. In the SPI mode, INT pin is a push-pull output stage. When an interrupt-generating event takes place, the INT pin is pulled low. Following events can generate interrupt and the corresponding bits are set in the interrupt register:

Thermal Shutdown (TSD_INT)
A valid wake-up pulse received on CQ (WU_INT)
DO output overcurrent fault (DO_FAULT_INT)
DO output overcurrent fault (CQ_FAULT_INT)
LP falls below warning threshold (LPW_INT)
V5IN falls below UVLO threshold (UV_V5_INT)
Temperature reached above the thermal warning threshold (TEMP_WARN) Individual interrupt events can be masked via INT_MASK register. When an interrupt is masked, that particular event does not activate the INT pin. However, interrupt bit is set if the interrupt generating event occurs. The interrupt bits are not cleared automatically when the interrupt generating event is no longer present. The interrupt bit needs to be cleared explicitly by the microcontroller. The INT pin goes high when all interrupt bits are cleared by the MCU (cleared on read) and the event does not persist. INT pin also goes high if all the interrupt bits are masked. If the interrupt bits are unmasked and if any of the interrupt bits are still set, the INT pin goes low again. TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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7.4 Device Functional Modes

These device can operate in two modes: pin mode or SPI mode. When the SPI/PIN pin is low, the device operates in pin mode. When the SPI/PIN pin is high, the device operates in SPI mode. The CQ driver control in either of the modes is described in Table 7-6. The DO driver control is described in Table 7-7. Additionally, if using SPI mode, both CQ and DO driver can be connected together to drive higher load currents. The settings for this configuration is described in Table 7-8 and CQ and DO Tracking mode . The recommended is to have the drivers in disabled state before changing the driver configuration settings including the driver modes, current limits and overcurrent blanking time. Table 7-6. CQ Control SPI/PIN EN1 TX1 CQ_TX_MODE = 11 (CQ Disabled) CQ_Q NPN Mode PNP Mode Push-Pull Mode L L/Open L X X Z Z Z H X X Z Z Z H L X X Z H H H X X L Z L H L L 0 0 Z Z Z H Z Z Z L 1 Z H H H Z H H H L 0 Z H H H L Z L L 1 Z H H H Z H H X X 1 X Z Z Z Table 7-7. DO Control When DO and CQ are set to track (DO_CQ_TRACK set to 1b, DO driver follows the CQ configuration and the DO configuration is ignored, including the driver modes, current limits and driver settings. SPI/PIN EN2 TX2 DO_MODE=11 (DO disabled) DO_Q NPN Mode PNP Mode Push-Pull Mode L L/Open L X X Z Z Z H X X Z Z Z H L X X Z H H H X X L Z L H L L Z Z Z H Z Z Z L Z H H H Z H H H L Z H H H L Z L L Z H H H Z H H X X 1 X Z Z Z www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TIOL221 ADVANCE INFORMATION

Table 7-8. DO Control (When DO_CQ_TRACK = 1b) When DO and CQ are set to track (DO_CQ_TRACK set to 1b, DO driver follows the CQ configuration and the DO configuration is ignored, including the driver modes, current limits and driver settings. SPI/PIN DO_CQ_TR ACK=1b EN2/TX2/ DO_MODE/ DO_CQ EN1 TX1 CQ_TX_MO DE=11 (CQ disabled) CQ_Q NPN Mode (Per CQ COnfig) PNP Mode (Per CQ COnfig) Push-Pull Mode (Per CQ COnfig) H 1b X L L Z Z Z H Z Z Z L Z H H H Z H H H L Z H H H L Z L L Z H H H Z H H X X 1 X Z Z Z Table 7-9. NPN, PNP and Push-Pull Mode Selection in Pin-Mode SPI/PIN CS/PP SDI/NPN CQ and DO Driver Mode L L L PNP L H NPN H X Push-Pull H X X CQ and DO driver modes selected via SPI interface

7.4.1 CQ and DO Tracking mode

In SPI mode, CQ and DO output drivers can be set to sync with each using only the TX1 as the input and EN1 as the enable pin using the DO_CQ_TRACK bit setting. When this bit is enabled, both the drivers take TX1 as the input and are controlled by the EN1 enable pin. The following configurations go into effect when the DO_CQ_TRACK bit is set:

DO configuration settings are ignored and CQ configuration settings (overcurrent, blanking time, auto re-try, CQ_Qimpact both the drivers
TX2 and EN2 input pins are ignored
If one of the drivers go into overcurrent or thermal faults, both the drivers are turned-off. – The interrupt and status bits of only the driver that go into the fault condition are set

7.5 SPI Programming

When SPI/PIN is tied high, TIOL221 is in SPI mode. The SPI communication uses a standard SPI. Physically the digital interface pins are CS /PP (Chip select active-low), SDI/NPN (SPI Data In), SDO/NFLT2 (SPI Data Out) and SCK (SPI Clock). Each SPI transaction is initiated by a seven bit address with a R/W bit. The data shifted out on the SDO pin for the transaction always starts with the register 8'h01[7:0] which is the status register. This register provides the high-level status information about the device. The data byte which are the ‘response’ to the address and R/W byte are shifted out next. See Figure 7-5 and Figure 7-6 for SPI read and write frame diagrams for non-burst mode. See Figure 7-7 and Figure 7-8 for SPI read and write frame diagrams for burst mode. The SPI controller must generate clock and data signals in SPI MODE0 (clock polarity CPOL = 0 and clock phase CPHA = 0) to communicate with TIOL221. The SPI data input data on SDI is sampled on the low to high edge of SCK. The SPI output data on SDO is changed on the high to low edge of SCK. TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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= 1 h’01[7:0] Status Register SCK SDI ADDRESS [6:0] Previous DATA[7:0] from Address [6:0] Previous DATA[7:0] from Address [6:0] +1 DATA[7:0] For Address [6:0] DATA[7:0] for Address [6:0] +1 Figure 7-8. SPI Write (Burst mode) TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

When TIOL221 is connected to an IO-Link controller through a three or four wire interface ( Figure 8-1 ), the controller can initiate communication and exchange data with a remote node with the TIOL221 IO-Link transceiver acting as a complete physical layer for the communication.

8.2 Typical Application

ILIM_ADJ1 EN1 TX1 VOUT CQ LM WU RX1 ILIM_ADJ2 EN2 TX2 DO RX2 DI SCK SDI/NPN INT/NFLT1 LP SPI/PIN CS /PP Buck Regulator GND CQ DO V5IN SDO/NFLT2 Microcontroller VCC 3.3 V VSEL GND GND GND RESET R VOUT R VOUT Figure 8-1. Typical Application Schematic (SPI Mode) www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TIOL221 ADVANCE INFORMATION

8.2.1 Design Requirements

TIOL221 IO-Link transceiver can be used to communicate using the IO-Link protocol, or as standard digital outputs to either sense or drive a wide range of sensors and loads. Table 8-1 shows recommended components for a typical system design. Table 8-1. Design Parameters PARAMETERS Design Requirement TIOL221 Specification Input voltage range (LP) 24V (typ), 30V (max) 7V to 36V Output current (CQ) 200mA Choose 250mA limit with RSET1 = 27kΩ LDO Output voltage 5V VOUT = 5V By connecting VSEL=VOUT LDO output current 5mA I(VOUT): Up to 20mA Pull-up resistors for NFLT1, NFLT2 and WU 10kΩ 10kΩ LP decoupling capacitor 0.1µF / 100V 0.1µF / 100V VOUT output capacitor 1µF / 10V 1µF / 10V Maximum Ambient Temperature, TA 105°C TIOL221 can support up to TA of 125 °C if TJ < T(SDN) TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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8.2.2 Detailed Design Procedure

8.2.2.1 Driving Capacitive Loads

These devices are capable of driving capacitive loads on the CQ and DO outputs. Assuming a pure capacitive load without series/parallel resistance, the maximum capacitance that can be charged without triggering current fault can be calculated as: SCO LIM LOAD L I x [ ] t C V (1) To drive higher capacitive loads and avoid overcurrent condition disabling the driver, the recommendation is to leave the corresponding ILIM_ADJx pin floating. With ILIM_ADJx pin floating, TIOL221 indicates overcurrent fault without blanking time delay (t SC) but does not disable the driver. Another approach is to drive high capacitive loads with a series resistor between the CQ output and the load to avoid overcurrent condition. Capacitive loads can be connected to LM or LP.

8.2.2.2 Driving Inductive Loads

The TIOL221 is capable of magnetizing and demagnetizing large inductive loads. These devices contain internal circuitry that enables fast and safe demagnetization when configured as either P-switch or N-switch mode. In P-switch configuration, the load inductor L is magnetized when the driver (CQ or DO) output is driven high. When the PNP is turned off, there is a significant amount of negative inductive kick back at the driver output pin. This voltage is safely clamped internally at about −15V. Similarly, in N-switch configuration, the load inductor L is magnetized when the driver output is driven low. When the NPN is turned off, there is a significant amount of positive inductive kick back at the driver output pin. This voltage is safely clamped internally at about 15V. The equivalent protection circuits are shown in Figure 8-3 and Figure 8-4. The minimum value of the resistive load R can be calculated as: L )O LIM ( V R I (2) L R CQ L+Rev. Polarity Protection Rev. Polarity Protection ESD and Surge Protection ESD and Surge Protection Figure 8-3. P-Switch Mode L R CQ L+Rev. Polarity Protection Rev. Polarity Protection ESD and Surge Protection ESD and Surge Protection L- Figure 8-4. N-Switch Mode

8.3 Power Supply Recommendations

The TIOL221 transceiver is designed to operate from a 24V nominal supply at LP, which can vary by +12V and -17V from the nominal value to remain within the device recommended supply voltage range of 7V to 36V. This supply should be buffered with at least a 100nF/100V capacitor. www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TIOL221 ADVANCE INFORMATION

8.4 Layout

8.4.1 Layout Guidelines

Use of a 4-layer board is recommended for good heat conduction. Use layer 1 (top layer) for control signals, layer 2 as power ground layer for LM, layer 3 for the 24V supply plane (LP), and layer 4 for the regulated output supply (VOUT).
Connect the thermal pad to LM with maximum amount of thermal vias for best thermal performance.
Use entire planes for LP, VOUT and LM for minimum inductance.
The LP terminal must be decoupled to ground with a low-ESR ceramic decoupling capacitor. The recommended minimum capacitor value is 100nF. The capacitor must have a voltage rating of 50V minimum (100V depending on max sensor supply fault rating) and an X5R or X7R dielectric.
The optimum placement of the capacitor is closest to the transceiver’s LP and LM terminals to reduce supply drops during large supply current loads. See Figure 8-5 for a PCB layout example.
Connect all open-drain control outputs via 10kΩ pull-up resistors to the VOUT plane to provide a defined voltage potential to the system controller inputs when the outputs are high-impedance.
If using pin mode, connect the RSET resistor between ILIM_ADJ1/2 and LM, as needed
Decouple the regulated output voltage at VOUT to ground with a low-ESR, ≥ 1μF, ceramic decoupling capacitor. The capacitor should have a voltage rating of 10V minimum and an X5R or X7R dielectric.

8.4.2 Layout Example

ILIM_ADJ2 SCK to MCU ILIM_ADJ1 RPU To MCU RPU To Connector To Connector DO/DI Via to VOUT Via to GND Via to LP Figure 8-5. Layout Example (SPI mode shown) TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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9 TIOL221 Registers

Table 9-1 lists the memory-mapped registers for the TIOL221 registers. All register offset addresses not listed in Table 9-1 should be considered as reserved locations and the register contents should not be modified. Table 9-1. TIOL221 Registers Address Acronym Register Name Section 0h INT Interrupt Go 1h STATUS Status Go 2h DEVICE_CONFIG Device Configuration Go 3h CQ_CURLIM CQ Driver Ccurrent Limit Go 4h CQ_CONFIG CQ Configration Go 5h DIO_CONFIG DIO Configuration Go 6h DO_CURLIM DO Driver current limit Go 7h DEVICE_ID Device ID Go 8h INT_MASK Interrupt Mask Go 9h RESET_CONFIG Reset pin configuration register Go Complex bit access types are encoded to fit into small table cells. Table 9-2 shows the codes that are used for access types in this section. Table 9-2. TIOL221 Access Type Codes Access Type Code Description Read Type R R Read RC R C Read to Clear Write Type W W Write Reset or Default Value -n Value after reset or the default value www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TIOL221 ADVANCE INFORMATION

9.1 INT Register (Address = 0h) [Reset = 00h]

INT is shown in Figure 9-1 and described in Table 9-3. Return to the Summary Table. Interrupt registers reflect current status of various fault conditions. Interrupt registers are not cleared automatically after the fault clears. They are cleared on read if the fault condition does not exist Figure 9-1. INT Register 7 6 5 4 3 2 1 0 TSD_INT WU_INT DO_FAULT_IN T CQ_FAULT_IN T LPW_INT RESERVED UV_V5_INT TEMP_WARN RC-0b RC-0b RC-0b RC-0b RC-0b R-0b RC-0b RC-0b Table 9-3. INT Register Field Descriptions Bit Field Type Reset Description 7 TSD_INT RC 0b Thermal shutdown interrupt bit. This bit is not cleared automatically when the fault is cleared. The bit is cleared on read if the fault does not exist anymore 0b = The device is not in thermal shutdown 1b = The device has entered thermal shutdown 6 WU_INT RC 0b This bit is set when an IO-link wake-up condition is detected on CQ. 0b = No wake-up detected 1b = Wake-up detected

5 DO_FAULT_INT RC 0b This bit is set when DO driver fault occurs (overcurrent or thermal)

0b = No fault on DO driver 1b = DO driver fault has occured

4 CQ_FAULT_INT RC 0b This bit is set when CQ driver fault occurs (overcurrent or thermal)

0b = No fault on CQ driver 1b = CQ driver fault has occured

3 LPW_INT RC 0b This bit is set when LP goes below the warning threshold

0b = LP above the warning threshold 1b = LP below the warning threshold

2 RESERVED R 0b Reserved

1 UV_V5_INT RC 0b Undervoltage on the V5IN supply input

0b = No UV fault on V5IN 1b = UV fault on V5IN

0 TEMP_WARN RC 0b Thermal warning interrupt

0b = No thermal warning 1b = Thermal warning limit reached TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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9.2 STATUS Register (Address = 1h) [Reset = 00h]

STATUS is shown in Figure 9-2 and described in Table 9-4. Return to the Summary Table. Status registers reflect current status of various fault conditions. They are read-only and cleared automatically when the fault is cleared. Note: Soft reset does not reset the STATUS register bits as they reflect the current status of the faults. It is recommended to read the MSB byte when reading the STATUS register because the POR recovery bit is cleared by the time LSB byte is transferred to data output Figure 9-2. STATUS Register 7 6 5 4 3 2 1 0 POR_RECOVE RY TSD DI_LEVEL DO_FAULT CQ_FAULT UV_V5 CQ_RX_LEVEL TEMP_WARN RC-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b Table 9-4. STATUS Register Field Descriptions Bit Field Type Reset Description 7 POR_RECOVERY RC 0b The bit is set when the device recovers from POR event. The bit is cleared on read 0b = The device is operating normally 1b = The device has recovered from POR event 6 TSD R 0b The bit reflects the status of thermal shutdown. The bit is automatically cleared when temperature falls below thermal shutdown threshold 0b = No thermal shutdown 1b = Part in thermal shutdown

5 DI_LEVEL R 0b This bit is set when DI voltage is logic high and cleared when DI

voltage is logic low Note: This bit is invalid if DI_DIS bit is set to 1. 0b = 0x0 1b = 0x1

4 DO_FAULT R 0b The bit reflects the status of DO drive fault

0b = No fault at DO pin 1b = Fault at DO pin

3 CQ_FAULT R 0b This bit reflects the status of the CQ driver fault

0b = No fault at CQ pin 1b = Fault at CQ pin

2 UV_V5 R 0b This bit reflects the status of the UV condition at the V5IN pin

0b = V5IN voltage above UVLO threshold 1b = V5IN below UVLO threshold

1 CQ_RX_LEVEL R 0b This bit is set when CQ voltage is logic high and cleared when CQ

voltage is logic low. Note: This bit is invalid if CQ_RX_DIS bit is set to 1. 0b = 0x0 1b = 0x1

0 TEMP_WARN R 0b Shows the status of the device temperature above or below the

temperature warning threshold 0b = No temprature warning 1b = Device temperature is above the warning threshold www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TIOL221 ADVANCE INFORMATION

9.3 DEVICE_CONFIG Register (Address = 2h) [Reset = 00h]

DEVICE_CONFIG is shown in Figure 9-3 and described in Table 9-5. Return to the Summary Table. Device level configuration registers Figure 9-3. DEVICE_CONFIG Register 7 6 5 4 3 2 1 0 SOFT_RESET WU_DIS DO_CQ_TRAC K IOLINK_5MA_P D DI_RX_FILTER CQ_RX_FILTE R T_UVLO INT_TOG R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b Table 9-5. DEVICE_CONFIG Register Field Descriptions Bit Field Type Reset Description 7 SOFT_RESET R/W 0b Resets all registers to their defaults. Note: The status and interrupt bits may still be set depending upon the corresponding fault status. 0b = No reset 1b = Resets the deive configuration

6 WU_DIS R/W 0b 0b = CQ can recognize wake-up pulse

1b = CQ ignores the wake-up pulse

5 DO_CQ_TRACK R/W 0b If the bit is set, DO and CQ drivers both track together as a function

of the TX input and CQ_CONFIG setting. 0b = DO and CQ drivers are independent 1b = DO and CQ drivers track as a function of the TX input

4 IOLINK_5MA_PD R/W 0b Enables 5mA pull-down current ILLM at both CQ and DO drivers

when the respective driver is disabled. Note: CQ_CUR_LIM and DO_CUR_LIM limit needs to be set to 500mA to enable this respectivly at CQ and DO. 0b = 5mA (min) pull-down current disabled 1b = 5mA (min) pull-down current enabled when the respective driver is disabled

3 DI_RX_FILTER R/W 0b Turns on or off the RX glitch filter on the DI line

0b = DI glitch filter disabled 1b = DI glitch filter enabled

2 CQ_RX_FILTER R/W 0b Turns on or off the RX glitch filter on the CQ line

0b = CQ RX glitech filter disabled 1b = CQ RX glitch filter enabled

1 T_UVLO R/W 0b UVLO auto-recovery time

0b = 0.5 ms (typ) 1b = 30 ms (typ)

0 INT_TOG R/W 0b Enables interrupt pin toggling

0b = Interrupt pin set to active low 1b = Interrupt pin set to toggle with 200us period and 50% duty cycle TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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9.4 CQ_CURLIM Register (Address = 3h) [Reset = 20h]

CQ_CURLIM is shown in Figure 9-4 and described in Table 9-6. Return to the Summary Table. CQ Driver current limit and auto-retry configuration Figure 9-4. CQ_CURLIM Register 7 6 5 4 3 2 1 0 CQ_CUR_LIM CQ_BL_TIME CQ_RETRY_TIME CQ_AUTO_RE TRY_EN R/W-001b R/W-00b R/W-00b R/W-0b Table 9-6. CQ_CURLIM Register Field Descriptions Bit Field Type Reset Description 7-5 CQ_CUR_LIM R/W 001b Sets current limits 000b = 35 mA (min) 001b = 50 mA (min) 010b = 100 mA (min) 011b = 150 mA (min) 100b = 200 mA (min) 101b = 250 mA (min) 110b = 300 mA (min) 111b = 500 mA (min) 4-3 CQ_BL_TIME R/W 00b Sets current blanking time 00b = 200 µs (typ) 01b = 500 µs (typ) 10b = 5 ms (typ) 11b = 0 s (no blanking time) 2-1 CQ_RETRY_TIME R/W 00b Sets auto re-try time 00b = 50 ms (typ) 01b = 100 ms (typ) 10b = 200 ms (typ) 11b = 500 ms (typ) 0 CQ_AUTO_RETRY_EN R/W 0b Enable auto re-try. When enabled the driver gets disabled after blanking time and re-enabled after the retry time. When auto retry is disabled, the driver stays enabled and shut off only after thermal shutdown NOTE: It is not recommended to enable auto retry when blanking time is configured to 2b11 (no blanking time) . 0b = Disabled 1b = Enabled www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TIOL221 ADVANCE INFORMATION

9.5 CQ_CONFIG Register (Address = 4h) [Reset = 0Ch]

CQ_CONFIG is shown in Figure 9-5 and described in Table 9-7. Return to the Summary Table. CQ configration registers for PNP/NPN modes and weak pull-up/down Figure 9-5. CQ_CONFIG Register 7 6 5 4 3 2 1 0 RESERVED CQ_WEAK_PD _EN CQ_WEAK_PU _EN CQ_TX_MODE CQ_Q RX_DIS R-0b R/W-0b R/W-0b R/W-11b R/W-0b R/W-0b Table 9-7. CQ_CONFIG Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0b Reserved

5 CQ_WEAK_PD_EN R/W 0b Configures the weak pull-down on CQ when the driver is disabled

0b = Weak pull-down disabled 1b = Weak pull-down enabled

4 CQ_WEAK_PU_EN R/W 0b Configures the weak pull-up on CQ when the driver is disabled

0b = Weak pull-up disabled 1b = Weak pull-up enabled 3-2 CQ_TX_MODE R/W 11b Configures the driver transmission mode 00b = PNP mode 01b = Push-pull mode 10b = NPN mode 11b = Driver disabled

1 CQ_Q R/W 0b CQ driver output logic

0b = CQ is in high-impedance when EN1 is low (or CQ_DIS is low) 1b = CQ driver outputs logic high in push-pull or PNP mode and is turned-off in NPN mode

0 RX_DIS R/W 0b Configures the RX of the CQ line

0b = RX is enabled 1b = RX is disabled TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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9.6 DIO_CONFIG Register (Address = 5h) [Reset = 0Ch]

DIO_CONFIG is shown in Figure 9-6 and described in Table 9-8. Return to the Summary Table. Figure 9-6. DIO_CONFIG Register 7 6 5 4 3 2 1 0 DI_WEAK_PD_ EN DI_WEAK_PU_ EN DO_WEAK_PD _EN DO_WEAK_PU _EN DO_MODE DO_Q DI_DIS R/W-0b R/W-0b R/W-0b R/W-0b R/W-11b R/W-0b R/W-0b Table 9-8. DIO_CONFIG Register Field Descriptions Bit Field Type Reset Description

7 DI_WEAK_PD_EN R/W 0b Configures the weak pull-down on DI

0b = Weak pull-down disabled 1b = Weak pull-down enabled

6 DI_WEAK_PU_EN R/W 0b Configures the weak pull-up on DI

0b = Weak pull-up disabled 1b = Weak pull-up enabled

5 DO_WEAK_PD_EN R/W 0b Configures the weak pull-down on DO when the driver is disabled

0b = Weak pull-down disabled 1b = Weak pull-down enabled

4 DO_WEAK_PU_EN R/W 0b Configures the weak pull-up on DO when the driver is disabled

0b = Weak pull-up disabled 1b = Weak pull-up enabled 3-2 DO_MODE R/W 11b Configures the DO driver transmission mode 00b = PNP mode 01b = Push-pull mode 10b = NPN mode 11b = Driver disabled

1 DO_Q R/W 0b DO driver output logic

0b = DO is in high-impedance when EN2 is low (or DO_DIS is low) 1b = DO driver outputs logic high in push-pull or PNP mode and is turned-off in NPN mode

0 DI_DIS R/W 0b Configures the DI receiver

0b = DI is enabled 1b = DI is disabled www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TIOL221 ADVANCE INFORMATION

9.7 DO_CURLIM Register (Address = 6h) [Reset = 20h]

DO_CURLIM is shown in Figure 9-7 and described in Table 9-9. Return to the Summary Table. DO Driver current limit and auto-retry configuration Figure 9-7. DO_CURLIM Register 7 6 5 4 3 2 1 0 DO_CUR_LIM DO_BL_TIME DO_RETRY_TIME DO_RETRY_E N R/W-001b R/W-00b R/W-00b R/W-0b Table 9-9. DO_CURLIM Register Field Descriptions Bit Field Type Reset Description 7-5 DO_CUR_LIM R/W 001b Sets current limits 000b = 35 mA (min) 001b = 50 mA (min) 010b = 100 mA (min) 011b = 150 mA (min) 100b = 200 mA (min) 101b = 250 mA (min) 110b = 300 mA (min) 111b = 500 mA (min) 4-3 DO_BL_TIME R/W 00b Sets current blanking time. NOTE: It is not recommended to configure 0b11 (no blanking time) when Auto retry is enabled. 00b = 200 µs (typ) 01b = 500 µs (typ) 10b = 5 ms (typ) 11b = 0 s (no blanking time) 2-1 DO_RETRY_TIME R/W 00b Sets auto re-try time NOTE: It is not recommended to enable auto retry when blanking time is configured to 2b11 (no blanking time) . 00b = 50 ms (typ) 01b = 100 ms (typ) 10b = 200 ms (typ) 11b = 500 ms (typ)

0 DO_RETRY_EN R/W 0b Enable auto re-try

0b = Disabled 1b = Enabled TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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9.8 DEVICE_ID Register (Address = 7h) [Reset = 01h]

DEVICE_ID is shown in Figure 9-8 and described in Table 9-10. Return to the Summary Table. Figure 9-8. DEVICE_ID Register 7 6 5 4 3 2 1 0 R-0b R-001b Table 9-10. DEVICE_ID Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R 0b Reserved 001b = 1st revision www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TIOL221 ADVANCE INFORMATION

9.9 INT_MASK Register (Address = 8h) [Reset = 00h]

INT_MASK is shown in Figure 9-9 and described in Table 9-11. Return to the Summary Table. Interrupt masking registers. When an interrupt is masked, the interrupt pin does not indicate the interrupt but the interrupt register is still updated to indicate the interrupt. Figure 9-9. INT_MASK Register 7 6 5 4 3 2 1 0 TSD_INT_MAS K WU_INT_MASK DO_FAULT_IN T_MASK CQ_FAULT_IN T_MASK LPW_INT_MAS K RESERVED UV_V5_INT_M ASK TEMP_WARN_ MASK R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b R-0b R/W-0b R/W-0b Table 9-11. INT_MASK Register Field Descriptions Bit Field Type Reset Description

7 TSD_INT_MASK R/W 0b 0b = Interrupt active

1b = Interrupt masked

6 WU_INT_MASK R/W 0b 0b = Interrupt active

1b = Interrupt masked

5 DO_FAULT_INT_MASK R/W 0b 0b = Interrupt active

1b = Interrupt masked

4 CQ_FAULT_INT_MASK R/W 0b 0b = Interrupt active

1b = Interrupt masked

3 LPW_INT_MASK R/W 0b 0b = Interrupt active

1b = Interrupt masked

1 UV_V5_INT_MASK R/W 0b 0b = Interrupt active

1b = Interrupt masked

0 TEMP_WARN_MASK R/W 0b 0b = Interrupt active

1b = Interrupt masked TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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9.10 RESET_CONFIG Register (Address = 9h) [Reset = 00h]

RESET_CONFIG is shown in Figure 9-10 and described in Table 9-12. Return to the Summary Table. Configures the behavior of the RESET pin Figure 9-10. RESET_CONFIG Register 7 6 5 4 3 2 1 0 RESET_SEL RESET_POL RESERVED R/W-00b R-0b R-0b Table 9-12. RESET_CONFIG Register Field Descriptions Bit Field Type Reset Description 7-6 RESET_SEL R/W 00b Selects the what events will activate the reset output 00b = Both UVLP and UVOUT 01b = UVLP 10b = UVOUT 11b = Reserved

5 RESET_POL R 0b Selects between active low and active high configuration for reset

0b = Pin output low (active-low) 1b = Pin output high (active-high) 4-0 RESERVED R 0b Reserved www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: TIOL221 ADVANCE INFORMATION

10 Device and Documentation Support

10.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. DATE REVISION NOTES September 2024 * Initial release

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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12.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: TIOL221 ADVANCE INFORMATION

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TIOL221RGER VQFN RGE 24 5000 360.0 360.0 36.0 TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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12.2 Mechanical Data

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in pa renthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circu it board for thermal and mechanical performance. PACKAGE OUTLINE www.ti.com 4219016 / A 08/2017 VQFN - 1 mm max height PLASTIC QUAD FLATPACK- NO LEAD RGE0024H A 0.08 C

0.1 C A B

0.05 C B SYMM SYMM 4.1 3.9 4.1 3.9PIN 1 INDEX AREA

1 MAX

0.05 0.00 SEATING PLANE C 2X 2.5 2.7±0.1 2.5 20X 0.5 7 12 1924 24X 0.30 0.18 24X 0.48 0.28 (0.2) TYP PIN 1 ID (OPTIONAL) www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: TIOL221 ADVANCE INFORMATION

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad o n the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Solder mask tolerances between and around signal pads can vary b ased on board fabrication site. EXAMPLE BOARD LAYOUT 4219016 / A 08/2017 www.ti.com VQFN - 1 mm max heightRGE0024H PLASTIC QUAD FLATPACK- NO LEAD SYMM SYMM LAND PATTERN EXAMPLE SCALE: 20X (1.1) 2X(1.1) (3.825) (3.825) ( 2.7) 7 12 1924 24X (0.58) 24X (0.24) 20X (0.5) (R0.05) (Ø0.2) VIA TYP SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

0.07 MAX

0.07 MIN

SLLSFS6 – SEPTEMBER 2024 www.ti.com

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NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.. EXAMPLE STENCIL DESIGN 4219016 / A 08/2017 www.ti.com VQFN - 1 mm max heightRGE0024H PLASTIC QUAD FLATPACK- NO LEAD SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 78% PRINTED COVERAGE BY AREA SCALE: 20X (3.825) (3.825) (0.694) TYP (0.694) TYP 4X ( 1.188) 7 12 1924 24X (0.24) 24X (0.58) 20X (0.5) (R0.05) TYP METAL TYP www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: TIOL221 ADVANCE INFORMATION

www.ti.com PACKAGE OUTLINE C0.4 MAX0.170.11

2 TYP

25X 0.250.210.5 TYP0.5 TYP B E A D 4229752/A 06/2023 D: Max = 2.720 mm, Min = 2.680 mm DSBGA - 0.4 mm max heightYAH0025-C01DIE SIZE BALL GRID ARRAY E: Max = 2.720 mm, Min = 2.680 mm BALL A1CORNER SEATING PLANE0.05C A120.015CAB SYMM SYMM BCDE 345 SCALE 6.000 TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

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www.ti.com EXAMPLE BOARD LAYOUT 0.05 MIN0.05 MAX 25X (0.23)(0.5) TYP(0.5) TYP (0.23)SOLDER MASKOPENING(0.23)METAL 4229752/A 06/2023 DSBGA - 0.4 mm max heightYAH0025-C01DIE SIZE BALL GRID ARRAY SOLDER MASK DETAILSNOT TO SCALE SYMM SYMM 12AB EXPOSED METAL SHOWNLAND PATTERN EXAMPLESCALE: 30X CDE NON-SOLDER MASKDEFINED(PREFERRED)EXPOSEDMETALSOLDER MASKOPENINGSOLDER MASKDEFINED METAL UNDERSOLDER MASKEXPOSEDMETAL www.ti.com TIOL221 SLLSFS6 – SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: TIOL221 ADVANCE INFORMATION

www.ti.com EXAMPLE STENCIL DESIGN (0.5) TYP (0.5) TYP25X (0.25)(R0.05) TYP 4229752/A 06/2023 DSBGA - 0.4 mm max heightYAH0025-C01DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLEBASED ON 0.075 mm THICK STENCILSCALE: 30X METALTYP 12AB 3 CDE TIOL221 SLLSFS6 – SEPTEMBER 2024 www.ti.com

Product Folder Links: TIOL221 ADVANCE INFORMATION

www.ti.com 13-Sep-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTIOL221RGER ACTIVE VQFN RGE 24 5000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2024, Texas Instruments Incorporated

Selected Specification

Texas Instruments PTIOL221RGER overview.

Overview

PTIOL221RGER is listed in the Power Management category. Available datasheets include documents from Texas Instruments. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

TIOL221 Dual Channel IO-Link Device PHY with Integrated LDO and SPI Interface SEPTEMBER 2024

Description

TIOL221 Dual Channel IO-Link Device PHY with Integrated LDO and SPI Interface SEPTEMBER 2024

Source title PTIOL221RGER Datasheet(PDF) - Texas Instruments

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