PT7C4337WE

PT7C4337 ETC2

Document overview

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Technical content

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Product Features

• Using external 32.768kHz quartz crystal
• Supports I2C-Bus's high speed mode (400 kHz)
• Includes time (Hour/Minute/Second) and calendar (Year/Month/Date/Day) counter functions (BCD code)
• Programmable square wave output signal
• Two Time-of-Day Alarms
• Oscillator Stop Flag
• Operating range: 1.8V to 5.5V

Ordering Information

PT7C4337PE Lead free 8-Pin DIP PT7C4337WE Lead free 8-Pin SOIC PT7C4337UE Lead free 8-Pin MSOP Product Description The PT7C4337 serial real-time clock is a low-power clock/calendar with two programmable time-of-day alarms and a programmable square-wave output. Address and data are transferred serially via a 2-wire, bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. Table 1 shows the basic functions of PT7C4337. More details are shown in section: overview of functions. Table 1. Basic functions of PT7C4337

1 Oscillator

3 Alarm interrupt √ 2

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus)

Contents

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Pin Assignment Pin Description Pin no. Pin Type Description 1 X1 I Oscillator Circuit Input. Together with X2, 32.768kHz crystal is connected between them. Or external clock input. 2 X2 O Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between them. When 32.768kHz external input, X2 must be float. 6 SCL I Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface. 5 SDA I/O Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The SDA pin is open-drain output and requires an external pull-up resistor. 3 INTA O Interrupt Output. When enabled, INTA is asserted low when the time matches the values set in the alarm registers. This pin is an open-drain output and requires an external pull up resistor. 7 SQW/INTB O Square-Wave/Interrupt Output. Programmable square-wave or interrupt output signal. It is an open-drain output and requires an external pull up resistor. 8 VCC P Power. 4 GND P Ground. INTA GND VCC SQW/INTB SCL 6 4 5SDA PT7C4337

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Function Block Recommended Layout for Crystal Crystal Specifications Parameter Symbol Min Typ Max Unit Nominal Frequency f O - 32.768 - kHz Series Resistance ESR - - 45 kΩ Load Capacitance C L - 12.5 - pF The crystal, traces and crystal input pins should be isolated from RF generating signals. Time Counter (Sec,Min,Hour,Day,Date,Month,Year) Interrupt Control Square Wave Output Control Comparator 1 Alarm 2 Register (Min, Hour, Day/Date)Comparator 2 Alarm 1 Register (Sec, Min, Hour, Day/Date) Shift Register Address Decoder Address Register INTA SQW/INTB SCL SDA PT7C4337 OSC CD CG 32.768 kHz Control Register Counter Chain I /O Interface (I2C) L)[ $SZTUBM PT7C4337 Guard Ring (connect to gound) Local Ground plane Layer 2

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Function Description Overview of Functions Clock function CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) ye ar that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100. Alarm function This device has two alarm system (Alarm 1 and Alarm 2) that outputs interrupt signals from INTA or INTB to CPU when the date, day of the week, hour, minute or second correspond to the setting. Each of them may output interrupt signal separately at a specified time. The alarm is be selectable between on and off for matching alarm or repeating alarm. Programmable square wave output Interface with CPU Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data). Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is also open drain. The SCL's maximum clock frequency is 400 kHz, which supports the I2C bus's high-speed mode. Oscillator fail detect When oscillator fail, PT7C4337 OSF bit will be set. Oscillator enable/disable Oscillator and time count chain can be enabled or disabled at the same time by /ETIME bit.

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Registers Allocation of registers Register definition Addr. (hex)*1 Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00 Seconds (00-59) 0 S40 S20 S10 S8 S4 S2 S1

01 Minutes (00-59) 0 M40 M20 M10 M8 M4 M2 M1

02 Hours (00-23 / 01-12) 0 12, /24 H20 or

P, /A H10 H8 H4 H2 H1

03 Days of the week (01-07) 0 0 0 0 0 W4 W2 W1

04 Dates (01-31) 0 0 D20 D10 D8 D4 D2 D1

05 Months (01-12) Century 0 0 MO10 MO8 MO4 MO2 MO1

06 Years (00-99) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1

07 Alarm 1: Seconds A1M1 *2 S40 S20 S10 S8 S4 S2 S1

08 Alarm 1: Minutes A1M2 *2 M40 M20 M10 M8 M4 M2 M1

09 Alarm 1: Hours A1M3 *2 12, /24 H20 or

P, /A H10 H8 H4 H2 H1 0A Alarm 1: Day, Date A1M4 *2 Day, /Date D20 D10 W4, W2, W1, 0B Alarm 2: Minutes A2M2 *3 M40 M20 M10 M8 M4 M2 M1 0C Alarm 2: Hours A2M3 *3 12, /24 H20 or P, /A H10 H8 H4 H2 H1 0D Alarm 2: Day, Date A2M4 *3 Day, /Date D20 D10 W4, W2, W1, 0E Control /ETIME *4 0 0 RS2 *5 RS1 *5 INTCN *6 A2IE *7 A1IE *7 0F Status OSF *9 0 0 0 0 0 A2F *8 A1F *8 Caution points: *1. PT7C4337 uses 8 bits for address. For excess 0FH address, PT7C4337 will not respond (no acknowledge signal was given). *2. Alarm 1 mask bits. Select alarm repeated rate when an alarm occurs. *3. Alarm 2 mask bits. Select alarm repeated rate when an alarm occurs. *4. Oscillator and time count chain enable/disable bit. *5. Square wave output frequency select. *6. Interrupt output pin select bit. *7. Alarm 1 and alarm 2 enable bits. *8. Alarm 1 and alarm 2 flag bits. *9. Oscillator stop flag. *10. All bits marked with "0" are read-only bits. Their value when read is always "0".

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Control and status register Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0 Control /ETIME 0 0 RS2 RS1 INTCN A2IE A1IE 0E (default) 0 0 0 1 1 0 0 0 Status OSF 0 0 0 0 0 A2F A1F 0F (default) 1 0 0 0 0 0 Undefined Undefined Oscillator related bits

• /ETIME Enable oscillator and time count chain bit. /ETIME Data Description 0 Enable oscillator and time count chain. Default Read / Write 1 Disable oscillator and time count chain.
• OSF Oscillator Stop Flag. A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and calendar data. This bit is set to logic 1 anytime that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltage present on VCC is insufficient to support oscillation. 3) The /ETIME bit is turned off. 4) External influences on the crystal (e.g., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. Square wave frequency selection bits
• RS2, RS1 Square wave Rate Select. These bits control the frequency of the square-wave output when the square wave has been enabled. RS2, RS1 Data SQW output freq. (Hz) 00 1 01 4.096k 10 8.192k Read / Write 11 32.768k Default

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Interrupt related bits

• INTCN Interrupt Output pin select bit. This bit controls the relationship between the two alarms and the interrupt output pins. INTCN Data Description A match between the timekeeping registers and the alarm 1 registers activates the INTA pin (if the alarm 1 is enabled) and a match between the timekeeping registers and the alarm 2 registers activates the SQW/INTB pin (if the alarm 2 is enabled). Read / Write A match between the timekeeping registers and either alarm 1 or alarm 2 registers activates the INTA pin (if the alarms are enabled). In this configuration, a square wave is output on the SQW/INTB pin. Default
• A1IE Alarm 1 Interrupt Enable. A1IE Data Description 0 The A1F bit does not initiate the INTA signal. DefaultRead / Write 1 Permits the alarm 1 flag (A1F) bit in the status register to assert INTA.
• A1F Alarm 1 Flag. A1F Data Description Read / Write 0 The time do not match the alarm 1 registers. Default Read 1 Indicates that the time matched the alarm 1 registers. If the A1IE bit is also logic 1, the INTA pin goes low. A1F is cleared when written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
• A2IE Alarm 2 Interrupt Enable. A2IE Data Description 0 The A2F bit does not initiate an interrupt signal. Default Read / Write 1 Permits the alarm 2 flag (A2F) bit in the status register to assert INTA (when INTCN = 0) or to assert SQW/INTB (when INTCN = 1).
• A2F Alarm 2 Flag. A1F Data Description Read / Write 0 The time do not match the alarm 2 registers. Default Read 1 Indicates that the time matched the alarm 1 registers. This flag can be used to generate an interrupt on either INTA or SQW/INTB depending on the status of the INTCN bit. If the INTCN = 0 and A2F = 1 (and A2IE = 1), the INTA pin goes low. If the INTCN = 1 and A2F = 1 (and A2IE = 1), the SQW/INTB pin goes low. A2F is cleared when written to logic 0. Attempting to write to logic 1 leaves the value unchanged.

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Time Counter Time digit display (in BCD code):

• Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00.
• Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00.
• Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0 Seconds 0 S40 S20 S10 S8 S4 S2 S1 00 (default) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Minutes 0 M40 M20 M10 M8 M4 M2 M1 01 (default) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Hours 0 12, /24 H20 or P,/A H10 H8 H4 H2 H1 02 (default) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Note: Any registered imaginary time should be replaced with correct time, otherwise it will cause the clock counter malfunction.
• 12, /24 bit This bit is used to select between 12-hour clock system and 24-hour clock system. 12, /24 Data Description 0 24-hour system Read / Write 1 12-hour system This bit is used to select between 12-hour clock operation and 24-hour clock operation. 12, /24 Description Hours register 0 24-hour time display 1 12-hour time display * Be sure to select between 12-hour and 24-hour clock operation before writing the time data. 24-hour clock 12-hour clock 24-hour clock 12-hour clock 00 52 ( AM 12 ) 12 72 ( PM 12) 01 41 ( AM 01 ) 13 61 ( PM 01 ) 02 42 ( AM 02 ) 14 62 ( PM 02 ) 03 43 ( AM 03 ) 15 63 ( PM 03 ) 04 44 ( AM 04 ) 16 64 ( PM 04 ) 05 45 ( AM 05 ) 17 65 ( PM 05 ) 06 46 ( AM 06 ) 18 66 ( PM 06 ) 07 47 ( AM 07 ) 19 67 ( PM 07 ) 08 48 ( AM 08 ) 20 68 ( PM 08 ) 09 49 ( AM 09 ) 21 69 ( PM 09 ) 10 50 ( AM 10 ) 22 70 ( PM 10 ) 11 51 ( AM 11 ) 23 71 ( PM 11 )

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Days of the week Counter The day counter is a divide-by-7 counter that counts from 01 to 07 and up 07 before starting again from 01. Values that correspond to the day of week are user defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0 Days of the week 0 0 0 0 0 W4 W2 W1 03 (default) 0 0 0 0 0 Undefined Undefined Undefined Calendar Counter The data format is BCD format.

• Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December). Range from 1 to 30 (for April, June, September and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). Carried to month digits when cycled to 1.
• Month digits: Range from 1 to 12 and carried to year digits when cycled to 1.
• Year digits: Range from 00 to 99 and 00, 04, 08, … , 92 and 96 are counted as leap years. Addr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0 Dates 0 0 D20 D10 D8 D4 D2 D1 04 (default) 0 0 Undefined Undefined Undefined Undefined Undefined Undefined Months Century *1 0 0 M10 M8 M4 M2 M1 05 (default) Undefined 0 0 Undefined Undefined Undefined Undefined Undefined Years Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 06 (default) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined *1: The century bit is toggled when the years register overflows from 99 to 00.

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Alarm Register

• Alarm 1, Alarm 2 Register Addr. Description D7 D6 D5 D4 D3 D2 D1 D0 Alarm 1: Seconds A1M1 *1 S40 S20 S10 S8 S4 S2 S1 07 (default) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Alarm 1: Minutes A1M2 *1 M40 M20 M10 M8 M4 M2 M1 08 (default) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Alarm 1: Hours A1M3 *1 12, /24 H20 or P,/A H10 H8 H4 H2 H1 09 (default) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Alarm 1: Day, Date A1M4 *1 Day, /Date*1 D20 D10 W4, W2, W1, D1 0A (default) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Alarm 2: Minutes A2M2 *2 M40 M20 M10 M8 M4 M2 M1 0B (default) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Alarm 2: Hours A2M3 *2 12, /24 H20 or P,/A H10 H8 H4 H2 H1 0C (default) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Alarm 2: Day, Date A2M4 *2 Day, /Date*2 D20 D10 W4, W2, W1, D1 0D (default) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined *1 Note: Alarm mask bit, using to select Alarm 1 alarm rate. *2 Note: Alarm mask bit, using to select Alarm 2 alarm rate.

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Alarm Function Related register Register definition Addr. (hex) Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00 Seconds 0 S40 S20 S10 S8 S4 S2 S1

01 Minutes 0 M40 M20 M10 M8 M4 M2 M1

02 Hours 0 12, /24 H20 or

A, /P H10 H8 H4 H2 H1

03 Days of the week 0 0 0 0 0 W4 W2 W1

04 Dates 0 0 D20 D10 D8 D4 D2 D1

07 Alarm 1: Seconds A1M1 S4 0 S20 S10 S8 S4 S2 S1

08 Alarm 1: Minutes A1M2 M40 M20 M10 M8 M4 M2 M1

09 Alarm 1: Hours A1M3 12, /24 H20 or

A, /P H10 H8 H4 H2 H1 0A Alarm 1: Day, Date A1M4 Day, /Date D20 D10 W4, W2, W1, 0B Alarm 2: Minutes A2M2 M40 M20 M10 M8 M4 M2 M1 0C Alarm 2: Hours A2M3 12, /24 H20 or A, /P H10 H8 H4 H2 H1 0D Alarm 2: Day, Date A2M4 Day, /Date D20 D10 W4, W2, W1, 0E Control /ETIME 0 0 RS2 RS1 INTCN A2IE A1IE 0F Status OSF 0 0 0 0 0 A2F A1F Note: Alarm function does not support different hour system adopted in time and alarm register. The PT7C4337 contains two time-of-day/date alarms. The alarms can be programmed (by the INTCN bit of the control register) to operate in two different modes - each alarm can drive its own separate interrupt output or both alarms can drive a common interrupt output. Bit 7 of each of the time-of-day/date alarm registers are mask bits. When all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h ~ 04h match the values stored in the time-of-day/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Table 2 and Table 3 shows the possible settings. The Day, /Date bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 ~ 5 of that register reflects the day of the week or the date of the month. If the bit is written to logic 0, the alarm is the result of a match with date of the month. If the bit is written to logic 1, the alarm is the result of a match with day of the week. When the PT7C4337 register values match alarm register settings, the corresponding alarm flag (A1F or A2F) bit is set to logic 1. If the corresponding alarm interrupt enable (A1IE or A2IE) is also set to logic 1, the alarm condition activates one of the interrupt output (INTA or SQW/INTB) signals. The match is tested on the once-per-second update of the time and date registers.

Table 1. Alarm 1 Mask Bits Table 2. Alarm 2 Mask Bits

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) I2C Bus Interface Overview of I2C-BUS The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on. Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data transfers, data changes that occur on the SDA line are performed while the SCL lin e is at low level, and on the receiving side the data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per clock pulse. The I 2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allo cated to each device and the receiving device responds to communications only when its slave address matches the slave address in the received data. System Configuration All ports connected to the I 2C bus must be either open drain or open collector ports in orde r to enable AND connections to multiple devices. SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently , SCL and SDA are both held at high level when the bus is released (when communication is not being performed). Fig 1. System configuration Master MCU Slave RTC Other Peripheral Device Vcc SDA SCL Note: When there is only one master, the MCU is ready for driving SCL to "H" and RP of SCL may not required. RP RP

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Starting and Stopping I2C Bus Communications Fig 2. Starting and stopping on I2C bus 1) START condition, repeated START condition, and STOP condition a) START condition SDA level changes from high to low while SCL is at high level b) STOP condition SDA level changes from low to high while SCL is at high level c) Repeated START condition (RESTART condition) In some cases, the START condition occurs between a prev ious START condition and the next STOP condition, in which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the START condition, the SDA level changes from high to low while SCL is at high level. 2) Data Transfers and Acknowledge Responses during I 2C-BUS Communication a) Data transfers Data transfers are perfor med in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. The address auto increment function operates during both write and read operations. Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level. The receiver (receiving side) captures data while the SCL line is at high level. *Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART, or STOP condition.

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) b) Data acknowledge response (ACK signal) When transferring data, the receiver generates a confirmation resp onse (ACK signal, low active) each time an 8-bit data segment is received. If there is no ACK signal fr om the receiver, it indicates that normal communication has not been established. (Thi s does not include instances where the master device intentionally does not generate an ACK signal.) Immediately after the falling edge of the clock pulse correspondin g to the 8th bit of data on the SCL line, the transmitter rel eases the SDA line and the receiver sets the SDA line to low (= acknowledge) level. After transmitting the ACK signal, if the Master remains the receive r for transfer of the next byte, the SDA is released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes t he transmitter. When the Master is the receiver, if the Master does not send an ACK signal in res ponse to the last byte sent from the slave, th at indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awai ts a STOP condition from the Master. SCL from Master 1 2 89 SDA from transmitter (sending side) SDA from receiver (receiving side) Release SDA Low active ACK signal

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Slave Address The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device. All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device responds to this communication only when the specified slave address it has received matches its own slave address. Slave addresses have a fixed length of 7 bits. See table for the details. An R/W bit is added to each 7-bit slave address during 8-bit transfers. Table Slave address R / W bit Operation Transfer data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read D1 h 1 (= Read) Write D0 h 1 1 0 1 0 0 0 0 (= Write) I2C Bus’s Basic Transfer Format 1) Write via I 2C bus S Start indication P Stop indication Sr Restart indication A RTC Acknowledge A Master Acknowledge Slave address (7 bits) 11 0 1 00 0 0 write Addr. setting Slave address + write specification Address Specifies the write start address. A bit 76543210 bit bit bit bit bit bit bit AP Write data S A A C K A C K A C K Start Stop

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) 2) Read via I2C bus a) Standard read b) Simplified read Note: 1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications. 2. 49H, 4AH are used as test mode address. Customer should not use the addresses. Slave address (7 bits) 11010000 write Slave address + write specification Address Specifies the read start address. Addr. setting AS Slave address (7 bits) 11 0 1 00 0 1 Read Slave address + read specification Data read (1) Data is read from the specified start address and address auto increment. A bit 76543210 bit bit bit bit bit bit bit /A PSr 76543210 bit bit bit bit bit bit bitbit Data read (2) Address auto increment to set the address for the next data to be read. A C K N O A C K A A C K A C K A C K A Start StopRestart Data read (2) Address register auto increment to set the address for the next data to be read. Data read (1) Data is read from the address pointed by the internal address register and address auto increment. Slave address (7 bits) 11 0 1 00 0 1 Read A bit 76543210 bit bit bit bit bit bit bit /A PS 76543210 b i tb i tb i tb i tb i tb i tb i tbit A C K N O A C K A C K A StopStart Slave address + read specification

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Maximum Ratings Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Part No. Symbol Description Min Type Max Unit VCC Power voltage 1.8 5.5 VOSC Oscillator voltage 1.3 5.5 SCL, SDA 0.7V CC V CC+0.3 VIH Input high level INTA, SQW/INTB 5.5 VIL Input low level -0.3 0.3V CC V PT7C4337 TA Operating temperature -40 85 ºC

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Unless otherwise specified, VCC = 1.8~5.5V, TA = -40 °C to +85 °C Sym. Item Pin Condition Min Typ Max Unit VCC Supply voltage V CC 1.8 5.5 V VOSC Oscillator voltage V CC 1.3 5.5 V Active supply current V CC /ETIME bit = 0, Note 1 150 Standby current V CC /ETIME bit = 1, Note 2,3 1.5 µA Timekeeping current V CC V CC: 1.3~1.8V, Note 2,4,5 600 ICC Data retention current V CC V CC: 1.3~1.8V, Note 2 50 nA VIL1 Low-level input voltage SCL -0.3 0.3V CC VIH1 High-level input voltage SCL 0.7V CC V CC+0.3 V VIL2 Low-level input voltage X1 0.53 VIH2 High-level input voltage X1 0.53 V IOL Low-level output current SDA, /INTA, /INTB V OL = 0.4V 3 mA IIL Input leakage current SCL 1 µA IOZ Output current when OFF SDA, /INTA, /INTB 1 µA Note: 1. SCL clocking at max frequency = 400kHz, VIL = 0.0V, VIH = VCC. 2. Specified with 2-wire bus inactive, VIL = 0.0V, VIH = VCC. 3. SQW enabled. 4. Specified with the SQW function disabled by setting INTCN = 1. 5. Using recommended crystal on X1 and X2.

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Sym Description Value Unit VHM Rising and falling threshold voltage high 0.8 V CC V VHL Rising and falling threshold voltage low 0.2 V CC V Over the operating range Symbol Item Min. Typ. Max. Unit fSCL SCL clock frequency 400 kHz tSU;STA START condition set-up time 0.6 µs tHD;STA START condition hold time 0.6 µs tSU;DAT Data set-up time (RTC read/write) 200 ns tHD;DAT1 Data hold time (RTC write) 35 ns tHD;DAT2 Data hold time (RTC read) 0 µs tSU;STO STOP condition setup time 0.6 µs tBUF Bus idle time between a START and STOP condition 1.3 µs tLOW When SCL = "L" 1.3 µs tHIGH When SCL = "H" 0.6 µs tr Rise time for SCL and SDA 0.3 µs tf Fall time for SCL and SDA 0.3 µs tSP* Allowable spike time on bus 50 ns CB Capacitance load for each bus line 400 pF * Note: only reference for design Signal tf tr VHM V LM S Sr P tHD;STA tSP tSU;DATtHD;STA tHD;DAT tSU;STA tSU;STO SCL SDA tBUF tHD;STA tSU;STA fSCL tLOW tHIGH Sr S PStart condition Restart condition Stop condition

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Mechanical Information PE (Lead free DIP-8) .355 .400 9.01 10.16 .240 .280 6.09 7.11 7.62 8.25 .300 .325 .008 .014 0.20 0.35 .430 Max 15o 10.92 2.54 5.33 .210 Max SEATING PLANE .014 .022 .115 .150 .356 .558 2.921 3.81 .100 typical .015 Min 0.381 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS Note: 1) Controlling dimensions in inches. 2) Ref: JEDEC MS-001 BA

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) WE (Lead free SOIC-8) X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS Note: 1) Controlling dimensions in millimeters. 2) Ref: JEDEC MS-012 AA SEATING PLANE .189 .196 4.80 5.00 .149 .157 3.78 3.99 .016 .026 0.406 0.660 REF .050 BSC 1.27 .013 .020 0.330 0.508 .0040 .0098 0.10 0.25 .053 .068 1.35 1.75 .0099 .0196 0.25 0.50 x 45o 0-8o .016 .050 0.40 1.27 .0075 .0098 0.19 0.25 .2284 .2440 5.80 6.20

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) UE(Lead free MSOP-8) Dimensions in Millimeters Dimensions in Inches Symbol Min Max Min Max A 0.820 1.100 0.032 0.043 A1 0.020 0.150 0.001 0.006 A2 0.750 0.950 0.030 0.037 b 0.250 0.380 0.010 0.015 c 0.090 0.230 0.004 0.009 D 2.900 3.100 0.114 0.122 e 0.650(BSC) 0.026(BSC) E 2.900 3.100 0.114 0.122 E1 4.750 5.050 0.187 0.199 L 0.400 0.800 0.016 0.031 θ 0ْ6ْ0ْ6ْ

PT0205(02/07) Ver: 1 Data Sheet PT7C4337 Real-time Clock Module (I2C Bus) Notes Pericom Technology Inc. China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 U.S.A.: 3545 North First Street, San Jose, California 95134, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100 Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation.