Power Management

PM823

NXP Semiconductors

Dual Synchronous 1.5A/1.5A Step-down Buck Regulators with 525 mA LDO Rev. 4 ??23 June 2022

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Dual Synchronous 1.5A/1.5A Step-down Buck Regulators with 525 mA LDO

Document overview

Manufacturer or author: NXP B.V.
PDF pages: 51

Technical content

Datasheet sections

1 Product overview
2 Ordering information
3 Signal description
3.1 Pin configuration
3.2 Pin descriptions
4 Electrical specifications
4.1 Absolute maximum ratings
4.2 Recommended operating conditions
4.3 External passive components
4.4 Electrical characteristics
5 Functional description
5.1 Overview
5.2 Serial interface (1-wire)
5.3 Soft start
5.4 Power-up sequence
5.5 Power good
5.6 Operating modes
5.7 Sleep mode
5.8 Under voltage lock-out (UVLO)
5.9 Over voltage protection (OVP)
5.10 Over-temperature thermal shutdown (OTS)
6 Functional characteristics
6.1 Start-up waveforms
6.2 Load transient waveforms
6.3 Switching waveforms
7 Typical characteristics
8 Application information
8.1 PC board layout considerations and
8.2 PCB schematics
8.3 PCB layout examples
8.3.1 PCB layout for WLCSP package
8.3.2 PCB layout for QFN package
8.4 Bill of materials (BOM)
9 Package information
9.1 Package mechanical drawings
9.2 Package markings
10 Revision history

Features

Supports 2.7 V~5.5 V operating voltage
Two 1.5 A synchronous buck converters
Single LDO supports up to 525 mA
Ultra low 15 µA sleep current
3 MHz switching frequency
High output voltage accuracy
Supports both DVS and AVS
Single wire proprietary serial interface Package options
WLCSP-12 lead (0.35 mm ball pitch)
QFN-24 lead (0.5 mm pin pitch)

Applications

IoT devices
Wi-Fi modules
Smart home devices
Cameras, printers
Smart appliances
Wi-Fi hubs, Access Points (APs)
Set top boxes

2 Ordering information

Figure 3. Part numbering scheme Table 1. Part order options Note: Based on Marvell’s 88PG823 RMA history, no RMA will be accepted except manufacturing defects. Device provided AS-IS and support limited to NXP Wi-Fi/Bluetooth system-related questions. PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

3 Signal description

3.1 Pin configuration

Figure 4 shows PM823 12-lead WLCSP configuration diagram. Figure 4. 1.26 mm x 1.545 mm WLCSP-12 lead, pop (see through) view PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 5 shows PM823 24-pin QFN configuration diagram. Figure 5. 4 mm x 4 mm QFN-24 in 0.5 mm pitch pin configuration, top (see through) view

3.2 Pin descriptions

It must be connected to the negative terminals of the input and output capacitors
All PGND pins must be connected to SGND, EPAD, and make a star connection to system ground
Do not float any PGND pin A2 21, 22 SW2 O Switch node for Buck2 regulator
Internally connected to the drains of the high side and low side MOSFETs
Connect to the external inductor
When the switching regulator is disabled, the SW node is high- impedance
If the step-down regulator 2 is not in use, float this pin A3 23, 24 PVIN S Switching regulator power input
Power input voltage. Internally connected to the source of the high side MOSFET.
Connect a ceramic input capacitor or an equivalent low ESR input capacitor between PVIN and PGND. Place it as close as possible to PVIN and PGND pins. See Section 8 "Application information".
The voltage between SVIN and PVIN should be equal to 50mV or less
All PVIN pins must be connected to the same voltage source
Do not float any PVIN pin B1 N/A EN I Enable Input for all regulators
Logic high enables regulators and logic low disables regulators
See Section 4 "Electrical specifications" for detailed logic high and logic low specifications
When not in use, connect this pin to GND or connect a 0Ω resistor to GND
Do not float this pin B2 12 DVS1 I Dynamic voltage scaling control 1
This digital input is used to select one of the three operating modes. See Section 5.6 "Operating modes" output voltage settings for mode selection.
Do not float this pin B3 1 SW1 O Switch node for buck1 regulator
Internally connected to the drains of the high side and low side MOSFETs
Connect to the external inductor
When the switching regulator is disabled, the SW node is high impedance
If Step-down Regulator 1 is not in use, float this pin C1 17 FB2 I Buck2 regulator output voltage sense feedback
Connect this pin to the output capacitor
This pin senses the output voltage of the switching regulator
Do not float this pin

This digital input pin has two functions
If DVS1=0, this pin is used as DVS0 input
If DVS1=1, this pin becomes the one wire serial interface input
Input data into this pin is used to program the output voltage (see Section 5.2 "Serial interface (1-wire)")
When not in use, connect this pin to GND or connect a 0Ω resistor to GND
Do not share this pin with other serial interface pins Do not float this pin C3 2, 3 PGND1 GND Power ground for Buck1 regulator
This pin must be connected to the negative terminals of the input and output capacitors
All PGND pins must be connected to SGND, EPAD, and make a star connection to system ground
Do not float this pin D1 14 FB1 I Buck1 regulator output voltage sense feedback
Connect this pin to the output capacitor
This pin senses the output voltage of the switching regulator
Do not float this pin D2 6 VIN-LDO S LDO power supply
This is the power supply input for the LDO Regulator
Connect a ceramic input capacitor or an equivalent low ESR input capacitor between this pin and the ground plane. Place it as close as possible to this pin and the ground plane. See Section 8 "Application information". D3 7 VLDO O LDO output
This pin is the output of the LDO
Connect a ceramic output capacitor or an equivalent low ESR output capacitor between this pin and the ground plane. Place it as close as possible to this pin and the ground plane. See Section 8 "Application information". N/A 4 SGND GND Signal ground
This pin must be connected to SGND, all PGNDx pins, and make a star connection to system ground
Do not float this pin N/A 5 SVIN S Signal input voltage
This is the input voltage pin to the internal circuitry. See Section 4.4 "Electrical characteristics " for input voltage range.
Connect a decoupling ceramic capacitor or an equivalent low ESR decoupling capacitor between SVIN and SGND and position it as close as possible to the IC. See Section 8 "Application information".
The voltage between SVIN and PVIN should be equal to 50mV or less
Do not float this pin N/A 8 PG2 O Buck2 regulator power good output

This pin is an open-drain output
Connect a 100kΩ pull-up resistor from this pin to VOUT or a logic rail that is equal to or less than SVIN
The PG is held low when the output voltage is outside its regulation band and goes high after the output voltage is within regulation
When not in use, float this pin
In shutdown, the PG will be actively low N/A 9 PGLDO O LDO power good
This pin is an open-drain output
Connect a 100kΩ pull-up resistor from this pin to VOUT or a logic rail that is equal to or less than SVIN
The PG is held low when the output voltage is outside its regulation band and goes high after the output voltage is within regulation
When not in use, float this pin
In shutdown, the PG will be actively low N/A 10 PG1 O Buck1 regulator power good output
This pin is an open-drain output
Connect a 100kΩ pull-up resistor from this pin to VOUT or a logic rail that is equal to or less than SVIN
The PG is held low when the output voltage is outside its regulation band and goes high after the output voltage is within regulation
When not in use, float this pin
In shutdown, the PG will be actively low N/A 13 EN2 I Buck2 enable input
See Section 5.4 "Power-up sequence" to determine which part numbers have power sequences versus those that do not
For part numbers with a power sequence in the QFN-24 package, EN1, EN2, and ENLDO pins need to be connected together. Any logic high from EN1, EN2, and ENLDO pins enables all regulators. EN1, EN2, and ENLDO need to have logic low to disable all regulators. User can not individually enable or disable each step- down regulator for parts with a power sequence
For part numbers without a power sequence, logic high for this pin enables Step-down Regulator 2. Logic low for this pin disables Step- down Regulator 2
When not in use, connect this pin to GND or connect a 0Ω resistor to ground
Do not float this pin N/A 15 EN1 I Buck1 enable input
See Section 5.4 "Power-up sequence" to determine which part numbers have power sequences versus those that do not
For part numbers with a power sequence in the QFN-24 package, EN1, EN2, and ENLDO pins need to be connected together. Any logic high from EN1, EN2, and ENLDO pins enables all regulators. EN1, EN2, and ENLDO need to have logic low to disable all regulators. User can not individually enable or disable each step- down regulator for parts with a power sequence

For part numbers without a power sequence, logic high for this pin enables Step-down Regulator 1. Logic low for this pin disables Step- down Regulator 1
When not in use, connect this pin to GND or connect a 0Ω resistor to ground
Do not float this pin N/A 16 ENLDO I LDO enable input
See Section 5.4 "Power-up sequence" to determine which part numbers have power sequences versus those that do not
For part numbers with a power sequence in the QFN-24 package, EN1, EN2, and ENLDO pins need to be connected together. Any logic high from EN1, EN2, and ENLDO pins enables all regulators. EN1, EN2, and ENLDO need to have logic low to disable all regulators. User can not individually enable or disable each step- down regulator for parts with a power sequence
For part numbers without a power sequence, logic high for this pin enables the LDO Regulator. Logic low for this pin disables the LDO Regulator
When not in use, connect this pin to GND or connect a 0Ω resistor to ground
The voltage on this pin must never be higher than the voltage on the SVIN pin + 0.3V for all conditions
Do not float this pin N/A 25 EPAD GND Exposed thermal pad
This pin must be connected to SGND, all PGND pins, and make a star connection to system ground. See Section 8 "Application information".
Do not float this pin

4 Electrical specifications

4.1 Absolute maximum ratings

Table 4. Absolute maximum ratings[1] [1] Exceeding the absolute maximum rating may damage the device. [2] SWx is capable of sustaining -1.0V for less than 50 ns.

4.2 Recommended operating conditions

4.3 External passive components

4.4 Electrical characteristics

Dual Synchronous 1.5A/1.5A Step-down Buck Regulators with 525 mA LDO

5 Functional description

5.1 Overview

The PM823 is a performant power management regulator as well as a general purpose power management regulator for portable applications. The PM823 includes two step-down switching (Buck) regulators and one Low Dropout (LDO) regulator. The switching step-down regulators utilize a proprietary internally compensated PWM control to regulate its respective output voltages that require no additional external compensation. The PM823 operates from an input voltage range of 2.7V to 5.5V. The LDO regulator can operate with an input voltage ranging from 100 mV above its regulation point to 5.5V. Each of the two switching regulators can deliver a maximum continuous load of 1.5A at 3 MHz switching frequency; while the LDO can deliver a continuous load current of up to 525 mA. Figure 6 shows the PM823 block diagram. PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5 — 27 February 2024

5.2 Serial interface (1-wire)

20% tolerance. Figure 7 illustrates the serial interface pulse setup. 1) Each write sequence needs 18 pulses to complete. 2) During a non-write operation, the input needs to be at VLOW (<VIL). at VLOW (<VIL) for a minimum of 80 s. Figure 7. Serial programmability PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

5.3 Soft start

limiting the inrush current.

5.4 Power-up sequence

For PM823 with WLCSP package, the EN pin controls the output sequence for all three regulators. enabled, Buck2 initializes. After Buck2 completes its start-up, the LDO initializes, followed by Buck1. Figure 8. Power-up sequence timing diagram - WLCSP package option PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

5.5 Power good

when this transistor is off, or when the buck regulator is disabled via the enable pin.

5.6 Operating modes

Table 8. Each operating mode provides different power-saving features to meet different application needs. For example, even if the serial interface is not used, the DVS pins are still able to provide the power-saving feature. Table 8. Operating mode selections 2 to support different applications.

Active Mode 3 improves the system power consumption if the serial interface is not used.

beyond the limit, the over-current protection mechanism kicks in and shuts down the output voltage.

5.7 Sleep mode

Dual Synchronous 1.5A/1.5A Step-down Buck Regulators with 525 mA LDO

5.8 Under voltage lock-out (UVLO)

This feature ensures that both internal MOSFETs for the step-down regulators and for the LDO regulator have adequate voltage levels to operate. When the input voltage is below UVLO low threshold, both MOSFETs for the step-down regulators and for the LDO regulator are off until the input rises above the UVLO high threshold. The switching nodes (SW) for both step-down regulators are in high Z state when the input voltage is less than UVLO high threshold.

5.9 Over voltage protection (OVP)

An over-voltage comparator guards against line transient overshoots, as well as other serious conditions that may damage the IC. When the input voltage is above OVP high threshold the output turns off and the switching node (SW) for both step-down regulators are high Z. The device will remain at this state until the input voltage comes back below OVP low threshold. PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5 — 27 February 2024

Figure 9. UVLO and OVP waveforms

5.10 Over-temperature thermal shutdown (OTS)

PM823. The device is enabled again once the junction temperature is below OTS low threshold. PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

6 Functional characteristics

VIN = 5V, VOUT_BK1 = 1.1V, VOUT_BK2 = 2.2V, and VOUT_LDO = 1.8V.

6.1 Start-up waveforms

Figure 10. Start-up Figure 11. UVLO / OVP Thresholds Figure 12. Buck1 short circuit Figure 13. Buck2 short circuit PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

6.2 Load transient waveforms

Figure 14. Buck1 (1.1V) load transient response 100 mA Figure 15. Buck1 (1.1V) load transient response 750 mA Figure 16. Buck2 (2.2V) load transient response 100 mA Figure 17. Buck2 (2.2V) load transient response 750 mA PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

6.3 Switching waveforms

Figure 18. Buck1 (1.1V) PFM Output Ripples at 25 mA Figure 19. Buck1 (1.1V) PWM Output Ripples at 1.5A Figure 20. Buck2 (2.2V) PFM Output Ripples at 45 mA Figure 21. Buck2 (2.2V) PWM Output Ripples at 1.5A PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

7 Typical characteristics

Section 8.2 "PCB schematics" at TA = 25°C. Figure 22. Buck1 (1.1V) efficiency vs output current Figure 23. Buck2 (2.2V) efficiency vs output current Figure 24. Buck1 (3.3V) efficiency vs output current Figure 25. Buck2 (1.8V) efficiency vs output current Figure 26. Buck1 (1.1V) output voltage vs output current Figure 27. Buck2 (2.2V) output voltage vs output current Figure 28. Buck1 (3.3V) output voltage vs output current Figure 29. Buck2 (1.8V) output voltage vs output current PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Dual Synchronous 1.5A/1.5A Step-down Buck Regulators with 525 mA LDO

8 Application information

8.1 PC board layout considerations and guidelines

Caution: To avoid abnormal noise and operating behavior follow these layout recommendations. The PC board layout is very critical in any switching converter application. An improper layout can contribute to system instability, excessive EMI (electromagnetic interference), and high switching loss. Follow these basic guidelines to assure a good PCB layout: 1. Copy these layout guidelines within this section as much as possible including the use of the recommended BOM 2. Before importing the net list into the layout tool, it is highly recommended to go through the board floor planning phase (the process defining the general location of components on the blank PCB before drawing in any traces). a. It is highly recommended to allocate 40% or more of the layout schedule to dedicate for floor planning of the board. b. Here are some of the questions that are commonly derived from the floor planning phase. Where to place the SOC on the board? On the top or bottom layer? In the center? c. After deciding where to place the SOC, the next step is to place the power management IC for the core voltage of the SOC. d. The optimum position to place the power management IC is on the same layer as the SOC. The output voltage of the power management IC should be close to the input voltage of the SOC. e. Continue this floor planning phase for the rest of the voltage rails before starting to layout the board. 3. ATTENTION: Before starting to route any traces and after choosing where to place the power management IC on the board, the next step is to place the input capacitors. a. Place input capacitor for the SVIN and SGND pins on the same layer as the IC. b. Then, place input capacitor for the PVIN and PGND pins on the same layer as the IC. c. Next, place the negative terminal for the output capacitors next to the negative terminal of the input capacitors. d. See Section 4.4 "Electrical characteristics " for the recommended input and output capacitor values. e. See Section 4.4 "Electrical characteristics " for the recommended distance between the IC and the input and output capacitors. f. Do not place the inductor before placing the capacitors. The input capacitors placement is the most crucial for proper operation. The AC current circulating through the input capacitors, loop (LP1), is a square wave with rise and fall times as fast as 8ns (typical) with slew rates being as high as 300µA/µs (typical). At these fast slew rates, stray and parasitic PCB inductance can generate voltage spikes as high as 3V per inch of the PCB trace; VIND = L * di/dt. g. Keep loop 2 (LP2) as small as possible and connect the negative terminal of the output capacitor as close to the negative terminal of the input capacitor as possible. 4. The input capacitors for the SVIN and PVIN pins need to be Ceramic or equivalent low ESR capacitor. a. Do not replace the Ceramic input or output capacitors with Tantalum capacitors. b. Any type of capacitor can be placed in parallel with the input capacitor as long as the Ceramic input capacitor is placed next to the IC. If Tantalum input capacitors are used, it must be rated for switching regulator applications and the operating voltage must be de-rated by 50%. c. Any type of capacitor can be placed in parallel with the output capacitor. PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5 — 27 February 2024

Dual Synchronous 1.5A/1.5A Step-down Buck Regulators with 525 mA LDO d. Low-ESR capacitors like the POSCAP from Sanyo can replace the Ceramic output capacitors as long as the capacitor value is the same or greater. Note that Ceramic capacitors provide the lowest noise and smallest foot print solution. 5. Use planes for the ground, input and output power to maintain good voltage filtering and to keep power losses low. If there is not enough space to place a power plane for the input sup-ply, then the input supply trace must be at least 3/8 of an inch wide. 6. Keep the switching and all sensitive traces away from the fast dv/dt to minimize capacitive coupling effects. PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5 — 27 February 2024

8.2 PCB schematics

1 LP1

Figure 52. PCB schematic - WLCSP package

For C3 and C4, can use 0.1 µF but it is best to use maximum capacitance for the 0603(mm)/0201(in) case size. For example, 0.22 µF is available 0603(mm)/0201(in) size.
For all capacitors, use the highest voltage rating available for the case size. For example, 22 µF is available in 1608(mm)/0603(in) case size with 6.3V and 10V rating. Use 22 µF/10V rating instead of 22 µF/6.3V rating
See Section 5.4 "Power-up sequence" for the power sequence function

Figure 53. PCB schematic - QFN package

For C3 and C4, can use 0.1µF but it is best to use maximum capacitance for the 0603(mm)/0201(in) case size. For example, 0.22µF is available 0603(mm)/0201(in) size
For all capacitors, use the highest voltage rating available for the case size. For example, 22µF is available in 1608 (mm) / 0603 (in) case size with 6.3V and 10V rating. Use 22µF/10V rating instead of 22µF/6.3V rating
For EN1, EN2, and ENLDO pins, can connect directly to VIN or through a 100K pull-up resistor if all outputs are turned on at the same time
If the LDO output voltage comes after the Buck2 output, then connect VIN_LDO to VOUT2_BK2. Either have the ENLDO pin connect to VOUT_BK2 or connect through a 100K pull-up resistor.
See Section 5.2 "Serial interface (1-wire)" for the SDI function and configuration
See Section 5.4 "Power-up sequence" for the power sequence function
Do not float DVS0/SDI and DVS1 pin.

8.3 PCB layout examples

WLCSP actual board size = 286 mil x 258 mil
QFN actual board size = 409 mil x 510 mil
WLCSP total copper layers = 4

8.3.1 PCB layout for WLCSP package

on the same PCB layer as the IC. Figure 54. Top traces, vias, and copper (not to scale) PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

8.3.2 PCB layout for QFN package

on the same PCB layer as the IC. Figure 58. Top traces, vias, and copper (not to scale) PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

8.4 Bill of materials (BOM)

Check component datasheets for the latest updates before designing these components in the schematic. heat source that these components will be subject to. Table 9. BOM for WLCSP package PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

9 Package information

9.1 Package mechanical drawings

Figure 60. 1.260mm x 1.545mm WLCSP-12 mechanical drawing Note: All dimensions in mm. See Section 9.2 "Package markings" for package marking and pin 1 location. PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 61. 4mm x 4mm QFN-24 mechanical drawing Note: All dimensions in mm. See Section 9.2 "Package markings" for package marking and pin 1 location. PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

9.2 Package markings

Note: The above drawing is not drawn to scale. The location of markings is approximate. Figure 63. Package marking and pin 1 location - QFN package Note: The above drawing is not drawn to scale. The location of markings is approximate. Figure 64. Package marking and pin 1 location - WLCSP package PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Dual Synchronous 1.5A/1.5A Step-down Buck Regulators with 525 mA LDO Document ID Release date Description PM823 v.5 27 February 2024 CIN 202402023I

Section 5.6 "Operating modes": removed the reference to internal registers.
Section DVS output voltage settings: removed.
Section 5.7 "Sleep mode": removed the reference to DVS register information.
Section Register sets: removed. PM823 v.4 23 June 2022 • Changed the document confidentiality level from "Company Confidential" to "Public". No changes in the content. PM823 v.3 24 May 2021 Signal description
Figure 4 "1.26 mm x 1.545 mm WLCSP-12 lead, pop (see through) view": corrected.

Application information

Figure 53 "PCB schematic - QFN package": corrected.

Package information

Section 9.2 "Package markings": updated with the marking of QFN ( Figure 63) and WLCSP (Figure 64) packages. PM823 v.2 12 May 2021 Signal description
Figure 5 "4 mm x 4 mm QFN-24 in 0.5 mm pitch pin configuration, top (see through) view": corrected. PM823 v.1 18 November 2020 • Initial version

Dual Synchronous 1.5A/1.5A Step-down Buck Regulators with 525 mA LDO Legal information Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL https://www.nxp.com. Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at https://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5 — 27 February 2024

Dual Synchronous 1.5A/1.5A Step-down Buck Regulators with 525 mA LDO Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this document expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. Bluetooth — the Bluetooth wordmark and logos are registered trademarks owned by Bluetooth SIG, Inc. and any use of such marks by NXP Semiconductors is under license. PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5 — 27 February 2024

Dual Synchronous 1.5A/1.5A Step-down Buck Regulators with 525 mA LDO Tables Figures Fig. 1. PM823 typical application-QFN package Fig. 2. PM823 typical application-WLCSP package Fig. 4. 1.26 mm x 1.545 mm WLCSP-12 lead, pop Fig. 5. 4 mm x 4 mm QFN-24 in 0.5 mm pitch pin Fig. 8. Power-up sequence timing diagram - Fig. 14. Buck1 (1.1V) load transient response Fig. 15. Buck1 (1.1V) load transient response Fig. 16. Buck2 (2.2V) load transient response Fig. 17. Buck2 (2.2V) load transient response Fig. 18. Buck1 (1.1V) PFM Output Ripples at Fig. 20. Buck2 (2.2V) PFM Output Ripples at Fig. 22. Buck1 (1.1V) efficiency vs output current Fig. 23. Buck2 (2.2V) efficiency vs output current Fig. 24. Buck1 (3.3V) efficiency vs output current Fig. 25. Buck2 (1.8V) efficiency vs output current Fig. 26. Buck1 (1.1V) output voltage vs output Fig. 27. Buck2 (2.2V) output voltage vs output Fig. 28. Buck1 (3.3V) output voltage vs output Fig. 29. Buck2 (1.8V) output voltage vs output Fig. 30. Buck1 output voltage vs input voltage Fig. 31. Buck2 Output Voltage vs Input Voltage Fig. 32. Quiescent Current vs Input Voltage For Fig. 33. Buck1 high side RDS(ON) vs. input voltage Fig. 34. Buck2 high side RDS(ON) vs. input voltage Fig. 35. Buck1 low side RDS(ON) vs. input voltage Fig. 36. Buck2 low side RDS(ON) vs. input voltage Fig. 37. Buck1 high side RDS(ON) vs. input voltage Fig. 38. Buck2 high side RDS(ON) vs. input voltage Fig. 39. Buck1 low side RDS(ON) vs. input voltage Fig. 40. Buck2 low side RDS(ON) vs. input voltage Fig. 41. Buck1 Output Voltage Error vs Fig. 42. Buck2 Output Voltage Error vs Fig. 43. Quiescent current vs temperature for active Fig. 44. Buck1 high side RDS(ON) vs. temperature Fig. 45. Buck2 high side RDS(ON) vs. temperature Fig. 46. Buck1 low side RDS(ON) vs. temperature Fig. 47. Buck2 low side RDS(ON) vs. temperature Fig. 48. Buck1 high side RDS(ON) vs. temperature Fig. 49. Buck2 high side RDS(ON) vs. temperature Fig. 50. Buck1 low side RDS(ON) vs. temperature Fig. 51. Buck2 low side RDS(ON) vs. temperature PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5 — 27 February 2024

Dual Synchronous 1.5A/1.5A Step-down Buck Regulators with 525 mA LDO Fig. 57. Bottom traces, vias, and copper (not to Fig. 59. Bottom traces, vias, and copper (not to Fig. 60. 1.260mm x 1.545mm WLCSP-12 Fig. 62. 4mm x 4mm QFN-24 mechanical drawing - Fig. 63. Package marking and pin 1 location - QFN Fig. 64. Package marking and pin 1 location - PM823 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 5 — 27 February 2024

Selected Specification

NXP Semiconductors PM823 overview.

Summary

Dual Synchronous 1.5A/1.5A Step-down Buck Regulators with 525 mA LDO Rev. 4 ??23 June 2022

Description

Dual Synchronous 1.5A/1.5A Step-down Buck Regulators with 525 mA LDO Rev. 4 ??23 June 2022

Source title PM823 Datasheet(PDF) - NXP Semiconductors

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