PLUS405-37

PLUS405-37 PHILIPS

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Programmable logic sequencers (16 × 64 × 8) Product specification 1996 Nov 12 INTEGRATED CIRCUITS IC13 Data Handbook

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

21996 Nov 12 853–1280 17500

DESCRIPTION

The PLUS405 devices are bipolar, programmable state machines of the Mealy type. Both the AND and the OR array are user-programmable. All 64 AND gates are connected to the 16 external dedicated inputs (I0 - I15) and to the feedback paths of the 8 on-chip State Registers (QP0 - QP7). Two complement arrays support complex IF-THEN-ELSE state transitions with a single product term (input variables C0, C1). All state transition terms can include True, False and Don’t Care states of the controlling state variables. All AND gates are merged into the programmable OR array to issue the next-state and next-output commands to their respective registers. Because the OR array is programmable, any one or all of the 64 transition terms can be connected to any or all of the State and Output Registers. All state (QP0 - QP7) and output (QF0 - QF7) registers are edge-triggered, clocked J-K flip-flops, with Asynchronous Preset and Reset options. The PLUS405 architecture provides the added flexibility of the J-K toggle function which is indeterminate on S-R flip-flops. Each register may be individually programmed such that a specific Preset-Reset pattern is initialized when the initialization pin is raised to a logic level “1”. This feature allows the state machine to be asynchronously initialized to known internal state and output conditions, prior to proceeding through a sequence of state transitions. Upon power-up, all registers are unconditionally preset to “1”. If desired, the initialization input pin (INIT) can be converted to an Output Enable (OE) function as an additional user-programmable feature. Availability of two user-programmable clocks allows the user to design two independently clocked state machine functions consisting of four state and four output bits each. Order codes are listed in the Ordering Information Table.

FEATURES

• PLUS405-37 – fMAX = 37MHz – 50MHz clock rate
• PLUS405-45 – fMAX = 45MHz – 58.8MHz clock rate
• Functional superset of PLS105/105A
• Field-programmable (Ti-W fusible link)
• 16 input variables
• 8 output functions
• 64 transition terms
• 8-bit State Register
• 8-bit Output Register
• 2 transition Complement Arrays
• Multiple clocks*
• Programmable Asynchronous Initialization or Output Enable
• Power-on preset of all registers to “1”
• “On-chip” diagnostic test mode features for access to state and output registers
• 950mW power dissipation (typ.)
• TTL compatible
• J-K or S-R flip-flop functions
• Automatic “Hold” states
• 3-State outputs

APPLICATIONS

• Interface protocols
• Sequence detectors
• Peripheral controllers
• Timing generators
• Sequential circuits
• Elevator contollers
• Security locking systems
• Counters
• Shift registers PIN CONFIGURATIONS 14 15 N Package 1234 12 13 14 15 16 17 18 262728 CLK I5/CLK GND F3 INIT/OE I15 I14 I13 I12 I11 I10 VCC CLKI6 I7 V CC I5/CLK I8 I9 F5 F4 GND F3 F2 F1 F0 INIT/OE I15 I14 I13 I12 I11 I10 N = Plastic DIP (600mil-wide) A = Plastic Leaded Chip Carrier A Package SP00251

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 3

ORDERING INFORMATION

FREQUENCY ORDER CODE DRAWING NUMBER 28-Pin Plastic DIP (600mil-wide) 45MHz (tIS1 + tCKO1 ) PLUS405–45N SOT117-2 28-Pin Plastic DIP (600mil-wide) 37MHz (tIS1 + tCKO1 ) PLUS405–37N SOT117-2 28-Pin Plastic Leaded Chip Carrier 45MHz (tIS1 + tCKO1 ) PLUS405–45A SOT261-3 28-Pin Plastic Leaded Chip Carrier 37MHz (tIS1 + tCKO1 ) PLUS405–37A SOT261-3 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION POLARITY 1 CLK1 Clock: The Clock input to the State and Output Registers. A Low-to-High transition on this line is necessary to update the contents of both state and output registers. Pin 1 only clocks P0–3 and F0–3 if Pin 4 is also being used as a clock. Active-High (H) 2, 3, 5–9, 26–27 20–22 I0–I4, I7, I6 I8–I9 I13–I15 Logic Inputs: The 12 external inputs to the AND array used to program jump conditions between machine states, as determined by a given logic sequence. True and complement signals are generated via use of “H” and “L”. Active-High/Low (H/L)

4 CLK2 Logic Input/Clock: A user programmable function:

• Logic Input: A 13th external logic input to the AND array, as above. Active-High/Low (H/L)
• Clock: A 2nd clock for the State Registers P4–7 and Output Registers F4–7, as above. Note that input buffer I5 must be deleted from the AND array (i.e., all fuse locations “Don’t Care”) when using Pin 4 as a Clock. Active-High (H)

23 I12 Logic/Diagnostic Input: A 14th external logic input to the AND array, as above, when

exercising standard TTL or CMOS levels. When I12 is held at +10V, device outputs F0–F7 reflect the contents of State Register bits P0–P7. The contents of each Output Register remains unaltered. Active-High/Low (H/L)

24 I11 Logic/Diagnostic Input: A 15th external logic input to the AND array, as above, when

exercising standard TTL levels. When I11 is held at +10V, device outputs F0–F7 become direct inputs for State Register bits P0–P7; a Low-to-High transition on the appropriate clock line loads the values on pins F0–F7 into the State Register bits P0–P7. The contents of each Output Register remains unaltered. Active-High/Low (H/L)

25 I10 Logic/Diagnostic Input: A 16th external logic input to the AND array, as above, when

exercising standard TTL levels. When I10 is held at +10V, device outputs F0–F7 become direct inputs for Output Register bits Q0–Q7; a Low-to-High transition on the appropriate clock line loads the values on pins F0–F7 into the Output Register bits Q0–Q7. The con- tents of each State Register remains unaltered. Active-High/Low (H/L) 10–13 15–18 F0 – F7 Logic Outputs/Diagnostic Outputs/Diagnostic Inputs: Eight device outputs which nor- mally reflect the contents of Output Register Bits Q0–Q7, when enabled. When I12 is held at +10V, F0–F7 = (P0–P7). When I11 is held at +10V, F0–F7 become inputs to State Reg- ister bits P0–P7. When I10 is held at +10V, F0–F7 become inputs to Output Register bits Q0–Q7. Active-High (H)

19 INIT/OE Initialization or Output Enable Input: A user programmable function:

• Initialization: Provides an asynchronous preset to logic “1” or reset to logic “0” of all State and Output Register bits, determined individually for each register bit through user programming. INIT overrides Clock, and when held High, clocking is inhibited and F0–F7 and P0–P7 are in their initialization state. Normal clocking resumes with the first full clock pulse following a High-to-Low clock transition, after INIT goes Low. See timing definition for tNVCK and tVCK . Active-High (H)
• Output Enable: Provides an output enable function to buffers F0–F7 from the Output Registers. Active-Low (L)

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 4

TRUTH TABLE 1, 2, 3, 4, 5, 6, 7 OPTION VCC INIT OE I10 I11 I12 CK J K Q P Q F F H * * * X X X H/L H/L Q F L +10V X X ↑ X X Q P L L L +10V X X ↑ X X Q P H H L X +10V X ↑ X X L Q F L L X +10V X ↑ X X H Q F H L X X +10V X X X Q P Q F Q P L X X X X X X Q P Q F Q F H X X * X X X Q P Q F Hi-Z +5V X +10V X X ↑ X X Q P L L X +10V X X ↑ X X Q P H H X X +10V X ↑ X X L Q F L X X +10V X ↑ X X H Q F H L X X +10V X X X Q P Q F Q P L X X X X X X Q P Q F Q F L X X X ↑ L L Q P Q F Q F L X X X ↑ L H L L L L X X X ↑ H L H H H L X X X ↑ H H Q P Q F Q F ↑ X X X X X X X X H H NOTES: 1. Positive Logic: S/R (or J/K) = T0 + T1 + T2 + . . . T63 2. Either Initialization (Active-High) or Output Enable (Active-Low) are available, but not both. The desired function is a user-programmable option. 3. ↑ denotes transition from Low-to-High level. 4. * = H or L or +10V 5. X = Don’t Care (<5.5V) 6. H/L implies that either a High or a Low can occur, depending upon user-programmed selection (each State and Output Register individually programmable). 7. When using the Fn pins as inputs to the State and Output Registers in diagnostic mode, the F buffers are 3-Stated and the indicated levels on the output pins are forced by the user. VIRGIN STATE A factory-shipped virgin device contains all fusible links intact, such that: 1. INIT/OE is set to INIT. In order to use the INIT function, the user must select either the PRESET or the RESET option for each flip-flop. Note that regardless of the user-programmed initialization, or even if the INIT function is not used, all registers are preset to “1” by the power-up procedure. 2. All transition terms are inactive (0). 3. All S/R (or J/K) flip-flop inputs are disabled (0). 4. The device can be clocked via a T est Array preprogrammed with a standard test pattern. 5. Clock 2 is inactive. LOGIC FUNCTION 0 1 0 0 0 1 STATE REGISTER SR Sn + 1 PRESENT STATE A ⋅ B ⋅ C ⋅ . . . NEXT STATE Q2 Q1 Q0 K0 = 0 RESET Q 1: J1 = 0 HOLD Q 2: J2 = 0 K2 = 0 RESET Q 3: J3 = (Q3 ⋅ Q2 ⋅ Q1 ⋅ Q0) ⋅ A ⋅ B ⋅ C . . . SP00231

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 5

I I/CLK J K P R Q (4) J K P R Q (4) J K P R Q (4) J K P R Q (4) F CK F INIT/OE SP00252

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 6

NOTE: Denotes a programmable fuse location. SP00253

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 7

DETAILS FOR REGISTERS FOR PLUS405 STATE REGISTERS J K Q P R CLK TO INIT LINE TO AND ARRAY Detail B

19 INIT/OE

J K Q P R CLK TO INIT LINE Detail C Fn FROM PIN 1 CLK FROM PIN 4 (I5/CLK) Detail D SP00254 COMPLEMENT ARRAY DETAIL P63 P62 P2 P1 P0 A B D E TO OR ARRAY SP00255 The Complement Array is a special sequencer feature that is often used for detecting illegal states. It is also ideal for generating IF-THEN-ELSE logic statements with a minimum number of product terms. The concept is deceptively simple. If you subscribe to the theory that the expressions (/A * /B * /C) and (A + B + C) are equivalent, you will begin to see the value of this single term NOR array. The Complement Array is a single OR gate with inputs from the AND array. The output of the Complement Array is inverted and fed back to the AND array (NOR). The output of the array will be Low if any one or more of the AND terms connected to it are active (High). If, however, all the connected terms are inactive (Low), which is a classic unknown state, the output of the Complement Array will be High. Consider the Product Terms A, B and D that represent defined states. They are also connected to the input of the Complement Array. When the condition (not A and not B and not D) exists, the Complement Array will detect this and propagate an Active-High signal to the AND array. This signal can be connected to Product Term E, which could be used in turn to reset the state machine to a known state. Without the Complement Array, one would have to generate product terms for all unknown or illegal states. With very complex state machines, this approach can be prohibitive, both in terms of time and wasted resources. Note that the PLUS405 has 2 Complement Arrays which allow the user to design 2 independent Complement functions. This is particularly useful if 2 independent state machines have been implemented on one device. Note that use of the Complement Array adds an additional delay path through the device. Please refer to the AC Electrical Characteristics for details.

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 8

ABSOLUTE MAXIMUM RATINGS 1 SYMBOL PARAMETER RATINGS UNIT VCC Supply voltage +7 VDC VIN Input voltage +5.5 VDC VOUT Output voltage +5.5 VDC IIN Input currents –30 to +30 mA IOUT Output currents +100 mA Tamb Operating temperature range 0 to +75 °C TSstg Storage temperature range –65 to +150 °C NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. THERMAL RATINGS TEMPERATURE Maximum junction 150°C Maximum ambient 75°C Allowable thermal rise ambient to junction 75°C DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT Input voltage2 VIH High VCC = MAX 2.0 V VIL Low VCC = MIN 0.8 V VIC Clamp3 VCC = MIN, IIN = –12mA –0.8 –1.2 V Output voltage2 VOH High VCC = MIN, IOH = –2mA 2.4 V VOL Low VCC = MIN, IOL = 9.6mA 0.35 0.45 V Input current IIH High VCC = MAX, VIN = VCC <1 30 µA IIL Low VCC = MAX, VIN = 0.45V –20 –250 µA Output current IO(OFF) Hi-Z state VCC = MAX, VOUT = 2.7V 1 40 µA VCC = MAX, VOUT = 0.45V –1 –40 µA IOS Short circuit 3, 4 VOUT = 0V –15 –70 mA ICC VCC supply current5 VCC = MAX 190 225 mA Capacitance C IN Input VCC = 5.0V, VIN = 2.0V 8 pF C OUT Output VCC = 5.0V, VOUT = 2.0V 10 pF NOTES: 1. All typical values are at VCC = 5V. Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Duration of short-circuit should not exceed one second. 5. ICC is measured with the INIT/OE input grounded, all other inputs at 4.5V and the outputs open.

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 9

AC ELECTRICAL CHARACTERISTICS R 1 = 470Ω , R2 = 1kΩ , CL = 30pF, 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER FROM TO PLUS405-37 PLUS405-45 UNIT MIN TYP 1 MAX MIN TYP 1 MAX Pulse width tCKH1 Clock High; CLK1 (Pin 1) CK+ CK– 10 8 8.5 7 ns tCKL1 Clock Low; CLK1 (Pin 1) CK– CK+ 10 8 8.5 7 ns tCKP1 CLK1 Period CK+ CK+ 20 16 17 14 ns tCKH2 Clock High; CLK2 (Pin 4) CK+ CK– 10 8 10 8 ns tCKL2 Clock Low; CLK2 (Pin 4) CK– CK+ 10 8 10 8 ns tCKP2 CLK2 Period CK+ CK+ 20 16 20 16 ns tINITH Initialization pulse INIT– INIT+ 15 10 15 8 ns Setup time tIS1 Input Input ± CK+ 15 12 12 10 ns tIS2 Input (through Complement Array) Input ± CK+ 25 20 22 18 ns tVS Power-on preset VCC + CK– 0 –10 0 –10 ns tVCK Clock resume (after Initialization) INIT– CK– 0 –5 0 –5 ns tNVCK Clock lockout (before Initialization) CK– INIT– 15 5 15 5 ns Hold time tIH Input CK+ Input ± 0 –5 0 –5 ns Propagation delay tCKO1 Clock1 (Pin 1) CK1+ Output ± 10 12 8 10 ns tCKO2 Clock2 (Pin 4) CK2+ Output ± 12 15 10 12 ns tOE 2 Output Enable OE– Output – 12 15 12 15 ns tOD 2 Output Disable OE+ Output + 12 15 12 15 ns tINIT Initialization INIT+ Output + 15 20 15 20 ns tPPR Power-on Preset VCC + Output + 0 10 0 10 ns Notes on following page

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 10

AC ELECTRICAL CHARACTERISTICS (Continued) R 1 = 470Ω , R2 = 1kΩ , CL = 30pF, 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER FROM TO PLUS405-37 PLUS405-45 UNIT MIN TYP 1 MAX MIN TYP 1 MAX Frequency of operation fMAX1 CLK1; without Complement Array tIS1 tCKO1 Input ± Output ± 37.0 45.5 45.5 55.6 MHz fMAX2 CLK2; without Complement Array tIS1 tCKO2 Input ± Output ± 33.0 41.7 41.7 50.0 MHz fMAX3 CLK1; with Complement Array tIS2 tCKO1 Input thru Complement Array ± Output ± 27.0 33.3 31.3 38.5 MHz fMAX4 CLK2; with Complement Array tIS2 tCKO2 Input thru Complement Array ± Output ± 25.0 31.3 29.4 35.7 MHz fMAX5 Internal feedback without Complement Array (CLK1 or CLK2) tCKL tCKH Register Output ± Register Intput ± 50.0 62.5 58.8 72.4 MHz fMAX6 Internal feedback with Complement Array (CLK1 or CLK2) tIS2 Register Output thru Complement Array ± Register Intput ± 40.0 50.0 45.5 55.6 MHz fCLK Minimum guaranteed clock frequency CK + CK + 50.0 62.5 58.8 72.4 MHZ NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 3. All propagation delays and setup times are measured and specified under worst case conditions. TEST LOAD CIRCUIT +5V C L R 1 R 2 GND INPUTS I15 CK OUTPUTS C 2C 1 DUT NOTE: C 1 and C2 are to bypass VCC to GND. VCC INIT/OE SP00256 VOLTAGE WAVEFORMS 90% 10% 2.5ns2.5ns 2.5ns 2.5ns 90% 10% +3.0V +3.0V tR tF MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses SP00007

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 11

1.5V 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V1.5V I0 – I15 F0 – F7 CLK OE +3V +3V +3V VOH VOL tIH tIS tCKLtCKHtIS fMAX tOD tOE tCKP SP00257 tNVCKtVCK tCKO Asynchronous Initialization ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ I0 – I15 F0 – F7 CLK INIT 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V1.5V1.5V 1.5V 1.5V +3V +3V +3V VOH VOL tCKH tCKLtIS tINIT tINITH tCKO SP00258 fMAX tCKO tIH ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ Power-On Preset 2.5V 1.5V tPPR VCC F0 – F7 CLK I0 – I15 +5V VOH VOL +3V +3V 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V tIS tCKH tVS [Fn] = 1 [F n] + 1 SP00259A

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 12

TIMING DIAGRAMS (Continued) tCKO tIH ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ Diagnostic Mode – State Register Outputs F0 – F7 1.5V tIS VOH VOL +3V 1.5V 1.5V 1.5V 8.0V 8.0V 1.5V 1.5V 1.5V 1.5V +10V +3V +3V VOH VOL I12 I0 – I11, I13 – I15 CLK Q0 – Q7 OE tCKH INTERNAL STATE REG. (PS) tSRE tSRD (Fn) (Fn+1) (Fn+1)(NS) (NS) SP00260 tCKO tRH tRJS ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ Diagnostic Mode – State Register Input Jam ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ 8.0V 8.0V I11 F0 – F7 (INPUTS) +10V +3V +3V +3V VOH VOL ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ tRJH 1.5V 1.5V 1.5V 1.5V tIS tCKH (FORCED D IN) (DIN) CLK Q P STATE REG.( ) SP00261 Diagnostic Mode—Output Register Input Jam ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ( ) Q F STATE REG. tCKO tRH tRJS 8.0V 8.0V I10 F0 – F7 (INPUTS) +10V +3V +3V +3V VOH VOL tRJH 1.5V 1.5V 1.5V 1.5V tIS tCKH (FORCED D IN) (DIN) CLK1/2 SP00243

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 13

tCKH1, 2 Width of input clock pulse. tCKP1, 2 Minimum guaranteed clock period. tIS1 Required delay between beginning of valid input and positive transition of Clock. tCKO1, 2 Delay between positive transition of Clock and when Outputs become valid (with INIT/OE Low). tPPR Delay between VCC (after power–on) and when Outputs become preset at “1”. tIS2 Required delay between beginning of valid Input and positive transition of Clock, when using optional Complement Array (two passes necessary through the AND Array). tRJH Required delay between positive transition of clock, and return of input I10, I11 or I12 from Diagnostic Mode (10V). fMAX1, 2 Minimum guaranteed operating frequency; input to output (CLK1 and CLK2). fMAX3, 4 Minimum guaranteed operating frequency; input through Complement Array, to output (CLK1 and CLK2). fMAX5 Minimum guaranteed internal operating frequency; with internal feedback from state register to state register. fMAX6 Minimum guaranteed internal operating frequency with Complement Array, with internal feedback from state register through Complement Array, to state register. fCLK Minimum guaranteed clock frequency (register toggle frequency). tCKL1, 2 Interval between clock pulses. tIH Required delay between positive transition of Clock and end of valid Input data. tOE Delay between beginning of Output Enable Low and when Outputs become valid. tSRE Delay between input I12 transition to Diagnostic Mode and when the Outputs reflect the contents of the State Register. tRJS Required delay between inputs I11, I10 or I12 transition to Diagnostic Mode (10V), and when the output pins become available as inputs. tNVCK Required delay between the negative transition of the clock and the negative transition of the Asynchronous Initialization to guarantee that the clock edge is not detected as a valid negative transition. tINITH Width of initialization input pulse. tVS Required delay between VCC (after power–on) and negative transition of Clock preceding first reliable clock pulse. tOD Delay between beginning of Output Enable High and when Outputs are in the OFF–state. tINIT Delay between positive transition of Initialization and when Outputs become valid. tSRD Delay between input I12 transition to Logic mode and when the Outputs reflect the contents of the Output Register. tRH Required delay between positive transition of Clock and end of valid Input data when jamming data into State or Output Registers in diagnostic mode. tVCK Required delay between negative transition of Asynchronous Initialization and negative transition of Clock preceding first reliable clock pulse.

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 14

The PLUS405-37/-45 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software packages. ABEL and CUPL  design software packages also support the PLUS405-37/-45 architecture. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. PLUS405-37/-45 logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only. To implement the desired logic functions, each logic variable (I, B, P, S, T, etc.) from the logic equations is assigned a symbol. TRUE, COMPLEMENT, PRESET, RESET, OUTPUT ENABLE, INACTIVE, etc., symbols are defined below. INITIALIZATION/OE OPTION – (INIT/OE) OPTION CODE LOE OPTION CODE HINITIALIZATION1 INIT (ALWAYS ENABLED) E = 1 INIT/OE INIT = 0 E INIT/OE (INITIALIZATION DISABLED) SP00265 PROGRAMMING THE PLUS405: The PLUS405 has a power-up preset feature. This feature insures that the device will power-up in a known state with all register elements (State and Output Register) at logic High (H). When programming the device it is important to realize this is the initial state of the device. You must provide a next state jump if you do not wish to use all Highs (H) as the present state. INITIALIZATION OPTION – (INIT) CODE O ACTION INDETERMINATE 4 CODEACTION CODE ACTION PRESET H RESET L CODE ACTION INDETERMINATE 4 INIT P R INIT P R INIT P R INIT P R INIT P R SP00266 “AND” ARRAY – (I), (P) CODE O STATE INACTIVE 1, 2 CODESTATE CODE STATE CODE STATE I, P H I, P L DON’T CARE – Tn i, p I, P Tn I, P Tn I, P Tn I, P Tn I, P i, p i, p i, p i, p i, p i, p i, p SP00267 Notes are on next page. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc.

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 15

“OR” ARRAY – J-K FUNCTION – (N), (F) CODEACTION CODE ACTION SET H RESET L N, F N, F Tn J Q K CODEACTION TOGGLE 1, 6 O N, F N, F Tn J Q K N, F N, F Tn J Q K N, F N, F Tn J Q K CODEACTION NO CHANGE – SP00268 “COMPLEMENT” ARRAY – (C) CODE O ACTION INACTIVE 1, 3 CODEACTION CODE ACTION CODE ACTION GENERATE A PROPAGATE • TRANSPARENT – Tn c c Tn c Tn c Tn c c c c SP00269 CLOCK OPTION – (CLK1/CLK2) OPTION CODE LCLK1 ONLY 1 CLK2 CLK1 OPTION CODE HCLK1 and CLK2 5 CLK2 CLK1 SP00270 NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate Tn will be unconditionally inhibited if any one of its I or P link pairs is left intact. 3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tn. 4. These states are not allowed when using INITIALIZATION option. 5. Input buffer I5 must be deleted from the AND array (i.e., all fuse locations “Don’t Care”) when using second clock option. 6. A single product term cannot drive more than 8 registers by itself when used in TOGGLE mode. PROGRAMMING/SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information.

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 16

NOTES: 1. The device is shipped with all links initially intact. Thus, a background of “0” for all Terms, and an “H” for the IN/E and H for the clock option, exists in the table, shown BLANK instead for clarity. 2. Unused Cn Im, and Ps bits are normally programmed Don’t Care (—). 3. Unused Transition Terms can be left blank for future code modification, or programmed as (—) for maximum speed. INACTIVE OR TOGGLE PIN NO. PIN LABELS 7 2 3 4 5 6 7 8 9 C1 C0 COMP. ARRAY INPUT (Im) AND PRESENT STATE (Ps) NEXT STATE (Ns) OR OUTPUT (Fr) CLOCK 1/2 INITIALIZATION/OUTPUT ENABLE CUSTOMER NAME PHILIPS DEVICE # CUSTOMER SYMBOLIZED P ART # CF (XXXX) REV DATE PROGRAM TABLE I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 P7 P6 P5 P4 P3 P2 P1 P0 N6 N5 N4 N3 N2 N1 N0 F7 F6 F5 F4 F3 F2 F1 F0 OPTIONSORAND INIT OE CLK1 ONLY CLK1 AND 2 H L L H INIT/OE CLK1/ CLK2 Ns, FrSET RESET NO CHANGE L H 0INACTIVE GENERATE PROPAGATE TRANSPARENT A Cn INACTIVE I, P I, P DON’T CARE H Im, PsL SP00263

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 17

SNAP RESOURCE SUMMARY DESIGNATIONS AND P63 P0 15I I/CLK J K P R Q (4) J K P R Q (4) J K P R Q (4) J K P R Q (4) F CK F INIT/OE DIN405 NIN405 JKFF405 CK405 CK405 OUT405 OUT405 NOR DIN405 NIN405 SP00264

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 18

DIP28: plastic dual in-line package; 28 leads (600 mil); long body SOT117-2

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 19

PLCC28: plastic leaded chip carrer; 28 leads; pedestal SOT261-3

Philips Semiconductors Product specification PLUS405-37/-45Programmable logic sequencers (16 × 64 × 8)

1996 Nov 12 20

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act.  Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A.