PLUS173-10 PHILIPS

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Philips Semiconductors Programmable Logic Devices Product specification PLUS173–10Programmable logic array (22 × 42 × 10) 41October 22, 1993 853–1422 11164

DESCRIPTION

The PLUS173–10 PLD is a high speed, combinatorial Programmable Logic Array. The Philips Semiconductors state-of-the-art Oxide Isolated Bipolar fabrication process is employed to produce maximum propagation delays of 10ns or less. The 24-pin PLUS173–10 device has a programmable AND array and a programmable OR array. Unlike PAL devices, 100% product term sharing is supported. Any of the 32 logic product terms can be connected to any or all of the 10 output OR gates. Most PAL ICs are limited to

7 AND terms per OR function; the

PLUS173–10 device can support up to 32 input wide OR functions. The polarity of each output is user- programmable as either Active-High or Active-Low, thus allowing AND-OR or AND-NOR logic implementation. This feature adds an element of design flexibility, particularly when implementing complex decoding functions. The PLUS173–10 device is user- programmable using one of several commercially available, industry standard PLD programmers.

FEATURES

  • I/O propagation delays – 10ns (worst case)
  • Functional superset of 20L10 and most other 24-pin combinatorial PAL devices
  • Two programmable arrays – Supports 32 input wide OR functions
  • 12 inputs
  • 10 bi-directional I/O
  • 42 AND gates – 32 logic product terms – 10 direction control terms
  • Programmable output polarity – Active-High or Active-Low
  • Security fuse
  • 3-State outputs
  • Power dissipation: 850mW (typ.)
  • TTL Compatible

APPLICATIONS

  • Random logic
  • Code converters
  • Fault detectors
  • Function generators
  • Address mapping
  • Multiplexing PIN CONFIGURATIONS 1234 12 13 14 15 16 17 18 262728 12 13 N Package I10 VCC I11GND A Package N = Plastic Dual In-Line (300mil-wide) I0I1I2I3 VCC B9 B8 NC NC I9 I10 GND I11 B0 B1 B2 NC NC A = Plastic Leaded Chip Carrier

ORDERING INFORMATION

DESCRIPTION tPD (MAX) ORDER CODE DRAWING NUMBER 24-Pin Plastic Dual In-Line 300mil-wide 10ns PLUS173–10N 0410D 28-Pin Plastic Leaded Chip Carrier 10ns PLUS173–10A 0401F  PAL is a registered trademark of Advanced Micro Devices Corporation.

Philips Semiconductors Programmable Logic Devices Product specification PLUS173–10Programmable logic array (22 × 42 × 10) October 22, 1993 42 LOGIC DIAGRAM NOTES: 1. All programmed ‘AND’ gate locations are pulled to logic “1”. 2. All programmed ‘OR’ gate locations are pulled to logic “0”. 3. Programmable connection. (LOGIC TERMS–P) (CONTROL TERMS) I10 I11 31 24 23 16 15 8 7 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0S9

Philips Semiconductors Programmable Logic Devices Product specification PLUS173–10Programmable logic array (22 × 42 × 10) October 22, 1993 43 FUNCTIONAL DIAGRAM P31 P0 D0 D9 I11 ABSOLUTE MAXIMUM RATINGS 1 THERMAL RATINGS RATING SYMBOL PARAMETER Min Max UNIT VCC Supply voltage +7 VDC VIN Input voltage +5.5 VDC VOUT Output voltage +5.5 VDC IIN Input currents –30 +30 mA IOUT Output currents +100.0 mA Tamb Operating free-air temperature range 0 +75 °C Tstg Storage temperature range –65 +150 °C NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. TEMPERATURE Maximum junction 150 °C Maximum ambient 75 °C Allowable thermal rise 75 °C ambient to junction

Philips Semiconductors Programmable Logic Devices Product specification PLUS173–10Programmable logic array (22 × 42 × 10) October 22, 1993 44 DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT Input voltage2 VIL Low VCC = MIN 0.8 V VIH High VCC = MAX 2.0 V VIC Clamp VCC = MIN, IIN = –12mA –0.8 –1.2 V Output voltage2 VCC = MIN VOL Low 4 IOL = 15mA 0.4 0.5 V VOH High5 IOH = –2mA 2.4 2.9 V Input current9 VCC = MAX IIL Low VIN = 0.45V –20 –100 µA IIH High VIN = VCC 1 40 µA Output current VCC = MAX IO(OFF) Hi-Z state8 VOUT = 2.7V 0 80 µA VOUT = 0.45V –15 –140 IOS Short circuit3, 5, 6 VOUT = 0V –15 –30 –70 mA ICC VCC supply current7 VCC = MAX 170 210 mA Capacitance VCC = 5V IIN Input VIN = 2.0V 8 pF C B I/O VB = 2.0V 15 pF NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with inputs I0 – I4 = 0V, inputs I5 – I9 = 4.5V , I11 = 4.5V and I10 = 10V. For outputs B0 – B4 and for outputs B5 – B9 apply the same conditions except I11 = 0V. 5. Same conditions as Note 4 except input I11 = +10V. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with inputs I0 – I11 and B0 – B9 = 0V . Part in Virgin State. 8. Leakage values are a combination of input and output leakage. 9. IIL and IIH limits are for dedicated inputs only (I0 – I11).

Philips Semiconductors Programmable Logic Devices Product specification PLUS173–10Programmable logic array (22 × 42 × 10) October 22, 1993 45 AC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V, R1 = 300Ω , R2 = 390Ω TEST LIMITS SYMBOL PARAMETER FROM TO CONDITION MIN TYP MAX UNIT tPD Propagation Delay2 Input +/– Output +/– C L = 30pF 8 10 ns tOE Output Enable1 Input +/– Output – C L = 30pF 8 10 ns tOD Output Disable1 Input +/– Output + C L = 5pF 8 10 ns NOTES: 1. For 3-State outputs; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 2. All propagation delays are measured and specified under worst case conditions. VOLTAGE WAVEFORM MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. 90% 10% 5ns5ns 5ns 5ns 90% 10% +3.0V +3.0V tR tF Input Pulses TIMING DEFINITIONS SYMBOL PARAMETER tPD Propagation delay between input and output. tOD Delay between input change and when output is off (Hi-Z or High). tOE Delay between input change and when output reflects specified output level. TEST LOAD CIRCUIT TIMING DIAGRAM Test Load Circuit +5V C L R 1 R 2 GND B Z B Z INPUTS In In B M B M OUTPUTS C 2C 1 DUT NOTE: C 1 and C2 are to bypass VCC to GND. VCC +3V VOH VOL I, B B tPD 1.5V 1.5V 1.5V 1.5V 1.5V tOD tOE VT

Philips Semiconductors Programmable Logic Devices Product specification PLUS173–10Programmable logic array (22 × 42 × 10) October 22, 1993 46 LOGIC PROGRAMMING The PLUS173–10 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL and CUPL /n636861723332000000000000 design software packages also support the PLUS173–10 architecture. All packages allow Boolean and state equation entry formats. SNAP , ABEL and CUPL also accept, as input, schematic capture format. PLUS173–10 logic designs can also be generated using the program table entry format, which is detailed on the following page. This program table entry format is supported by SNAP only. To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P , etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. PROGRAMMING AND SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information. AND ARRAY – (I, B) CODE O STATE INACTIVE 1, 2 CODESTATE CODE STATE CODE STATE I, B H L – P, D I, B I, B I, B I, B P, D I, B I, B I, B P, D I, B I, B I, B P, D I, B I, B I, B DON’T CARE OR ARRAY – (B) VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at “H” polarity. 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs. NOTES: 1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates Pn, Dn. 2. Any gate Pn, Dn will be unconditionally inhibited if both the true and complement of any input (I, B) are left intact. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. CODEACTIVE LEVEL LOW (INVERTING) L CODEACTIVE LEVEL HIGH 1 (NON-INVERTING) H S X B S X B OUTPUT POLARITY – (B) CODE INACTIVEA CODEPn STATUS ACTIVE 1 • P S Pn STATUS P S

Philips Semiconductors Programmable Logic Devices Product specification PLUS173–10Programmable logic array (22 × 42 × 10) October 22, 1993 47 PLA PROGRAM TABLE POLARITY PIN T E R M AND OR ACTIVE INACTIVE CONTROL HIGH LOW A INACTIVE H L B(0) (POL) DON’T CARE I, B I, B I, B(I) CUSTOMER NAME PHILIPS DEVICE # PROGRAM T ABLE # REV DATE H L VARIABLE NAME AND OR B(0) 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 B(I) 13 11 10 9 8 7 6 5 4 3 2 1 23 22 21 20 19 18 17 16 15 14 23 22 21 20 19 18 17 16 15 14 NOTES The PLA is shipped with all links intact. Thus a background (Shown BLANK for clarity.) Unused I and B bits in the AND array must be programmed Unused product terms can be left blank. Don’t Care (—). of entries corresponding to states of virgin links exists in the table. I

Philips Semiconductors Programmable Logic Devices Product specification PLUS173–10Programmable logic array (22 × 42 × 10) October 22, 1993 48 SNAP RESOURCE SUMMARY DESIGNATIONS CANDAND P31 P0 D 0 D 9 I11 OR DIN173 NIN173 EXOR173 TOUT173 DIN173 NIN173