PLUS153B PHILIPS

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Philips Semiconductors Programmable Logic Devices Product specification PLUS153B/DProgrammable logic arrays (18 × 42 × 10) 9October 22, 1993 853–1285 11164

DESCRIPTION

The PLUS153 PLDs are high speed, combinatorial Programmable Logic Arrays. The Philips Semiconductors state-of-the-art Oxide Isolated Bipolar fabrication process is employed to produce propagation delays as short as 12ns. The 20-pin PLUS153 devices have a programmable AND array and a programmable OR array. Unlike PAL devices, 100% product term sharing is supported. Any of the 32 logic product terms can be connected to any or all of the 10 output OR gates. Most PAL ICs are limited to

7 AND terms per OR function; the PLUS153

devices can support up to 32 input wide OR functions. The polarity of each output is user-programmable as either active-High or active-Low, thus allowing AND-OR or AND-NOR logic implementation. This feature adds an element of design flexibility, particularly when implementing complex decoding functions. The PLUS153 devices are user-programmable using one of several commercially available, industry standard PLD programmers.

FEATURES

  • I/O propagation delays (worst case) – PLUS153B – 15ns max. – PLUS153D – 12ns max.
  • Functional superset of 16L8 and most other 20-pin combinatorial PAL devices
  • Two programmable arrays – Supports 32 input wide OR functions
  • 8 inputs
  • 10 bi-directional I/O
  • 42 AND gates – 32 logic product terms – 10 direction control terms
  • Programmable output polarity – Active-High or Active-Low
  • Security fuse
  • 3-State outputs
  • Power dissipation: 750mW (typ.)
  • TTL Compatible

APPLICATIONS

  • Random logic
  • Code converters
  • Fault detectors
  • Function generators
  • Address mapping
  • Multiplexing PIN CONFIGURATIONS 10 11 N Package B0 B2 GND VCC 123 9 10 11 12 13 1920 A Package N = Plastic Dual In-Line Package (300mil-wide) A = Plastic Leaded Chip Carrier B2 B3B1B0 GND I1I2 B9 VCCI0

ORDERING INFORMATION

DESCRIPTION tPD (MAX) ORDER CODE DRAWING NUMBER 20-Pin Plastic Dual-In-Line 300mil-wide 15ns PLUS153BN 0408D 20-Pin Plastic Dual-In-Line 300mil-wide 12ns PLUS153DN 0408D 20-Pin Plastic Leaded Chip Carrier 15ns PLUS153BA 0400E 20-Pin Plastic Leaded Chip Carrier 12ns PLUS153DA 0400E  PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices Corporation.

Philips Semiconductors Programmable Logic Devices Product specification PLUS153B/DProgrammable logic arrays (18 × 42 × 10) October 22, 1993 10 LOGIC DIAGRAM NOTES: 1. All programmed ‘AND’ gate locations are pulled to logic “1”. 2. All programmed ‘OR’ gate locations are pulled to logic “0”. 3. Programmable connection. (LOGIC TERMS–P) (CONTROL TERMS) 31 24 23 16 15 8 7 0 D 9D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0S9

Philips Semiconductors Programmable Logic Devices Product specification PLUS153B/DProgrammable logic arrays (18 × 42 × 10) October 22, 1993 11 FUNCTIONAL DIAGRAM P31 P0 D 0 D 9 ABSOLUTE MAXIMUM RATINGS 1 THERMAL RATINGS RATING SYMBOL PARAMETER MIN MAX UNIT VCC Supply voltage +7 VDC VIN Input voltage +5.5 VDC VOUT Output voltage +5.5 VDC IIN Input currents –30 +30 mA IOUT Output currents +100 mA Tamb Operating free-air temperature range 0 +75 °C Tstg Storage temperature range –65 +150 °C NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. TEMPERATURE Maximum junction 150 °C Maximum ambient 75 °C Allowable thermal rise 75 °C ambient to junction

Philips Semiconductors Programmable Logic Devices Product specification PLUS153B/DProgrammable logic arrays (18 × 42 × 10) October 22, 1993 12 DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT Input voltage2 VIL Low VCC = MIN 0.8 V VIH High VCC = MAX 2.0 V VIC Clamp VCC = MIN, IIN = –12mA –0.8 –1.2 V Output voltage2 VCC = MIN VOL Low 4 IOL = 15mA 0.5 V VOH High5 IOH = –2mA 2.4 V Input current9 VCC = MAX IIL Low VIN = 0.45V –100 µA IIH High VIN = VCC 40 µA Output current VCC = MAX IO(OFF) Hi-Z state8 VOUT = 2.7V 80 µA VOUT = 0.45V –140 IOS Short circuit3, 5, 6 VOUT = 0V –15 –70 mA ICC VCC supply current7 VCC = MAX 150 200 mA Capacitance VCC = 5V C IN Input VIN = 2.0V 8 pF C B I/O VB = 2.0V 15 pF NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with inputs I0 – I2 = 0V, inputs I3 – I5 = 4.5V, inputs I7 = 4.5V and I6 = 10V. For outputs B0 – B4 and for outputs B5 – B9 apply the same conditions except I7 = 0V . 5. Same conditions as Note 4 except I7 = +10V. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with inputs I0 – I7 and B0 – B9 = 0V. 8. Leakage values are a combination of input and output leakage. 9. IIL and IIH limits are for dedicated inputs only (I0 – I7).

Philips Semiconductors Programmable Logic Devices Product specification PLUS153B/DProgrammable logic arrays (18 × 42 × 10) October 22, 1993 13 AC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V, R1 = 300Ω , R2 = 390Ω LIMITS SYMBOL PARAMETER FROM TO TEST PLUS153B PLUS153D UNIT CONDITION MIN TYP MAX MIN TYP MAX tPD Propagation Delay2 Input +/– Output +/– C L = 30pF 11 15 10 12 ns tOE Output Enable1 Input +/– Output – C L = 30pF 11 15 10 12 ns tOD Output Disable1 Input +/– Output + C L = 5pF 11 15 10 12 ns NOTES: 1. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 2. All propagation delays are measured and specified under worst case conditions. VOLTAGE WAVEFORMS MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. 90% 10% 5ns5ns 5ns 5ns 90% 10% +3.0V +3.0V tR tF Input Pulses TIMING DEFINITIONS SYMBOL PARAMETER tPD Propagation delay between input and output. tOD Delay between input change and when output is off (Hi-Z or High). tOE Delay between input change and when output reflects specified output level. TEST LOAD CIRCUIT TIMING DIAGRAM +5V C L R 1 R 2 GND B Z B Y INPUTS B W B X OUTPUTS C 2C 1 DUT NOTE: C 1 and C2 are to bypass VCC to GND. VCC +3V VOH VOL I, B B tPD 1.5V 1.5V 1.5V 1.5V 1.5V tOD tOE VT

Philips Semiconductors Programmable Logic Devices Product specification PLUS153B/DProgrammable logic arrays (18 × 42 × 10) October 22, 1993 14 LOGIC PROGRAMMING The PLUS153B/D is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL and CUPL  design software packages also support the PLUS153B/D architecture. All packages allow Boolean and state equation entry formats. SNAP , ABEL and CUPL also accept, as input, schematic capture format. PLUS153B/D logic designs can also be generated using the program table entry format, which is detailed on the following page. This program table entry format is supported by SNAP only. To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P , etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. PROGRAMMING AND SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/Software Support) of this data handbook for additional information. AND ARRAY – (I, B) CODE O STATE INACTIVE 1, 2 CODESTATE CODE STATE CODE STATE I, B H L – P, D I, B I, B I, B I, B P, D I, B I, B I, B P, D I, B I, B I, B P, D I, B I, B I, B DON’T CARE OR ARRAY – (B) VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at “H” polarity. 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs. NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate Pn will be unconditionally inhibited if both the true and complement of an input (either I or B) are left intact. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. CODEACTIVE LEVEL LOW (INVERTING) L CODEACTIVE LEVEL HIGH 1 (NON–INVERTING) H S X B S X B OUTPUT POLARITY – (B) CODE INACTIVEA CODEPn STATUS ACTIVE 1 • P S Pn STATUS P S

Philips Semiconductors Programmable Logic Devices Product specification PLUS153B/DProgrammable logic arrays (18 × 42 × 10) October 22, 1993 15 PROGRAM TABLE POLARITY PIN T E R M AND OR ACTIVE INACTIVE CONTROL HIGH LOW A INACTIVE H L B(0) (POL) DON’T CARE I, B I, B I, B(I) CUSTOMER NAME PHILIPS DEVICE # PROGRAM T ABLE # REV DATE H L VARIABLE NAME AND OR B(0) 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 B(I) 7 6 5 4 3 2 1 19 18 17 16 15 14 13 12 11 9 19 18 17 16 15 14 13 12 11 9 PURCHASE ORDER # CF(XXXX) CUSTOMER SYMBOLIZED P ART # TOTAL NUMBER OF P ARTS I NOTES In the unprogrammed state: Output polarity is non–inverting. Unused I and B bits in the AND array should be programmed Unused product terms in the OR array should be as Don’t Care (–). All AND gates are pulled to a logic “0” (Low). programmed as INACTIVE (o).

Philips Semiconductors Programmable Logic Devices Product specification PLUS153B/DProgrammable logic arrays (18 × 42 × 10) October 22, 1993 16 SNAP RESOURCE SUMMARY DESIGNATIONS CAND P31 P0 D 0 D 9 DIN153 NIN153 OR TOUT153 AND EXOR153 DIN153 NIN153