PLS173 PHILIPS

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Philips Semiconductors Programmable Logic Devices Product specification PLS173Programmable logic array (22 × 42 × 10) 25October 22, 1993 853–0324 11164

DESCRIPTION

The PLS173 is a two-level logic element consisting of 42 AND gates and 10 OR gates with fusible link connections for programming I/O polarity and direction. All AND gates are linked to 12 inputs (I) and 10 bidirectional I/O lines (B). These yield variable I/O gate configurations via 10 direction control gates (D), ranging from 22 inputs to 10 outputs. On-chip T/C buffers couple either True (I, B) or Complement (I, B) input polarities to all AND gates, whose outputs can be optionally linked to all OR gates. Their output polarity, in turn, is individually programmable through a set of EX-OR gates for implementing AND/OR or AND/NOR logic functions. The PLS173 is field programmable, enabling the user to quickly generate custom patterns using standard programming equipment. Order codes for this device are listed below.

FEATURES

  • I/O propagation delay: 30ns (max.)
  • 12 inputs
  • 42 AND gates
  • 10 OR gates
  • 10 bidirectional I/O lines
  • Active-High or -Low outputs
  • 42 product terms: – 32 logic terms – 10 control terms
  • Ni-Cr programmable links
  • Input loading: –100µA (max.)
  • Power dissipation: 750mW (typ.)
  • 3-State outputs
  • TTL compatible

APPLICATIONS

  • Random logic
  • Code converters
  • Fault detectors
  • Function generators
  • Address mapping
  • Multiplexing PIN CONFIGURATIONS 1234 12 13 14 15 16 17 18 262728 12 13 N Package I10 VCC I11GND A Package N = Plastic DIP (300mil-wide) I0I1I2I3 VCC B9 B8 NC NC I9 I10 GND I11 B0 B1 B2 NC NC A = Plastic Leaded Chip Carrier

ORDERING INFORMATION

DESCRIPTION ORDER CODE DRAWING NUMBER 24-Pin Plastic Dual-In-Line 300mil-wide PLS173N 0410D 28-Pin Plastic Leaded Chip Carrier PLS173A 0401F

Philips Semiconductors Programmable Logic Devices Product specification PLS173Programmable logic array (22 × 42 × 10) October 22, 1993 26 LOGIC DIAGRAM NOTES: 1. All programmed ‘AND’ gate locations are pulled to logic “1”. 2. All programmed ‘OR’ gate locations are pulled to logic “0”. 3. Programmable connection. (LOGIC TERMS–P) (CONTROL TERMS) I10 I11 31 24 23 16 15 8 7 0 D 9D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0S9

TYPICAL PRODUCT TERM: TYPICAL LOGIC FUNCTION: AT OUTPUT POLARITY = H /n636861723332000000000000 Z = P0 + P1 + P2 . . ./n636861723332000000000000 AT OUTPUT POLARITY + L /n636861723332000000000000 Z = P0 + P1 + P2 + . . ./n636861723332000000000000 NOTES: 1. For each of the 10 outputs, either function Z (Active-High) or Z (Active-Low) is available, but not both. The desired output polarity is programmed via the EX-OR gates. 2. ZX, A, B, C, etc. are user defined connections to fixed inputs (I), and bidirectional pins (B). TEMPERATURE Maximum junction 150 °C Maximum ambient 75 °C Allowable thermal rise 75 °C ambient to junction The PLS173 is also processed to military requirements for operation over the military temperature range. For specifications and ordering information, consult the Philips Semiconductors Military Data Handbook. Philips Semiconductors Programmable Logic Devices Product specification PLS173Programmable logic array (22 × 42 × 10) October 22, 1993 27 FUNCTIONAL DIAGRAM LOGIC FUNCTION P31 P0 D 0 D 9 I11 ABSOLUTE MAXIMUM RATINGS 1 THERMAL RATINGS RATING SYMBOL PARAMETER Min Max UNIT VCC Supply voltage +7 VDC VIN Input voltage +5.5 VDC VOUT Output voltage +5.5 VDC IIN Input currents –30 +30 mA IOUT Output currents +100 mA Tamb Operating free-air temperature range 0 +75 °C Tstg Storage temperature range –65 +150 °C NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

Philips Semiconductors Programmable Logic Devices Product specification PLS173Programmable logic array (22 × 42 × 10) October 22, 1993 28 DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT Input voltage2 VIL Low VCC = MIN 0.8 V VIH High VCC = MAX 2.0 V VIC Clamp3 VCC = MIN, IIN = –12mA –0.8 –1.2 V Output voltage2 VCC = MIN VOL Low 4 IOL = 15mA 0.5 V VOH High5 IOH = –2mA 2.4 V Input current9 VCC = MAX IIL Low VIN = 0.45V –100 µA IIH High VIN = VCC 40 µA Output current VCC = MAX IO(OFF) Hi-Z state8 VOUT = 5.5V 80 µA VOUT = 0.45V –140 IOS Short circuit3, 5, 6 VOUT = 0V –15 –70 mA ICC VCC supply current7 VCC = MAX 150 170 mA Capacitance VCC = 5V IIN Input VIN = 2.0V 8 pF C B I/O VB = 2.0V 15 pF NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with inputs VIL applied to I11. Pins 1–5 = 0V, Pins 6–10 = 4.5V, Pin 11 = 0V and Pin 13 = 10V . 5. Same conditions as Note 4 except Pin 11 = +10V. 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with I0 and I1 = 0V, and I2 – I11 and B0 – B9 = 4.5V. Part in Virgin State. 8. Leakage values are a combination of input and output leakage. 9. IIL and IIH limits are for dedicated inputs only (I0 – I11).

Philips Semiconductors Programmable Logic Devices Product specification PLS173Programmable logic array (22 × 42 × 10) October 22, 1993 29 AC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V, R1 = 470Ω , R2 = 1kΩ TEST LIMITS SYMBOL PARAMETER FROM TO CONDITION MIN TYP MAX UNIT tPD Propagation delay2 Input ± Output ± C L = 30pF 20 30 ns tOE Output enable1 Input ± Output – C L = 30pF 20 30 ns tOD Output disable1 Input ± Output + C L = 5pF 20 30 ns NOTES: 1. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 2. All propagation delays are measured and specified under worst case conditions. VOLTAGE WAVEFORM MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. 90% 10% 5ns5ns 5ns 5ns 90% 10% +3.0V +3.0V tR tF Input Pulses TIMING DEFINITIONS SYMBOL PARAMETER tPD Propagation delay between input and output. tOD Delay between input change and when output is off (Hi-Z or High). tOE Delay between input change and when output reflects specified output level. TEST LOAD CIRCUIT TIMING DIAGRAM +5V C L R 1 R 2 GND B Z B Y INPUTS I11 B W B X OUTPUTS C 2C 1 DUT NOTE: C 1 and C2 are to bypass VCC to GND. VCC +3V VOH VOL I, B B tPD 1.5V 1.5V 1.5V 1.5V 1.5V tOD tOE VT

Philips Semiconductors Programmable Logic Devices Product specification PLS173Programmable logic array (22 × 42 × 10) October 22, 1993 30 LOGIC PROGRAMMING The PLS173 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP, Data I/O Corporation’s ABEL , and Logical Devices Incorporated’s CUPL design software packages. All packages allow Boolean and state equation entry formats. SNAP , ABEL and CUPL also accept, as input, schematic capture format. PLS173 logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors SNAP PLD design software package. To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P , etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. PROGRAMMING AND SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/Software Support) of this data handbook for addtional information. OUTPUT POLARITY – (B) AND ARRAY – (I, B) CODE O STATE INACTIVE 1, 2 CODESTATE CODE STATE CODE STATE I, B H L – P, D I, B I, B I, B I, B P, D I, B I, B I, B P, D I, B I, B I, B P, D I, B I, B I, B DON’T CARE OR ARRAY – (B) VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at “H” polarity. 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs. NOTES: 1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates Pn, Dn. 2. Any gate Pn, Dn will be unconditionally inhibited if both the True and Complement of any input (I, B) are left intact. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. CODEACTIVE LEVEL LOW (INVERTING) L CODEACTIVE LEVEL HIGH 1 (NON-NVERTING) H S X B S X B CODE INACTIVEA CODEPn STATUS ACTIVE 1 • P S Pn STATUS P S

Philips Semiconductors Programmable Logic Devices Product specification PLS173Programmable logic array (22 × 42 × 10) October 22, 1993 31 PROGRAM TABLE POLARITY PIN T E R M AND OR ACTIVE INACTIVE CONTROL HIGH LOW A INACTIVE H L B(0) (POL) DON’T CARE I, B I, B I, B(I) CUSTOMER NAME PHILIPS DEVICE # PROGRAM T ABLE # REV DATE H L VARIABLE NAME AND OR B(0) 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 B(I) 13 11 10 9 8 7 6 5 4 3 2 1 23 22 21 20 19 18 17 16 15 14 23 22 21 20 19 18 17 16 15 14 NOTES The PLA is shipped with all links intact. Thus a background (Shown BLANK for clarity.) Unused I and B bits in the AND array must be programmed Unused product terms can be left blank. Don’t Care (—). of entries corresponding to states of virgin links exists in the table. I

Philips Semiconductors Programmable Logic Devices Product specification PLS173Programmable logic array (22 × 42 × 10) October 22, 1993 32 SNAP RESOURCE SUMMARY DESIGNATIONS CANDAND P31 P0 D 0 D 9 I11 OR DIN173 NIN173 EXOR173 TOUT173 DIN173 NIN173