PLS168 PHILIPS
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 12
Technical content
Field programmable logic sequencer (12 x 48 x 8) Product specification 1995 Jan 5 Military and Special Products Data Handbook PHILIPS Mi 7110826 0088e7b TH? | ee -
Philips Semiconductors Product specification a Field programmable logic sequencer (12 x 48 x 8) PLS168 LS FEATURES © Timing generators © Field-programmable (Ni-Cr link) © Sequential circuits © 12 True/Complement buffered inputs © Elevator controllers ® 48 programmable AND gates © Security locking systems © 29 programmable OR gates © Counters 10-bit state register « shit registers ® 4-bit shared state/output register © 4-bit output register © Transition complement array DESCRIPTION . The PLS168 is a bipolar, programmable state machine of the Mealy © Programmable asynchronous preset/output enable type. It contains logic AND-OR gate arrays with user programmable ep K connections which control the inputs of on-chip state and output sitive edge-trigger cloc! registers. These consist respectively of 10 Qp, and 4 Qy © Power-on preset to logic “1” of all registers edge-triggered, clocked S/R flip-flops, with an asynchronous preset option. © Automatic logic “HOLD” state via S/R flip-flops All flip-flops are unconditionally preset to “1” during power tum-on. © On-chip test array The AND array combines 12 external inputs, lo.11, with 10 intemal © Power: 600mW inputs, Po.9, fed back from the State register to form up to 48 transition terms (AND terms). In addition, Po-P of the internal state © TTL compatible register are brought off-chip to allow extending the output register to © 3-State outputs 8 bits, if so desired. © Single +5V supply Al transition terms can include True, False, or Don’t Care states of oo the controlling variables, and are merged in the OR array to issue ‘© 300mil-wide 24-pin DIP next-state and next-output commands to their respective registers on the log to high transition of the Clock pulse. Both True and Complement transition terms can be generated by APPLICATIONS Optional use of the intemal variable (C) from the complement array. © Interface protocols Also, if desired, the Preset input can be converted to output-enable function, as an additional user programmable option. Sequence detectors . Order codes for this device are listed in the Ordering Information © Peripheral controllers table. FUNCTIONAL DIAGRAM PIN CONFIGURATION se — + oO 24 Yoo Ht 4 > - DUPRE bZ 2's U- __ UO Oj \\ 4 BI 122] 17
8 Ey 127] Ie
Ch € — }>-fs q eB 120] to | @ 4 & 19] 10 { ) > lee! y >-{s t—OP t y > q >—Or FoiPq [10] [73] PoiPg ) > tame eno [7 Pore <-Ock 147 To SJ00001 00002
1995 Jan 5 2 853-0861 14570
Philips Semiconductors Product specification Teese Prt spctfication Field programmable logic sequencer (12 x 48 x 8) PLS168 ee FPLS LOGIC DIAGRAM pa ee A RBH RES EIN GE TER NN MMAS SINEMA ESE S LARS SRSA TAMER H Ea * PAC ee ASRHESRAMEAH AS ARR MATROU SUE SER eReKS FMNETNEETORRSA ig ee MESUE SED REGRET TOE RE TURE SEE LER SHERNCS TANT Siena ae f [; ene PUClee MER UMHS dGRd NTE SDUSHESAdERGEdsaGne T2sEete iste auaeege Up Ue pg Clg MESSARE IES RN NINTH RIRESR EEN ASRTENSENSTNNAea me saReaan
6 Bc EEE RES EEC CEE PEs PELE PEESEEREC RG Hath ieee beh
bd Hee, MERE E ASRS EAN RA EARNS EONAR RUE LIMERERM ES TERA Sen i pg pe MERGE RSW HUR HES RN EGRUTINEEHE iS ensas RO RREEEL ne fa AE a Se PEE Ee ee Co Sere 7 eS EE ESE Ee Se eee %—— PIRHEMUNSU ETN SEH RENT A SENNENEESAE RHE EROREMLGAEREumeY bind CERI RRES RC tide Seer roe eR eh rial 3 RPMsisigueMsvsisseMeseieseMuscsssrbussscssvsceres MAUS SHHPRNESERUE RUDE RHEE EUORUnROGHEER GRE sicmih Gitta HCE CEE ee eo ee ceo I|| SHUG SHARAN NEN HENNE GEE EENT ACUTE RUNEHREE SA RSOOS REN ERe Pere eee Teese gaery uGURONEGGHESH ET] gue eUoHaanEeG: FE-e:H mill BU BENS ES AE GES Ut Es BE RME HERES OURS guna UHH SGnENET Eau ie@i—t HESS He ep rt th a]| SPEDE GSE ERED ESSER ial Eee hbee hore Lb eethezhi nied > [2 9 BseeeameUSesGssteaH59 eizGEHnGHGa GENE cuimuueeaEEEDa: Hml| SAUMESG RETA U README ER ERERSRUDESNRSREUT Sa GHEE S Eat FaaRe Seer eee eaee ceuCEHmT SUuUEEUEGREEGURIHSHgRUEE-E HEM PEELE AS-Bee Pere eG CCEL ES ar Sct Cee bpreter ther bey > 7&8. BEM HEHE TRUE RHE SUHUINDEYEHA SRSA ANS cuted Seat em BB STH HUA SHUE DAES EH CSRERMRNSSERS ERE RUHL IREICHE EEE ed aol Lpars HEE EEE eee ete |_| : BEMASCCCET BR cen PPE b pPeb hiner debe neer yy | 8 rare “EHH Eee ete | ° SHR RAR MINN SHEDS GE SHO RENIN R ETON GEISER oe RET EN Te ee a ra os EH ree Ee otee |_| ° EHGRE UREN SENDER GRU NEHEIER ERB IU SUE ER OSERUUR Ge ye RAGIN EAA REMET CERN GRE EHES GER NE ANE ee CORTE Golem ° RS DHEGH MHA Ra NHSGE SERS SLUT ANS ERNU RINE cuRne Mm SnNeaKie Lh re SOB REGIS RS USHHS Sas UMESHMES ESSE ON EHU ROR RENE GUTS eames pee * LEE EEMECSS TPE Cree CET EEEErESEREBEEE TS loses CHEERS EA EAE ECE heer eee Chor een betbeh Bint rer] DHS 97 CECCCOIE ECAC PEPE CEE CEPEEEERDEEERESELEEEEE > TESS Tor rag, COCEEER SAPP ET Ca LE DPobe Seer phe bree bhi bre as © Hs | PEECLCBEC EE RES CTE ECE bebe ber tr PPPS pber ep hre yy © | 100s tare EGEE CEASE EERE ES SEA CAPPS RP TEr Ero EEE Epon eer pert > H5 er oe ar Ce ee ee eee. +—1 ox NOTES: 1, All programmed “AND” gate locations are pulled to logic “1”. 2. All programmed “OR" gate locations are pulled to logic “0”. 3, >» Programmable connection. ‘sP00190
1995 Jan 5 3
M™§ 7110826 0084278 817
Philips Semiconductors Product specification $A SpHBION Field programmable logic sequencer (12 x 48 x 8) PLS168
ORDERING INFORMATION
24-Pin Ceramic DIP 300mil-wide PLS168/BLA PIN DESCRIPTION [ PINNO. | SYMBOL NAME AND FUNCTION POLARITY 1 cK Clock: The Clock input to the state and output registers. A Low-to-High transition on | — Active-High this line is necessary to update the contents of both registers. 2-7 Wea Logic Inputs: The 11 external inputs to the AND array used to program jump condi- | Active-High/Low 18-23 tions between machine states, as determined by a given logic sequence. 7 lo Logic/Diagnostic Input: A 12th extemal logic input to the AND array, as above, Active-High/Low when exercised with standard TTL levels. When Ip is held at +10V, device outputs Fa. and Po -g reflect the contents of state register bits P. 9 (see Diagnostic Output Mode diagram on page 7). The contents of flip-flops Po - ; and Fo . 3 remain unal- tered. 13-16 Po-3 Logic/Diagnostic Outputs: Four device outputs which normally reflect the contents | — Active-High of state register bits Po . 3. When Ig is held at +10V these pins reflect (Pg - Po). 10-11 Fo-Fa Logic/Diagnostic Outputs: Two register bits (Fp - Fg) which normally reflect output Active-High register bits (Qz - Qs). When Ip is held at +10V these pins reflect (P4 - Ps).
7 PRIOE Preset or Output Enable Input: A user programmable function: Active-High (H)
- Preset: Provides an asynchronous preset to logic “1” of all state and output register bits. Preset overrides Clock, and when held High, clocking is inhibited and Po..9 and Fo. are High. Normal clocking resumes with the first full clock pulse following a High-to-Low clock transition, after Preset goes Low. «Output Enable: Provides an Output Enable function to all output buffers. Active-Low (L) 8,9 Fo-Fi Logic Output: Two device outputs which reflect output registers Qo - Qy. When Ip is. held at +10V Fo - Fy = Logic “1”. ABSOLUTE MAXIMUM RATINGS! SyMBon PARAMETER a [ow | Supply voltage ee ee Input voltage PT +t0.0 Voc | [of ouputvotegs 5 ioe [uf tnputcurremts CT TdT [io [outputeuents CdS tom Storage Temperature range a ee
1995 Jan 5 4
@® 7110826 0086279 756 mw
Philips Semiconductors Product specification eee pCO Field programmable logic sequencer (12 x 48 x 8) PLS168 eee DC ELECTRICAL CHARACTERISTICS -55°C < Ta < +125°C, 4.5V < Voc < 5.5V ‘SYMBOL PARAMETER? TEST CONDITIONS? a [min] tye? | Max | Vin High Voc = 5.5V v Vit Low Veo =4.5V v Vik Clamp* Voo = 4.5V, = -18MA v Voo = 4.5V Vox High lon = -2mA 7 Vo. Lows lo. = 9.6mA v Voc = 5.5V Na High Vj=5.5V <1 HA Ie Low V\\=0.45V -10 nA in Low (CK input) V\\=0.45V -50 HA Voc =5.5V lovorr) Hi-Z state” Voc =5.5V 60 pA Vo = 0.45V -60 HA los Short circuit4-8 Vo =0V 85 mA loc Voc supply current? Voc = 5.5V 185 mA Veo =5.0V Cw Vi=2.0V 10 pF Cour Vo =2.0V 13 pF
1995 Jan 5 5
Philips Semiconductors Product specification Field programmable logic sequencer (12 x 48 x 8) PLS168 $$ eSSSeSsSsSsssSSsSsSSSSSSSssSSsSsSSSssssssese AC ELECTRICAL CHARACTERISTICS -55°C < Ta < +125°C, 4.5V < Voc <5.5V SYMBOL PARAMETER TO LIMITS UNIT Pulse Width tokH Clock High"! Ck CK+ 40 15 tek Clock Low CK+ CK- 40 15 toke1 Period (w/o C-array) CK CK+ 95 40 toKp2 Period (w/C-array)'0 CK+ CK+ 136 60 ter Preset pulse PR PR- 40 15 tist Input'S CK+ Input+ 60 ns tise Input (through Complement array)'2. 13 CK+ Input: 100 ns tvs Power-on preset’? CkK- Voct 5 10 ns ters Preset? Ck- PR~ 5 -10 ns fim [impt® TT irpats ox 0 To Ts | Propagation Delay toKo Clock Output CK+ 15 35 toe Output Enable’? Output- OE- 20 40 top Output Disable!? Output+ OE+ 20 40 ter Preset Output+ PR+ 18 45 tper Power-on preset Output+ Vect 0) 20 Frequency of Operation fMax w/o C-array 10.5 faax® wiC-array'® 74 NOTES: 1. Stresses above those listed under “Absolute Maximum Ratings” may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other conditions above those indicated in the operational and programming specification of the device is not implied. 2. All typical values are at Veg = SV, Ta = +25°C. 3. All voltage values are with respect to network ground terminal. 4. Test one ata time. 5. Measured with Vi_ applied to OF and a logic High stored, or with Viy applied to PR. 6. Measured with a programmed logic condition for which the output is at a Low logic level, and Vi applied to PR/OE Output sink current is applied through a resistor to Voc. 7. Measured with Viy applied to PR/OE. 8. Duration of short circuit should not exceed 1 second. 9. I¢c is measured with the PR/OE input grounded, all other inputs at 4.5, ant the outputs open. 10. Guaranteed, but not tested. 14. To prevent spurious clocking, clock rise time (10% - 90%) < 30ns. 12. Not testable on unprogrammed devices. 13. Set up time must be increased with increased number of product terms programmed. Time shown is with two product terms programmed.
1995 Jan 5 6
Philips Semiconductors Product specification ees FOR SeCTTICattOn Field programmable logic sequencer (12 x 48 x 8) PLS168 ee TIMING DIAGRAMS TIMING DEFINITIONS av SYMBOL PARAMETER 15V 18 ke) w | [lew remetnpacarpae hal is wv Interval between clock pulses. 18 1.6V 13 CLK. ow Clock period - when not using Complement Fog 'CKH—*" "CK Array. -----+ v Pos 7” VT (OH tist Required delay between beginning of valid input /, and positive transition of clock. p Key ‘op “ou OE ‘cK av Clock period - when using Complement Array. ee tev ow tise Required delay between beginning of valid input and positive transition of clock, when using optional Complement array (two passes ‘s00003 necessary through the AND array). Sequential Mode tvs Required delay between Vcc (after power-on) and negative transition of clock preceding first reliable clock pulse. == ry on XIV — ters Required delay between negative transition of ‘CKP — 43v asynchronous Preset and negative transition of 1 sv fisv i i cux 18V FI Ke wv clock preceding first reliable clock pulse. KO == Kt _ Fog! Kisv iv ‘ay YOH Required delay between positive transition of Poa ; Vou clock and end of valid input data. PR 13 ¥ wT tcxo Delay between positive transition of clock and ~ ov when Outputs become valid (with PR/OE Low). ‘PRH Delay between beginning of Output Enable Low sv00004 and when Outputs become valid. Asynchronous mode Delay between beginning of Output Enable High and when Outputs are in the OFF-State. fan “sv ter Delay between positive transition of Preset and Voc when Outputs become valid at “1”. ov PPR tepr Delay between Voc (after power-on) and when === Von Outputs become preset at “1”. Fog! 18v (Frl=1 15 Fy +t} Po. Vou 0-3 KP KO : Jem | ‘Width of preset input pulse. cux - wv Lov [tux | Maximum clock frequency. —4+---— ov ICKt IS +3V foe 18 18V ov NS ‘1H $J00005 Power-On Preset
1995 Jan 5 7
Philips Semiconductors Product specification SSS Field programmable logic sequencer (12 x 48 x 8) PLS168 To LOGIC FUNCTION VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such . that: Typical State Transition: 1. PRICE option is set to PR. Thus, all outputs will be at "1", as a2 a1 ao preset by initial power-up procedure. (sn) Presenr stare 2. Alltransition terms are disabled (0). 3. All S/R flip-flop inputs are disabled (0). STATE REGISTER BBC. 4. The device can be clocked via a Test Array pre-programmed with 6.) next stare a standard test pattern, : Sp = Gg: Qy Ug) A: Bsc... NOTE: The Test Array pattern must be deleted before SET Qo: A : G2 1 Go) RB. incorporating a user program. This is accomplished RESET 1:8; <0 automatically by any Philips qualified programming MSI lap 04 -G)-K-B-C... equipment. HOLD Q2: So =0 R2=0 5400006. TRUTH TABLE!:2.3.4.5.6 H . x x x H L +10V x x x (Qe)n L x x x x (rn H . x x x Hi-Z +5V L +10 x x x (Qe) L x x Xx x (Qn L x Tt L L Qn (Qe)n L x t L H L L L x Tt H L H H L x t H H IND. IND. a a a NOTES:
1 Poste Loge SIR= 1941) +To+ + Tay
Tn = Cllo ty Ig) (Po Py. Ps) 2 Either Preset (Active-High) or Output Enablé (active-Low) are available, but not both. The desired function is a user programmable option.
3 T denotes transition trom Low to High level
4 R=S= Hah is anslegat mpat condition
5 ¢=HUHov. 6 _ X= Dont Caro (< 5 5Y TEST LOAD CIRCUITS Yoo oro P3 \\ ° : fH Ry i} OUT | : Fg Re co ° Mt il (ucLupes ScoPE 0 0 AND J CK PRIDE = = capactrance) NOTE Ry = 4700, Rg = 1KQ, CL = 50pF 900007
1995 Jan 5 8
@§ 7110826 0088283 187 a
Philips Semiconductors Product specification Field programmable logic sequencer (12 x 48 x 8) PLS168 Eee VOLTAGE WAVEFORMS LOGIC PROGRAMMING Jov The FPLS can be programmed by means of Logic programming iw + w —| iW equipment. NEGATIVE VM vm With Logic programming, the AND/OR gate input connections sv os ow necessary to implement the desired logic function are coded directly (i from the State Diagram using the Program Table on the following TTHL(tH, TLH(tr) | page. In this table, the logic state or action of control variables C, |, P, N STLH(tr) THUG, and F, associated with each Transition term T,, is assigned a symbol 2a 27v 3.0v which results in the proper fusing pattem of corresponding link pairs, ITIVE - PoLse vm Vw defined as follows: o3v o3v w ov Input Pulse Definitions INPUT PULSE CHARACTERISTICS [va enn [rue wet] tr [tm | Die [me [ston [se | oe | .$100008 PRESET/OE OPTION - (P/E) PRIDE PRIOE E=1 E (PRESET LWAYS L a rt eae >) DISABLED) a [__orrion [cove | [oprion [cove | a Le ‘ss000009 PROGRAMMING: The PS168 has a power-up preset feature. This feature insures that device it is important to realize this is the initial state of the device. the device will power-up in a known state with all register elements You must provide a next state jump if you do not wish to use all (state and output register) at logic High (H). When programming the Highs (H) as the present state. “AND” ARRAY - (1), (P) ip ip ip Mp uP ue uP uP tp Tp Tp Tp Ta Th Th Ta [stare [cove | [stare [cove | [stare [cove] [__stare_ [cove | Linacre 15 | o | Lue Lie Te [_vowrcane [= | 100010
1995 Jan 5 9
m@™ 7110826 0088284 013 a
Philips Semiconductors Product specification Field programmable logic sequencer (12 x 48 x 8) PLS168 SSS “OR” ARRAY - (N), (F) Th Th Th Th [action “cove | [_Acrion [coe] [action [cove | [__Acnion [cove] Linacrve'4.16 | 0 | a L_reser__ | it L_Nochanae [=| ‘$900017 “COMPLEMENT” ARRAY - (C) © e e é e e G c Th Th Tr Th [__acrion [cone] [Action [cone | [_Acrion [cone | [action] cove | Linacrveti7 [oo | L_cenenare a] L_proracare | ° | Ltransranent | - | ‘S100012 NOTES: 14. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused (inactive) AND gates T,. 15. Any gate T,, will be unconditionally inhibited if any one of its | or P link pairs are left intact. 16. To prevent simultaneous Set and Reset flip-flop commands, this state is not allowed for N and F link pairs coupled to active gates T, (see flip-flop truth tables). 17. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates Tp.
1995 Jan 5 10
Philips Semiconductors Product specification Field programmable logic sequencer (12 x 48 x 8) PLS168 SS FPLS PROGRAM TABLE PLS168 PROGRAM TABLE ENTRIES CUSTOMER NAME —===— Ae — 5 -___ on PURCHASE ORDER #. [inactive 79 | [inactive . 0 | PHILIPS DEVICE # CF (XXXX) pGenenate A fy fet ee CUSTOMER SYMBOLIZED PART # [PROPAGATE 7 TOTAL NUMBER OF PARTS PANSPARENT, = | PROGRAM TABLE, INACTIVE. 0 ("~~~ option — hey TT Pee ae PTW Dare Here | “ en - ; Se | Se | eee 8 ee eee ee a OO eG A a a OO a OO OO Pere a aS 6 ee ee Pee a [ry a as a ee Seo oe A a OG GO BEE EERE EEE EERE ee a Oe a A SO Ree ae a Pas EE A
2 OO OB OO OP
a eG OS GG OO | a a a a ee ee Se ee ee ee A a GG OO ee SS 66S ee a A Ree Boe = a ee — a oe ee A a ee ee ee eee Pa en i — a oe Oe Cio a a pee er Pa esol ofl BEeEttng zs ‘SPO0195
1995 Jan 5 W
@™ 7110826 0048286 996
Philips Semiconductors Product specification eee Product Sp ACication Field programmable logic sequencer (12 x 48 x 8) PLS168 eee TEST ARRAY Voc 9 +5V The FPLS may be subjected to AC and DC parametric tests prior to programming via an A) (n+ F Fn The array consists of test transition terms 48 and 49, factory programmed as shown below. Testing is accomplished by clocking the FPLS Fon (Fn Poo ros and applying the proper input sequence to In lott Fr lo-13 aS shown in the test circuit timing tock cK Fos diagram. ~~) (a+FriFin rt PRIOE_GND State Diagram = FPLS Under Test TEST ARRAY PROGRAM [—_—_erron T a é om Ti INPUT (1m) PRESENT STATE (Pa) NEXT STATE (Ns) OUTPUT (Fr) M ‘eh RTs] see Rp spe REET ye PROTA R pray Cae a Tae ee ee | eA Test Array Program anv wv vec ov we 'CKH ta iS KL Both terms 48 and 49 must be deleted during y \\| VIH user programming to avoid interfering with the ck 1.8 16V 1aev desired logic function. This is accomplished Vit automatically by any Philips qualified tH uso | nt programming equipment. wees -- Vm cate = VIL | ‘PPR tcKo ‘cKo ov Fo3 15V 18V, 15 ov — eee eeesy rot HIGH STATE . : Test Circuit Timing Diagram TEST ARRAY DELETED [error a € INPUT (Im) PRESENT STATE (Ps) NEXT STATE (Ns) OUTPUT (Fr) ‘yi M 1jolsyeyT7yey s[4]3 [2 [i] of s] 8] 7 ef 547 sy 2] 7] 0] Sep ey7 es 14] sels lolayayi yo [ae [tata tata tata tata te te Tate el ee {PP -} eS | ‘Test Array Deleted 100018