PLS153 PHILIPS

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Philips Semiconductors Programmable Logic Devices Product specification PLS153/AProgrammable logic arrays (18 × 42 × 10) 1October 22, 1993 853–0311 11164

DESCRIPTION

The PLS153 and PLS153A are two-level logic elements, consisting of 42 AND gates and 10 OR gates with fusible link connections for programming I/O polarity and direction. All AND gates are linked to 8 inputs (I) and 10 bidirectional I/O lines (B). These yield variable I/O gate configurations via 10 direction control gates (D), ranging from 18 inputs to 10 outputs. On-chip T/C buffers couple either True (I, B) or Complement (I, B) input polarities to all AND gates, whose outputs can be optionally linked to all OR gates. Their output polarity, in turn, is individually programmable through a set of EX-OR gates for implementing AND/OR or AND/NOR logic functions. The PLS153 and PLS153A are field-programmable, enabling the user to quickly generate custom patterns using standard programming equipment.

FEATURES

  • Field-Programmable (Ni-Cr links)
  • 8 inputs
  • 42 AND gates
  • 10 OR gates
  • 10 bidirectional I/O lines
  • Active-High or -Low outputs
  • 42 product terms: – 32 logic terms – 10 control terms
  • I/O propagation delay: – PLS153: 40ns (max) – PLS153A: 30ns (max)
  • Input loading: –100µA (max)
  • Power dissipation: 650mW (typ)
  • 3-State outputs
  • TTL compatible

APPLICATIONS

  • Random logic
  • Code converters
  • Fault detectors
  • Function generators
  • Address mapping
  • Multiplexing PIN CONFIGURA TIONS 10 11 N Package B 0 B 2 GND B 3 B 4 B 5 B 6 B 7 B 8 B 9 VCC B 1 123 9 10 11 12 13 1920 A Package N = Plastic DIP (300mil-wide) A = Plastic Leaded Chip Carrier B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9VCC B 1 I0I1I2 B 0 GND SP00274

ORDERING INFORMATION

DESCRIPTION ORDER CODE DRAWING NUMBER 20-Pin Plastic Dual In-Line, 300mil-wide PLS153N, PLS153AN 0408B 20-Pin Plastic Leaded Chip Carrier PLS153A, PLS153AA 0400E

Philips Semiconductors Programmable Logic Devices Product specification PLS153/AProgrammable logic arrays (18 × 42 × 10) October 22, 1993 2 LOGIC DIAGRAM NOTES: 1. All programmed ‘AND’ gate locations are pulled to logic “1”. 2. All programmed ‘OR’ gate locations are pulled to logic “0”. 3. Programmable connection. (LOGIC TERMS–P) (CONTROL TERMS) 31 24 23 16 15 8 7 0 D 9D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0S9 SP00276

Philips Semiconductors Programmable Logic Devices Product specification PLS153/AProgrammable logic arrays (18 × 42 × 10) October 22, 1993 3 FUNCTIONAL DIAGRAM P31 P0 D 0 D 9 B 0 B 9 B 9 B 0 SP00277 ABSOLUTE MAXIMUM RA TINGS 1 RATINGS SYMBOL PARAMETER MIN MAX UNIT VCC Supply voltage +7 VDC VIN Input voltage +5.5 VDC VOUT Output voltage +5.5 VDC IIN Input currents –30 +30 mA IOUT Output currents +100 mA Tamb Operating temperature range 0 +75 °C Tstg Storage temperature range –65 +150 °C NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

Philips Semiconductors Programmable Logic Devices Product specification PLS153/AProgrammable logic arrays (18 × 42 × 10) October 22, 1993 4 LOGIC FUNCTION NOTES: 1. For each of the 10 outputs, either function Z (Active-High) or Z (Active-Low) is available, but not both. The desired output polarity is programmed via the Ex-OR gates. 2. Z, A, B, C, etc. are user defined connections to fixed inputs (I) and bidirectional pins (B). TYPICAL PRODUCT TERM: TYPICAL LOGIC FUNCTION: AT OUTPUT POLARITY = H AT OUTPUT POLARITY = L SP00275 THERMAL RATINGS TEMPERATURE Maximum junction 150 C Maximum ambient 75 C Allowable thermal rise ambient to junction 75 C The PLS153/A devices are also processed to military requirements for operation over the military temperature range. For specifications and ordering information consult the Philips Semiconductors Military Data Handbook. DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT Input voltage2 VIL Low VCC = MIN 0.8 V VIH High VCC = MAX 2.0 V VIC Clamp3 VCC = MIN, IIN = –12mA –0.8 –1.2 V Output voltage2 VCC = MIN VOL Low 4 IOL = 15mA 0.5 V VOH High5 IOH = –2mA 2.4 V Input current9 VCC = MAX IIL Low VIN = 0.45V –100 µA IIH High VIN = 5.5V 40 µA Output current VCC = MAX IO(OFF) Hi-Z state8 VOUT = 5.5V 80 µA VOUT = 0.45V –140 IOS Short circuit3, 5, 6 VOUT = 0V –15 –70 mA ICC VCC supply current7 VCC = MAX 130 155 mA Capacitance VCC = 5V C IN Input VIN = 2.0V 8 pF C B I/O VB = 2.0V 15 pF NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one at a time. 4. Measured with +10V applied to I7. 5. Measured with +10V applied to I0–7. Output sink current is supplied through a resistor to VCC . 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with I0, I1 at 0V, I2 – I7 and B0–9 at 4.5V. 8. Leakage values are a combination of input and output leakage. 9. IIL and IIH limits are for dedicated inputs only (I0 – I7).

Philips Semiconductors Programmable Logic Devices Product specification PLS153/AProgrammable logic arrays (18 × 42 × 10) October 22, 1993 5 AC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V, R1 = 300Ω , R2 = 390Ω LIMITS SYMBOL PARAMETER FROM TO TEST PLS153 PLS153A UNIT CONDITION MIN TYP 1 MAX MIN TYP 1 MAX tPD Propagation delay Input ± Output ± C L = 30pF 30 40 20 30 ns tOE Output enable2 Input ± Output – C L = 30pF 25 35 20 30 ns tOD Output disable2 Input ± Output + C L = 5pF 25 35 20 30 ns NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 3. All propagation delays are measured and specified under worst case conditions. VOLTAGE WAVEFORMS 90% 10% 5ns5ns 5ns 5ns 90% 10% +3.0V +3.0V tR tF MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. Input Pulses SP00017 TIMING DEFINITIONS SYMBOL PARAMETER tPD Propagation delay between input and output. tOD Delay between input change and when output is off (Hi-Z or High). tOE Delay between input change and when output reflects specified output level. TEST LOAD CIRCUIT +5V C L R 1 R 2 GND B Z B Y INPUTS B W B X OUTPUTS C 2C 1 DUT NOTE: C 1 and C2 are to bypass VCC to GND. VCC SP00278

Philips Semiconductors Programmable Logic Devices Product specification PLS153/AProgrammable logic arrays (18 × 42 × 10) October 22, 1993 6 TIMING DIAGRAM +3V VOH VOL I, B B tPD 1.5V 1.5V 1.5V 1.5V 1.5V tOD tOE VT SP00279 LOGIC PROGRAMMING The PLS153/A is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP , Data I/O’s ABEL and Logical Devices, Inc. CUPL design software packages. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. PLS153/A logic designs can also be generated using the program table entry format detailed on the following page. This program table entry format is supported by the Philips Semiconductors SNAP PLD design software package. To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT , INACTIVE, PRESET, etc., are defined below. PROGRAMMING/SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/ Software Support) of this data handbook for additional information OUTPUT POLARITY – (B) CODEACTIVE LEVEL LOW (INVERTING) L CODEACTIVE LEVEL HIGH 1 (NON–INVERTING) H S X B S X B SP00280 AND ARRAY – (I, B) CODE O STATE INACTIVE 1, 2 CODESTATE CODE STATE CODE STATE I, B H L – P, D I, B I, B I, B I, B P, D I, B I, B I, B P, D I, B I, B I, B P, D I, B I, B I, B DON’T CARE SP00281 ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc.

Philips Semiconductors Programmable Logic Devices Product specification PLS153/AProgrammable logic arrays (18 × 42 × 10) October 22, 1993 7 OR ARRAY – (B) CODE INACTIVEA CODEPn STATUS ACTIVE 1 • P S Pn STATUS P S SP00282 NOTES: 1. This is the initial unprogrammed state of all links. 2. Any gate Pn will be unconditionally inhibited if both the True and Complement of an input (either I or B) are left intact. VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at “H” polarity. 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs. CAUTION: PLS153A TEST COLUMNS The PLS153A incorporates two columns not shown in the logic block diagram. These columns are used for in-house testing of the device in the unprogrammed state. These columns must be disabled prior to using the PLS153A in your application. If you are using a Philips Semiconductors-approved programmer, the disabling is accomplished during the device programming sequence. If these columns are not disabled, abnormal operation is possible. Furthermore, because of these test columns, the PLS153A cannot be programmed using the programmer algorithm for the PLS153.

Philips Semiconductors Programmable Logic Devices Product specification PLS153/AProgrammable logic arrays (18 × 42 × 10) October 22, 1993 8 PROGRAM TABLE POLARITY PIN T E R M AND OR ACTIVE INACTIVE CONTROL HIGH LOW A INACTIVE H L B(0) (POL) DON’T CARE I, B I, B I, B(I) CUST OMER NAME PHILIPS DEVICE # PROGRAM TABLE # REV DATE H L VARIABLE NAME AND OR B(0) 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 B(I) 7 6 5 4 3 2 1 19 18 17 16 15 14 13 12 11 9 19 18 17 16 15 14 13 12 11 9 PURCHASE ORDER # CF(XXXX) CUST OMER SYMBOLIZED P ART # TOTAL NUMBER OF PARTS I NOTES In the unprogrammed state: Output polarity is non–inverting. Unused I and B bits in the AND array should be programmed Unused product terms in the OR array should be as Don’t Care (–). All AND gates are pulled to a logic “0” (Low). programmed as INACTIVE (o). SP00283

Philips Semiconductors Programmable Logic Devices Product specification PLS153/AProgrammable logic arrays (18 × 42 × 10) October 22, 1993 9 SNAP RESOURCE SUMMAR Y DESIGNA TIONS CAND P31 P0 D 0 D 9 DIN153 NIN153 OR TOUT153 AND EXOR153 DIN153 NIN153 SP00284