PLS100 PHILIPS

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Philips Semiconductors Programmable Logic Devices Product specification PLS100/PLS101Programmable logic arrays (16 × 48 × 8) 49October 22, 1993 853–0308 11164

DESCRIPTION

The PLS100 (3-State) and PLS101 (Open Collector) are bipolar, fuse Programmable Logic Arrays (PLAs). Each device utilizes the standard AND/OR/Invert architecture to directly implement custom sum of product equations. Each device consists of 16 dedicated inputs and 8 dedicated outputs. Each output is capable of being actively controlled by any or all of the 48 product terms. The True, Complement, or Don’t Care condition of each of the 16 inputs and be ANDed together to comprise one P-term. All 48 P-terms can be selectively ORed to each output. The PLS100 and PLS101 are fully TTL compatible, and chip enable control for expansion of input variables and output inhibit. They feature either Open Collector or 3-State outputs for ease of expansion of product terms and application in bus-organized systems. Order codes are listed in the Ordering Information T able.

FEATURES

  • Field-programmable (Ni-Cr link)
  • Input variables: 16
  • Output functions: 8
  • Product terms: 48
  • I/O propagation delay: 50ns (max.)
  • Power dissipation: 600mW (typ.)
  • Input loading: –100µA (max.)
  • Chip Enable input
  • Output option: – PLS100: 3-State – PLS101: Open-Collector
  • Output disable function: – 3-State: Hi-Z – Open-Collector: High

APPLICATIONS

  • CRT display systems
  • Code conversion
  • Peripheral controllers
  • Function generators
  • Look-up and decision tables
  • Microprogramming
  • Address mapping
  • Character generators
  • Data security encoders
  • Fault detectors
  • Frequency synthesizers
  • 16-bit to 8-bit bus interface
  • Random logic replacement PIN CONFIGURATIONS 14 15 N Package FE * GND VCC I10 I11 I12 I14 CE I15 I13 1234 12 13 14 15 16 17 18 262728 FE A Package I7I6I5 F5 F4 GND F2 F1 F0 I9I8VCC CE I10 I11 I12 I14 I15 I13 * Fuse Enable Pin: It is recommended that this pin be left open or connected to ground during normal operation. N = Plastic DIP (600mil-wide) A = Plastic Leaded Chip Carrier

ORDERING INFORMATION

DESCRIPTION 3-STATE OPEN COLLECTOR DRAWING NUMBER 28-Pin Plastic Dual In-Line 600mil-wide PLS100N PLS101N 0413D 28-Pin Plastic Leaded Chip Carrier PLS100A PLS101A 0401F

Philips Semiconductors Programmable Logic Devices Product specification PLS100/PLS101Programmable logic arrays (16 × 48 × 8) October 22, 1993 50 LOGIC DIAGRAM NOTES: 1. All AND gate inputs with a blown link float to a logic “1”. 2. All OR gate inputs with a blown fuse float to logic “0”. 3. Programmable connection. (LOGIC TERMS–P) 47 40 39 32 31 24 23 16 8 7 0 I10 I11 I12 I13 I14 I15

19 CE15

Philips Semiconductors Programmable Logic Devices Product specification PLS100/PLS101Programmable logic arrays (16 × 48 × 8) October 22, 1993 51 FUNCTIONAL DIAGRAM I15 TYPICAL CONNECTION TYPICAL CONNECTION P0 P1 P47 CE ABSOLUTE MAXIMUM RATINGS 1 SYMBOL PARAMETER RATINGS UNIT VCC Supply voltage +7.0 VDC VIN Input voltage +5.5 VDC VO Output voltage +5.5 VDC IIN Input current ±30 mA IOUT Output current +100 mA Tamb Operating temperature range 0 to +75 °C Tstg Storage temperature range –65 to +150 °C NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other conditions above those indicated in the operational and programming specification of the device is not implied. THERMAL RATINGS TEMPERATURE Maximum junction 150°C Maximum ambient 75°C Allowable thermal rise ambient to junction 75°C The PLS100 device is also processed to military requirements for operation over the military temperature range. For specifications and ordering information consult the Philips Semiconductors Military Data Handbook.

Philips Semiconductors Programmable Logic Devices Product specification PLS100/PLS101Programmable logic arrays (16 × 48 × 8) October 22, 1993 52 DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT Input voltage2 VIH High VCC = MAX 2.0 V VIL Low VCC = MIN 0.8 V VIC Clamp3 VCC = MIN, IIN = –12mA –0.8 –1.2 V Output voltage2 VCC = MIN VOH High (PLS100)4 IOH = –2mA 2.4 V VOL Low 5 IOL = 9.6mA 0.35 0.45 V Input current IIH High VIN = 5.5V < 1 25 µA IIL Low VIN = 0.45V –10 –100 µA Output current IO(OFF) Hi-Z state (PLS100) CE = High, VCC = MAX VOUT = 5.5V 1 40 µA VOUT = 0.45V –1 –40 µA IOS Short circuit (PLS100)3, 6 CE = Low, VOUT = 0V –15 –70 mA ICC VCC supply current7 VCC = MAX 120 170 mA Capacitance CE = High, VCC = 5.0V C IN Input VIN = 2.0V 8 pF C OUT Output VOUT = 2.0V 17 pF NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Test one pin at a time. 4. Measured with VIL applied to CE and a logic high stored. 5. Measured with a programmed logic condition for which the output test is at a low logic level. Output sink current is applied through a resistor to VCC . 6. Duration of short circuit should not exceed 1 second. 7. ICC is measured with the Chip Enable input grounded, all other inputs at 4.5V and the outputs open.

ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ INPUT F0 – F7 CE 1.5V 1.5V 1.5V 1.5V 1.5V tPD tCE tCD VOL VOH +3.0V +3.0V Read Cycle Philips Semiconductors Programmable Logic Devices Product specification PLS100/PLS101Programmable logic arrays (16 × 48 × 8) October 22, 1993 53 AC ELECTRICAL CHARACTERISTICS 0°C < Tamb < +75°C, 4.75 < VCC < 5.25V, R1 = 470Ω , R2 = 1kΩ LIMITS SYMBOL PARAMETER TO FROM MIN TYP 1 MAX UNIT Propagation delay2 tPD Input Output Input 35 50 ns tCE Chip Enable3 Output Chip Enable 15 30 ns Disable time tCD Chip Disable3 Output Chip Enable 15 30 ns NOTES: 1. All typical values are at VCC = 5V. Tamb = +25°C. 2. All propagation delays are measured and specified under worst case conditions. 3. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. VOLTAGE WAVEFORMS TEST LOAD CIRCUIT MEASUREMENTS: All circuit delays are measured at the +1.5V level of in- puts and outputs, unless otherwise specified. 90% 10% 5ns5ns 5ns 5ns 90% 10% +3.0V +3.0V tR tF Input Pulses +5V C L R 1 R 2 GND INPUTS I15 CE OUTPUTS C 2C 1 DUT NOTE: C 1 and C2 are to bypass VCC to GND. VCC TIMING DEFINITIONS SYMBOL PARAMETER tCE Delay between beginning of Chip Enable Low (with Input valid) and when Data Output becomes valid. tCD Delay between when Chip Enable becomes High and Data Output is in off state (Hi-Z or High). tPD Delay between beginning of valid Input (with Chip Enable Low) and when Data Output becomes valid. TIMING DIAGRAM

Philips Semiconductors Programmable Logic Devices Product specification PLS100/PLS101Programmable logic arrays (16 × 48 × 8) October 22, 1993 54 LOGIC PROGRAMMING PLS100/PLS101 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors’ SNAP, Data I/O Corporation’s ABEL and Logical Devices Inc.’s CUPL design software packages. All packages allow Boolean and state equation entry formats. SNAP , ABEL and CUPL also accept, as input, schematic capture format. PLS100/PLS101 logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the Philips Semiconductors’ SNAP PLD design software package. To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P , etc.) is assigned a symbol. The sumbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. PROGRAMMING AND SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this dat handbook for additional informational. OUTPUT POLARITY – (F) CODEACTIVE LEVEL LOW (INVERTING) H S X O , B CODEACTIVE LEVEL HIGH 1 (NON-INVERTING) L S F “AND” ARRAY – (I) CODESTATE INACTIVE 1,2 O P I I I CODE STATE DON’T CARE CODESTATE CODE STATE I H L P I I I P I I I P I I I I “OR” ARRAY – (F) CODE INACTIVEA CODEPn STATUS ACTIVE 1 • P S P S Pn STATUS NOTES: 1. This is the initial unprogrammed state of all links. It is normally associated with all unused (inactive) AND gates Pn. 2. Any gate Pn will be unconditionally inhibited if any one of its (I) link pairs is left intact. VIRGIN STATE The PLS100/101 virgin devices are factory shipped in an unprogrammed state, with all fuses intact, such that: 1. All Pn terms are disabled (inactive) in the AND array. 2. All Pn terms are active in the OR array. 3. All outputs are Active-High. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc.

Philips Semiconductors Programmable Logic Devices Product specification PLS100/PLS101Programmable logic arrays (16 × 48 × 8) October 22, 1993 55 PROGRAM TABLE POLARITY OR OUTPUT (F P) AND INPUT (Im ) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 T E R M PIN NO. 20 21 22 23 24 25 26 27 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 VARIABLE NAME CUSTOMER NAME PURCHASE ORDER # PHILIPS DEVICE # CF (XXXX) CUSTOMER SYMBOLIZED P ART # TOTAL NUMBER OF P ARTS PROGRAM T ABLE # REV DATE PROGRAM T ABLE ENTRIES INPUT VARIABLE OUTPUT FUNCTION OUTPUT ACTIVE LEVEL Im Im Don’t Care H L – (dash) NOTE Enter (–) for unused inputs of used P-terms. Prod. Term Present in Fp Prod. Term Not Present in Fp A H L Active High Active Low (period) NOTES NOTES 1. Entries independent of output polarity. 2. Enter (A) for unused outputs of used P-terms. 1. Polarity programmed once only. 2. Enter (H) for all unused outputs.

Philips Semiconductors Programmable Logic Devices Product specification PLS100/PLS101Programmable logic arrays (16 × 48 × 8) October 22, 1993 56 SNAP RESOURCE SUMMARY DESIGNATIONS I15 P0 P1 P47 CE TOUT100 EXOR100 AND DIN100 NIN100 OR NOE100