PHU66NQ03LT NXP
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 13
Technical content
- Product profile
1.1 General description
Logic level N-channel enhancement mode field effect transistor in a plastic package using TrenchMOS™ technology.
1.2 Features
1.3 Applications
1.4 Quick reference data
- Pinning information PHP/PHU66NQ03LT N-channel TrenchMOS™ logic level FET Rev. 06 — 12 August 2004 Product data sheet ■ Logic level threshold ■ Low on-state resistance. ■ DC-to-DC converters ■ General purpose switching. ■ VDS ≤ 25 V ■ ID ≤ 66 A ■ R DSon ≤ 10.5 mΩ ■ Q gd = 3.6 nC (typ). Table 1: Discrete pinning Pin Description Simplified outline Symbol 1 gate (g) SOT78 (TO-220AB) SOT533 (I-PAK) 2 drain (d) 3 source (s) mb mounting base; connected to drain (d) mb Top view s d g mbb076
9397 750 13428 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 06 — 12 August 2004 2 of 13 Philips Semiconductors PHP/PHU66NQ03LT N-channel TrenchMOS™ logic level FET 3. Ordering information 4. Limiting values Table 2: Ordering information Type number Package Name Description Version PHP66NQ03LT TO-220AB Plastic single-ended package; heatsink mounted; 1 mounting hole; 3 lead TO-220AB SOT78 PHU66NQ03LT I-PAK Plastic single-ended package (Philips version of I-PAK); 3 leads (in-line) SOT533 Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj≤ 175 °C - 25 V VDGR drain-gate voltage (DC) 25 °C ≤ Tj≤ 175 °C; RGS =2 0kΩ -2 5 V VGS gate-source voltage (DC) - ±20 V ID drain current (DC) T mb =2 5°C; VGS =5V ;Figure2 and 3 -5 7 A Tmb = 100°C; VGS =5V ;Figure2 -4 0 A Tmb =2 5°C; VGS =1 0V - 6 6 A Tmb = 100°C; VGS =1 0V - 4 5 A IDM peak drain current T mb =2 5°C; pulsed; tp ≤ 10 µs;Figure3 - 228 A Ptot total power dissipation T mb =2 5°C; Figure1 -9 3 W Tstg storage temperature −55 +175 °C Tj junction temperature −55 +175 °C Source-drain diode I S source (diode forward) current (DC) Tmb =2 5°C - 57 A ISM peak source (diode forward) current Tmb =2 5°C; pulsed; tp ≤ 10 µs - 228 A Avalanche ruggedness E DS(AL)S non-repetitive drain-source avalanche energy unclamped inductive load; ID =4 3A ; tp = 0.15 ms; VDD ≤ 25 V; RGS =5 0Ω ; VGS = 10 V; starting at Tj=2 5°C -9 0 m J
9397 750 13428 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 06 — 12 August 2004 3 of 13 Philips Semiconductors PHP/PHU66NQ03LT N-channel TrenchMOS™ logic level FET Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. Tmb =2 5°C; IDM is single pulse; VGS =5V Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 03aa16 120 0 50 100 150 200 Tmb (°C) Pder (%) 03aa24 120 0 50 100 150 200 Tmb (°C) Ider (%) P der P tot P tot 25 C°() ID I D2 5C°() 03ag19 102 103 1 10 10 2 VDS (V) ID (A) tp = 10 µ s DC 100 ms 10 ms Limit RDSon = VDS / ID 1 ms 100 µ s
9397 750 13428 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 06 — 12 August 2004 4 of 13 Philips Semiconductors PHP/PHU66NQ03LT N-channel TrenchMOS™ logic level FET 5. Thermal characteristics
5.1 Transient thermal impedance
Table 4: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit R th(j-mb) thermal resistance from junction to mounting baseFigure4 - - 1.6 K/W R th(j-a) thermal resistance from junction to ambient SOT78 vertical in free air - 60 - K/W SOT533 - 70 - K/W Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. 03ag18 10-2 10-1 10-5 10-4 10-3 10-2 10-1 1 10 tp (s) Zth(j-mb) (K/W) single pulse δ = 0.5 0.2 0.1 0.05 0.02 tp T P t tp Tδ =
9397 750 13428 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 06 — 12 August 2004 5 of 13 Philips Semiconductors PHP/PHU66NQ03LT N-channel TrenchMOS™ logic level FET 6. Characteristics Table 5: Characteristics Tj=2 5°C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V (BR)DSS drain-source breakdown voltage ID = 250µA; VGS =0V Tj=2 5°C 2 5 --V Tj= −55 °C 2 2 --V VGS(th) gate-source threshold voltage ID = 1 mA; VDS =V GS ;Figure9 and 10 Tj=2 5°C 1 1.5 2 V IDSS drain-source leakage current V DS =2 5V ; VGS =0V Tj=2 5°C --1 0 µA Tj= 175°C - - 500 µA IGSS gate-source leakage current V GS = ±15 V; VDS = 0 V - 10 100 nA R DSon drain-source on-state resistance VGS = 10 V; ID =2 5A ;Figure6 and 8 Tj=2 5°C - 9.1 10.5 m Ω Tj= 175°C - 16.4 18.9 m Ω VGS =5V ; ID =2 5A ;Figure6 and 8 - 11.2 13.6 m Ω Dynamic characteristics Q g(tot) total gate charge I D = 50 A; VDS =1 5V ; VGS =5V ; Figure11 -1 2 -n C Q gs gate-source charge - 4.5 - nC Q gd gate-drain (Miller) charge - 3.6 - nC C iss input capacitance V GS =0V ; VDS = 25 V; f = 1 MHz; Figure13 - 860 - pF C oss output capacitance - 330 - pF C rss reverse transfer capacitance - 145 - pF td(on) turn-on delay time V DS =1 5V ; RL = 0.6Ω ; VGS =5V ;R G = 5.6Ω - 1 52 5n s tr rise time - 90 135 ns td(off) turn-off delay time - 25 40 ns tf fall time - 2 54 0n s Source-drain diode V SD source-drain (diode forward) voltage IS = 25 A; VGS =0V ;Figure12 - 0.95 1.2 V trr reverse recovery time I S = 10 A; dIS/dt =−100 A/µs; VGS =0V ;V R =2 5V -3 2 -n s Q r recovered charge - 20 - nC
9397 750 13428 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 06 — 12 August 2004 6 of 13 Philips Semiconductors PHP/PHU66NQ03LT N-channel TrenchMOS™ logic level FET Tj=2 5°CT j=2 5°C Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Drain-source on-state resistance as a function of drain current; typical values. Tj=2 5°C and 175°C; VDS > ID xR DSon Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. 03ag20 0 0.5 1 1.5 2 V DS (V) ID (A)
5 VTj = 25 °C
VGS = 3 V 10 V 3.5 V 6 V 4 V 4.5 V 03ag21 0 2 04 06 08 0 ID (A) R DSon (mΩ ) VGS = 4.5 V Tj = 25 °C 10 V 6 V 03ag22 012345 V GS (V) ID (A) VDS > ID x RDSon Tj = 25 °C175 °C 03af18 0.5 1.5 -60 0 60 120 180 Tj (°C) a a R DSon R DSon 25 C°()
9397 750 13428 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 06 — 12 August 2004 7 of 13 Philips Semiconductors PHP/PHU66NQ03LT N-channel TrenchMOS™ logic level FET ID = 1 mA; VDS =V GS Tj=2 5°C; VDS =5V Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. ID = 50 A; VDS =1 5V Fig 11. Gate-source voltage as a function of gate charge; typical values. 03aa33 0.5 1.5 2.5 -60 0 60 120 180 Tj (°C) VGS(th) (V) max typ min 03aa36 10-6 10-5 10-4 10-3 10-2 10-1 0123 VGS (V) ID (A) maxtypmin 03ag25 0 1 02 03 0 Q G (nC) VGS (V) Tj = 25 °C ID = 50 A VDD = 15 V
9397 750 13428 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 06 — 12 August 2004 8 of 13 Philips Semiconductors PHP/PHU66NQ03LT N-channel TrenchMOS™ logic level FET Tj=2 5°C and 175°C; VGS =0V V GS = 0 V; f = 1 MHz Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 03ag23 0 0.3 0.6 0.9 1.2 V SD (V) IS (A) Tj = 25 °C175 °C VGS = 0 V 03ag24 102 103 104 10-1 1 10 10 2 VDS (V) C (pF) C iss C oss C rss
9397 750 13428 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 06 — 12 August 2004 9 of 13 Philips Semiconductors PHP/PHU66NQ03LT N-channel TrenchMOS™ logic level FET 7. Package outline Fig 14. SOT78 (TO-220AB) package outline. REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT78 SC-46 3-lead TO-220AB D D 1 q p L 123 L1(1) e e b 0 5 10 mm scale Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78 DIMENSIONS (mm are the original dimensions) AE c Note 1. Terminals in this zone are not tinned. Q UNIT A 1 b1 D 1 e p mm 2.54 qQA b Dc L2 max. 3.0 3.8 3.6 15.0 13.5 3.30 2.79 3.0 2.7 2.6 2.2 0.7 0.4 15.8 15.2 0.9 0.6 1.3 1.0 4.5 4.1 1.39 1.27 6.4 5.9 10.3 9.7 L1(1)E L 01-02-16 03-01-22 mounting base
9397 750 13428 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 06 — 12 August 2004 10 of 13 Philips Semiconductors PHP/PHU66NQ03LT N-channel TrenchMOS™ logic level FET Fig 15. SOT533 (I-PAK) package outline. REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT533 99-02-18TO-251 0 2.5 5 mm scale Plastic single-ended package (Philips version of I-PAK); 3 leads (in-line) SOT533 UNIT D e QLc e1A 2.285mm 2.38 2.22 7.28 6.94 A 1 0.89 0.71 b 0.89 0.71 0.56 0.46 E1D 1 1.06 0.96 E 6.73 6.47 5.36 5.26 4.57 9.8 9.4 1.00 1.10 DIMENSIONS (mm are the original dimensions) D D 1 L 123 mounting base e Q b AE E1 A1 cw M
9397 750 13428 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 06 — 12 August 2004 11 of 13 Philips Semiconductors PHP/PHU66NQ03LT N-channel TrenchMOS™ logic level FET 8. Revision history Table 6: Revision history Document ID Release date Data sheet status Change notice Document number Supersedes PHP_PHU66NQ03LT_6 20040812 Product data sheet - 9397 750 13428 PHP_PHB_PHD66NQ03LT_5 Modifications: • Removal of PHB66NQ03LT (now in separate data sheet)
- Removal of PHD66NQ03LT (now in separate data sheet)
- Addition of PHU66NQ03LT.
- Data sheet updated to latest standard. PHP_PHB_PHD66NQ03LT_5 20040415 Product data sheet - 9397 750 13107 PHP_PHB_PHD66NQ03LT_4 PHP_PHB_PHD66NQ03LT_4 20020909 Product data sheet - 9397 750 10158 PHP_PHB_PHD66NQ03LT_3 PHP_PHB_PHD66NQ03LT_3 20020312 Product data sheet - 9397 750 09284 PHP_PHB_PHD66NQ03LT_2 PHP_PHB_PHD66NQ03LT_2 20011210 Product data sheet - 9397 750 09119 PHP_PHB_PHD66NQ03LT_1 PHP_PHB_PHD66NQ03LT_1 20011012 Product data sheet - 9397 750 08725 -
Philips Semiconductors PHP/PHU66NQ03LT N-channel TrenchMOS™ logic level FET 9397 750 13428 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 06 — 12 August 2004 12 of 13 9. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 10. Definitions Short-form specification —The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 11. Disclaimers Life support —These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes —Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 12. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. 13. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
© Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 12 August 2004 Document order number: 9397 750 13428 Published in The Netherlands Philips Semiconductors PHP/PHU66NQ03LT N-channel TrenchMOS™ logic level FET 14. Contents