PHU108NQ03LT NXP
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
- Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS™ technology.
1.2 Features
1.3 Applications
1.4 Quick reference data
- Pinning information [1] It is not possible to make a connection to pin 2 of the SOT404 and SOT428 packages. PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET Rev. 03 — 18 April 2005 Product data sheet ■ Logic level threshold ■ Very low on-state resistance ■ Lead-free construction ■ Low gate charge ■ DC-to-DC converter ■ Switch-mode power supplies ■ VDS ≤ 25 V ■ ID ≤ 75 A ■ R DSon ≤ 6m Ω ■ Q gd = 5.6 nC (typ) Table 1: Pinning Pin Description Simplified outline Symbol 1 gate (G) SOT404 (D2PAK) SOT428 (DPAK) SOT533 (IPAK) 2 drain (D) [1] 3 source (S) mb mounting base; connected to drain mb mb mb S D G mbb076
9397 750 14707 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 18 April 2005 2 of 14 Philips Semiconductors PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET 3. Ordering information 4. Limiting values Table 2: Ordering information Type number Package Name Description Version PHB108NQ03LT D2PAK plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT404 PHD108NQ03LT DPAK plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT428 PHU108NQ03LT IPAK plastic single-ended package; 3 leads (in-line) SOT533 Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj≤ 175 °C - 25 V VDGR drain-gate voltage (DC) 25 °C ≤ Tj≤ 175 °C; RGS =2 0kΩ -2 5 V VGS gate-source voltage - ±20 V ID drain current (DC) T mb =2 5°C; VGS =5V ;Figure2 and3 -7 5 A Tmb = 100°C; VGS =5V ;Figure2 -7 5 A IDM peak drain current T mb =2 5°C; pulsed; tp ≤ 10 µs;Figure3 - 240 A Ptot total power dissipation T mb =2 5°C; Figure1 - 187 W Tstg storage temperature −55 +175 °C Tj junction temperature −55 +175 °C Source-drain diode I S source (diode forward) current (DC) Tmb =2 5°C - 75 A ISM peak source (diode forward) current Tmb =2 5°C; pulsed; tp ≤ 10 µs - 240 A Avalanche ruggedness E DS(AL)S non-repetitive drain-source avalanche energy unclamped inductive load; ID =4 3A ; tp = 0.25 ms; VDD ≤ 25 V; RGS =5 0Ω ; VGS = 10 V; starting at Tj=2 5°C - 180 mJ
9397 750 14707 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 18 April 2005 3 of 14 Philips Semiconductors PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET Fig 1. Normalized total power dissipation as a function of mounting base temperature Fig 2. Normalized continuous drain current as a function of mounting base temperature Tmb =2 5°C; IDM is single pulse; VGS =5V Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 03aa16 120 0 50 100 150 200 Tmb (°C) Pder (%) 03ar58 120 0 50 100 150 200 Tmb (°C) Ider (%) P der P tot P tot 25 C°() ID I D2 5 C°() 03ar59 102 103 1 10 10 2 VDS (V) ID (A) 10 µstp = DC 1 ms 100 µ s Limit RDSon = VDS / ID 10 ms
9397 750 14707 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 18 April 2005 4 of 14 Philips Semiconductors PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET 5. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit R th(j-mb) thermal resistance from junction to mounting baseFigure4 - - 0.8 K/W R th(j-a) thermal resistance from junction to ambient SOT404 mounted on a printed-circuit board; minimum footprint; vertical in still air - 50 - K/W SOT428 mounted on a printed-circuit board; minimum footprint; vertical in still air - 75 - K/W mounted on a printed-circuit board; vertical in still air; SOT404 minimum footprint - 50 - K/W SOT533 vertical in free air - 70 - K/W Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration 03ar60 10-2 10-1 10-5 10-4 10-3 10-2 10-1 1 tp (s) Zth(j-mb) (K/W) single pulse 0.2 0.1 0.05 δ = 0.5 0.02 tp T P t tp Tδ =
9397 750 14707 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 18 April 2005 5 of 14 Philips Semiconductors PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET 6. Characteristics Table 5: Characteristics Tj=2 5°C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V (BR)DSS drain-source breakdown voltage ID = 250µA; VGS =0V Tj=2 5°C 2 5 --V Tj= −55 °C 2 2 --V VGS(th) gate-source threshold voltage ID = 1 mA; VDS =V GS ;Figure9 and10 Tj=2 5°C 1 1.5 2 V IDSS drain-source leakage current V DS =2 5V ; VGS =0V Tj=2 5°C --1 µA Tj= 175°C - - 500 µA R G gate resistance f = 1 MHz - 1.2 - Ω IGSS gate-source leakage current V GS = ±10 V; VDS = 0 V - 0.02 100 nA R DSon drain-source on-state resistance VGS =5V ; ID =2 5A ;Figure6 and8 Tj=2 5°C - 6.7 7.5 m Ω Tj= 175°C - 12.1 13.5 m Ω VGS = 10 V; ID =2 5A ;Figure6 and8 - 5.3 6 m Ω Dynamic characteristics Q g(tot) total gate charge I D = 25 A; VDS =1 2V ; VGS = 4.5 V; Figure11 and12 - 16.3 - nC Q gs gate-source charge - 4 - nC Q gs1 pre-VGS(th) gate-source charge - 2.5 - nC Q gs2 post-VGS(th) gate-source charge - 1.5 - nC Q gd gate-drain (Miller) charge - 5.6 - nC Vplat plateau voltage - 2.4 - V Q g(tot) total gate charge I D = 0 A; VDS =0V ; VGS = 4.5 V - 12.5 - nC C iss input capacitance V GS =0V ; VDS = 12 V; f = 1 MHz; Figure14 -1 3 7 5 -p F C oss output capacitance - 640 - pF C rss reverse transfer capacitance - 250 - pF C iss input capacitance V GS =0V ; VDS = 0 V; f = 1 MHz - 2120 - pF td(on) turn-on delay time V DS =1 2V ; RL = 0.5Ω ; VGS = 4.5 V; R G = 5.6Ω -1 5 -n s tr rise time -3 8 -n s td(off) turn-off delay time - 32 - ns tf fall time -2 5 -n s Source-drain diode V SD source-drain (diode forward) voltage IS = 25 A; VGS =0V ;Figure13 - 0.86 1.2 V trr reverse recovery time I S = 20 A; dIS/dt =−100 A/µs; VGS =0V ; VR =2 5V -3 4 -n s Q r recovered charge - 21 - nC
9397 750 14707 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 18 April 2005 6 of 14 Philips Semiconductors PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET Tj=2 5°CT j=2 5°C Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. Drain-source on-state resistance as a function of drain current; typical values Tj=2 5°C and 175°C; VDS >ID × R DSon Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature 03ar61 0 0.2 0.4 0.6 0.8 1 V DS (V) ID (A) 3.5 4.5 2.5 10 5VGS (V) = 03ar62 0 2 04 06 08 0 ID (A) R DSon (mΩ ) 4.5 3.5 VGS (V) = 03ar63 01234 V GS (V) ID (A) Tj = 175 °C 25 °C 03af18 0.5 1.5 -60 0 60 120 180 Tj (°C) a a R DSon R DSon 25 C°()
9397 750 14707 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 18 April 2005 7 of 14 Philips Semiconductors PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET ID = 1 mA; VDS =V GS Tj=2 5°C; VDS =5V Fig 9. Gate-source threshold voltage as a function of junction temperature Fig 10. Sub-threshold drain current as a function of gate-source voltage ID = 25 A; VDS = 12 V and 19 V Fig 11. Gate-source voltage as a function of gate charge; typical values Fig 12. Gate charge waveform definitions 03aa33 0.5 1.5 2.5 -60 0 60 120 180 Tj (°C) VGS(th) (V) max typ min 03aa36 10-6 10-5 10-4 10-3 10-2 10-1 0123 VGS (V) ID (A) maxtypmin 03ar64 0 1 02 03 04 0 Q G (nC) VGS (V) ID = 25 A Tj = 25 °C VDS = 19 V12 V 003aaa508 VGS VGS(th) Q gs1 Q gs2 Q gd VDS Q g(tot) ID Q gs Vplat
9397 750 14707 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 18 April 2005 8 of 14 Philips Semiconductors PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET Tj=2 5°C and 175°C; VGS =0V V GS = 0 V; f = 1 MHz Fig 13. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values VDS =0V Fig 15. Input and reverse transfer capacitances as a function of gate-source voltage; typical values 03ar65 V SD (V) IS (A) Tj = 25 °C175 °C 03ar66 102 103 104 10-1 1 10 10 2 VDS (V) C (pF) C iss C oss C rss 03ar67 1000 2000 3000 4000 02468 1 0 V GS (V) C (pF) C iss C rss
9397 750 14707 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 18 April 2005 9 of 14 Philips Semiconductors PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET 7. Package outline Fig 16. Package outline SOT404 (D2PAK) UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm A 1 D 1 D max. E eL p H D Qc 2.54 2.60 2.20 15.80 14.80 2.90 2.1011 1.60 1.20 10.30 9.70 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 b DIMENSIONS (mm are the original dimensions) SOT404 0 2.5 5 mm scale Plastic single-ended surface mounted package (D2PAK); 3 leads (one lead cropped) SOT404 e e E b D 1 H D D Q Lp c A mounting base 04-10-13 05-02-11
9397 750 14707 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 18 April 2005 10 of 14 Philips Semiconductors PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET Fig 17. Package outline SOT428 (DPAK) REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT428 SC-63 TO-252 SOT428 05-02-09 05-02-11 DIMENSIONS (mm are the original dimensions) Plastic single-ended surface mounted package (DPAK); 3 leads (one lead cropped) A D 2 D 1 H D L e mounting base wAMb E b1 c y 0 5 10 mm scale UNIT mm 0.93 0.73 5.46 5.00 0.56 0.20 6.22 5.98 6.73 6.47 10.4 9.6 2.95 2.55 A 1 2.38 2.22 Ab 2 1.1 0.9 b1 e1 0.89 0.71 bc D 1 0.9 0.5 L2Ee 2.285 4.574.0 D 2 min 4.45 E 1 min 0.5 minH D Lw 0.2 y max 0.2 A
Philips Semiconductors PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET 9397 750 14707 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 18 April 2005 11 of 14 Fig 18. Package outline SOT533 (IPAK) REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT533 TO-251 SOT533 04-09-22 05-02-11 DIMENSIONS (mm are the original dimensions) Plastic single-ended package (IPAK); 3 leads (in-line) E 123 D 2 L A b c Q D 1 e w M mounting base 0 2.5 5 mm scale UNIT mm 0.89 0.71 0.89 0.71 0.56 0.46 6.23 5.97 6.73 6.47 2.285 BSC (1) 4.57 BSC (1) 9.6 9.2 A 1 2.38 2.22 A b cD 2 E e e1 5.21 5.00 E 1 1.10 0.96 D 1 L1(2) max 2.7 0.3 Lw 1.1 1.0 Q Notes 1. Basic spacing between centers. 2. Terminal dimensions are uncontrolled within zone L
9397 750 14707 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 18 April 2005 12 of 14 Philips Semiconductors PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET 8. Revision history Table 6: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes PHB_PHD_PHU108NQ03LT_3 20050418 Product data sheet 2004070095 9397 750 14707 PHP_PHB_PHD108NQ03LT -02 Modifications: • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors.
- Removal of PHP108NQ03LT
- Addition of PHU108NQ03LT
- Section 4 “Limiting values” ID , IDM , Ptot and ISM data corrected.
- Table5 “Characteristics”R DSon ,Q g(tot),Q gs,Q gd,Ciss,Coss,Crss,td(on),tr,td(off),tfand Q r test conditions and/or typical values modified.
- Table 5 “Characteristics” RG , Qgs1, Qgs2 and Vplat tests added.
- Table 5 “Characteristics” VGS(th), Ciss, Crss and Qg(tot)data added.
- Figure2,3,4,5,6,7,8,11,13 and14 modified.
- Figure12 and15 added. PHP_PHB_PHD108NQ03LT -02 20020911 Product data - 9397 750 10159 PHP_PHB_PHD108NQ03LT -01 PHP_PHB_PHD108NQ03LT -01 20011218 Product data - 9397 750 09065
Philips Semiconductors PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET 9397 750 14707 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 18 April 2005 13 of 14 9. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 10. Definitions Short-form specification —The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 11. Disclaimers Life support —These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes —Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 12. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. 13. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
© Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 18 April 2005 Document number: 9397 750 14707 Published in The Netherlands Philips Semiconductors PHB/PHD/PHU108NQ03LT N-channel TrenchMOS™ logic level FET 14. Contents